samv71-xult: Add support for the MRF24J40 radio and create a mrf24j40-starhub configuration. A few fixes to IPv6 and 6LoWPAN were required to have 6LoWPAN and Ethernet coexisting. Untested and expect some complexity in the bring-up.

arch/arm/src/samv7/sam_lowputc.c

@@ -364,9 +364,9 @@ void sam_lowsetup(void)
 #    warning The SYSIO Pin4 must be bound to PB4 to use USART1
 #  endif
 
-  uint32_t sysioreg = getreg32(SAM_MATRIX_CCFG_SYSIO);
+  regval  = getreg32(SAM_MATRIX_CCFG_SYSIO);
-  sysioreg |= MATRIX_CCFG_SYSIO_SYSIO4;
+  regval |= MATRIX_CCFG_SYSIO_SYSIO4;
-  putreg32(sysioreg, SAM_MATRIX_CCFG_SYSIO);
+  putreg32(regval, SAM_MATRIX_CCFG_SYSIO);
 
 #endif
 

configs/clicker2-stm32/src/stm32_mrf24j40.c

@@ -135,6 +135,7 @@ static struct stm32_priv_s g_mrf24j40_mb1_priv =
   .dev.attach  = stm32_attach_irq,
   .dev.enable  = stm32_enable_irq,
   .handler     = NULL,
+  .arg         = NULL,
   .intcfg      = GPIO_MB1_INT,
   .spidev      = 3,
 };
@@ -145,7 +146,9 @@ static struct stm32_priv_s g_mrf24j40_mb2_priv =
 {
   .dev.attach  = stm32_attach_irq,
   .dev.enable  = stm32_enable_irq,
-  .uint32_t    = GPIO_MB2_INT,
+  .handler     = NULL,
+  .arg         = NULL,
+  .intcfg      = GPIO_MB2_INT,
   .spidev      = 2,
 };
 #endif

configs/clicker2-stm32/src/stm32_spi.c

@@ -136,17 +136,18 @@ void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
 {
   spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 
-  switch(devid)
+  switch (devid)
-  {
+    {
 #ifdef CONFIG_IEEE802154_MRF24J40
-    case SPIDEV_IEEE802154(0):
+      case SPIDEV_IEEE802154(0):
-      /* Set the GPIO low to select and high to de-select */
+        /* Set the GPIO low to select and high to de-select */
-      stm32_gpiowrite(GPIO_MB1_CS, !selected);
+
-      break;
+        stm32_gpiowrite(GPIO_MB1_CS, !selected);
+        break;
 #endif
-    default:
+      default:
-      break;
+        break;
-  }
+    }
 }
 
 uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)

configs/samv71-xult/Kconfig

@@ -9,6 +9,37 @@ config SAMV71XULT_MXTXPLND
 	bool "MaXTouch Xplained connected"
 	default n
 
+config SAMV71XULT_CLICKSHIELD
+	bool "Mikroe Click Shield"
+	default n
+	---help---
+		In the mrf24j40-starhub configuration, a click shield from
+		MikroElectronika was used along with a Click "Bee" module.  The
+		click shield supports two click shields.
+
+config SAMV71XULT_MB1_SPI
+	bool
+	default n
+
+config SAMV71XULT_MB2_SPI
+	bool
+	default n
+
+choice
+	prompt "Bee mikroBUS"
+	depends on SAMV71XULT_CLICKSHIELD && IEEE802154_MRF24J40
+	default SAMV71XULT_MB1_BEE
+
+config SAMV71XULT_MB1_BEE
+	bool "MRF24J40 Bee in mikroBUS1"
+	select SAMV71XULT_MB1_SPI
+
+config SAMV71XULT_MB2_BEE
+	bool "MRF24J40 Bee in mikroBUS2"
+	select SAMV71XULT_MB2_SPI
+
+endchoice # Bee mikroBUS
+
 if SAMV71XULT_MXTXPLND
 
 choice

configs/samv71-xult/README.txt

@@ -25,6 +25,7 @@ Contents
   - maXTouch Xplained Pro
   - MCAN1 Loopback Test
   - SPI Slave
+  - Click Shield
   - Tickless OS
   - Debugging
   - Configurations
@@ -1437,6 +1438,61 @@ SPI Slave
 
   b) It will hog all of the CPU for the duration of the transfer).
 
+Click Shield
+============
+
+  In the mrf24j40-starhub configuration, a click shield from
+  MikroElectronika was used along with a Click "Bee" module.  The click
+  shield supports two click shields and the following tables describe the
+  relationship between the pins on each click shield, the Arduino
+  connector and the SAME70 pins.
+
+  --------- ---------------------- -------- --------- ------------------ ----------
+  mikroBUS1 Arduino                SAME70   mikroBUS2 Arduino            SAME70
+  --------- ---------------------- -------- --------- ------------------ ----------
+  AN        HD1 A0  AN0      Pin 1 AD0 PD26 AN        HD1 A1 AN1  Pin 2  AD1 PC31
+  RST       HD1 A3           Pin 4 AD3 PD30 RST       HD1 A2      Pin 3  AD2 PA19
+  CS        HD4 D10 SPI-SS   Pin 8 D10 PD25 CS        HD4 D9      Pin 9  D9  PC9
+  SCK       HD4 D13 SPI-SCK  Pin 5 D13 PD22 SCK       Same
+  MISO      HD4 D12 SPI-MISO Pin 6 D12 PD20 MISO      Same
+  MOSI      HD4 D11 SPI-MOSI Pin 7 D11 PD21 MOSI      Same
+  3.3V      N/A                             3.3V      N/A
+  GND       N/A                             GND       N/A
+  PWM       HD3 D6 PWMA      Pin 2 D6  PA2  PWM       HD3 D5 PWMB Pin 5  D5 PD11
+  INT       HD3 D2 INT0      Pin 6 D2  PA5  INT       HD3 D3 INT1 Pin 5  D3 PA6
+  RX        HD3 D0 HDR-RX*   Pin 8 D0  PD28 RX        Same
+  TX        HD3 D1 HDR-TX*   Pin 7 D1  PD20 TX        Same
+  SCL       HD1 A5 I2C-SCL   Pin 5 AD5 PE0  SDA       Same
+  SDA       HD1 A4 I2C-SDA   Pin 6 AD4 PC13 SCL       Same
+  5V        N/A                             5V        N/A
+  GND       N/A                             GND       N/A
+  --------- ---------------------- -------- --------- ------------------ ----------
+
+  * Depends upon setting of SW1, UART vs PROG.
+
+  --- ----- ------------------------------ ---------------------------------
+  PIN PORT  SHIELD FUNCTION                PIN CONFIGURATION
+  --- ----- ------------------------------ ---------------------------------
+  AD0 PD26  microBUS2 Analog TD            *** Not an AFE pin ***
+  AD1 PC31  microBUS2 Analog               AFE1_AD6   GPIO_AFE1_AD6
+  AD2 PA19  microBUS2 GPIO reset output
+  AD3 PD30  microBUS1 GPIO reset output
+  AD4 PC13  (both) I2C-SDA                 *** Does not support I2C SDA ***
+  AD5 PE0   (both) I2C-SCL                 *** Does not support I2C SCL ***
+
+  D0  PD28  (both) HDR_RX                  URXD3      GPIO_UART3_RXD
+  D1  PD30  (both) HDR_TX                  UTXD3      GPIO_UART3_TXD_1
+  D2  PA0   microBUS1 GPIO interrupt input
+  D3  PA6   microBUS2 GPIO interrupt input
+  D5  PD11  microBUS2 PWM                  PWMC0_H0
+  D6  PC19  microBUS1 PWN                  PWMC0_H2
+  D9  PC9   microBUS2 CS GPIO output
+  D10 PD25  microBUS1 CS GPIO output       SPI0_NPCS1
+  D11 PD21  (both) SPI-MOSI                SPI0_MOSI  GPIO_SPI0_MOSI
+  D12 PD20  (both) SPI-MISO                SPI0_MISO  GPIO_SPI0_MISO
+  D13 PD22  (both) SPI-SCK                 SPI0_SPCK  GPIO_SPI0_SPCK
+  --- ----- ------------------------------ ---------------------------------
+
 Tickless OS
 ===========
 
@@ -1791,6 +1847,49 @@ Configuration sub-directories
     STATUS:
     2017-01-30: Does not yet run correctly.
 
+  mrf24j40-starhub
+
+    This configuration implement a hub node in a 6LoWPAN start network.
+    It is intended for the us the mrf24j40-starpoint configuration with
+    the clicker2-stm32 configurations.  Essentially, the SAMV71-XULT
+    plays the roll of the hub in the configuration and the clicker2-stm32
+    boards are the endpoints in the start.
+
+    NOTES:
+    1. This configuration derives from the netnsh configuration, but adds
+       support for IPv6, 6LoWPAN, and the MRF24J40 IEEE 802.15.4 radio.
+
+    2. This configuration uses the Mikroe BEE MRF24j40 click boards and
+       connects to the SAMV71-XULT using a click shield as described above.
+
+    3. You must must have also have at least two clicker2-stm32 boards each
+       with an  MRF24J40 BEE click board in order to run these tests.
+
+    4. Telnet:  The clicker2-stm32 star point configuration supports the
+       Telnet daemon, but not the Telnet client; the star hub configuration
+       supports the Telnet client, but not the Telnet daemon.  Therefore,
+       the star hub can Telnet to any point in the star, the star endpoints
+       cannot initiate telnet sessions.
+
+    5. TCP and UDP Tests:  The same TCP and UDP tests as described for
+       the clicker2-stm32 mrf24j40-starpoint coniguration are supported on
+       the star endpoints, but NOT on the star hub.  Therefore, all network
+       testing is between endpoints with the hub acting, well, only like a
+       hub.
+
+       The nsh> dmesg command can be use at any time on any node to see
+       any debug output that you have selected.
+
+       Telenet sessions may be initiated only from the hub to a star
+       endpoint:
+
+         C: nsh> telnet <server-ip> <-- Runs the Telnet client
+
+       Where <server-ip> is the IP address of either the E1 or I2 endpoints.
+
+    STATUS:
+      2017-07-02:  Configurations added.  Not yet tested.
+
   mxtxplnd:
 
     Configures the NuttShell (nsh) located at examples/nsh.  There are five

configs/samv71-xult/include/board.h

@@ -300,7 +300,6 @@
 
 #define GPIO_UART3_TXD  GPIO_UART3_TXD_1
 
-
 /* - Arduino Communications.  Additional UART/USART connections are available
  *  on the Arduino Communications connection J505:
  *

configs/samv71-xult/mrf24j40-starhub/Make.defs

@@ -0,0 +1,128 @@
+############################################################################
+# configs/samv71-xult/mrf24j40-starhub/Make.defs
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_ARMV7M_DTCM),y)
+  LDSCRIPT = flash-dtcm.ld
+else
+  LDSCRIPT = flash-sram.ld
+endif
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION)
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -fno-strict-aliasing
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
+
+LDMODULEFLAGS = -r -e module_initialize
+ifeq ($(WINTOOL),y)
+  LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libc/modlib/gnu-elf.ld}"
+else
+  LDMODULEFLAGS += -T $(TOPDIR)/libc/modlib/gnu-elf.ld
+endif
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+

configs/samv71-xult/mrf24j40-starhub/SAVEconfig

@@ -0,0 +1,377 @@
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_BOARD_SAME70_XPLAINED=y
+CONFIG_ARCH_BOARD="same70-xplained"
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP_SAME70=y
+CONFIG_ARCH_CHIP_SAME70Q=y
+CONFIG_ARCH_CHIP_SAME70Q21=y
+CONFIG_ARCH_CHIP_SAMV7=y
+CONFIG_ARCH_CHIP="samv7"
+CONFIG_ARCH_CORTEXM7=y
+CONFIG_ARCH_DMA=y
+CONFIG_ARCH_DPFPU=y
+CONFIG_ARCH_FAMILY="armv7-m"
+CONFIG_ARCH_FPU=y
+CONFIG_ARCH_HAVE_BUTTONS=y
+CONFIG_ARCH_HAVE_CMNVECTOR=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+CONFIG_ARCH_HAVE_DPFPU=y
+CONFIG_ARCH_HAVE_FPU=y
+CONFIG_ARCH_HAVE_HEAPCHECK=y
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+CONFIG_ARCH_HAVE_I2CRESET=y
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_HAVE_IRQBUTTONS=y
+CONFIG_ARCH_HAVE_IRQPRIO=y
+CONFIG_ARCH_HAVE_LEDS=y
+CONFIG_ARCH_HAVE_MPU=y
+CONFIG_ARCH_HAVE_NET=y
+CONFIG_ARCH_HAVE_NETDEV_STATISTICS=y
+CONFIG_ARCH_HAVE_PHY=y
+CONFIG_ARCH_HAVE_RAMFUNCS=y
+CONFIG_ARCH_HAVE_RAMVECTORS=y
+CONFIG_ARCH_HAVE_RESET=y
+CONFIG_ARCH_HAVE_SDIO=y
+CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
+CONFIG_ARCH_HAVE_SPI_BITORDER=y
+CONFIG_ARCH_HAVE_SPI_CS_CONTROL=y
+CONFIG_ARCH_HAVE_STACKCHECK=y
+CONFIG_ARCH_HAVE_TICKLESS=y
+CONFIG_ARCH_HAVE_TIMEKEEPING=y
+CONFIG_ARCH_HAVE_TLS=y
+CONFIG_ARCH_HAVE_VFORK=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_ARCH_PHY_INTERRUPT=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_TOOLCHAIN_GNU=y
+CONFIG_ARCH="arm"
+CONFIG_ARM_HAVE_MPU_UNIFIED=y
+CONFIG_ARMV7M_CMNVECTOR=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_HAVE_DCACHE=y
+CONFIG_ARMV7M_HAVE_DTCM=y
+CONFIG_ARMV7M_HAVE_ICACHE=y
+CONFIG_ARMV7M_HAVE_ITCM=y
+CONFIG_ARMV7M_HAVE_STACKCHECK=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_LAZYFPU=y
+CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y
+CONFIG_AT24XX_ADDR=0x57
+CONFIG_AT24XX_EXTENDED=y
+CONFIG_AT24XX_EXTSIZE=160
+CONFIG_AT24XX_FREQUENCY=100000
+CONFIG_AT24XX_SIZE=2
+CONFIG_AT25_SPIFREQUENCY=20000000
+CONFIG_AT25_SPIMODE=0
+CONFIG_BOARD_INITIALIZE=y
+CONFIG_BOARD_LOOPSPERMSEC=51262
+CONFIG_BOOT_RUNFROMFLASH=y
+CONFIG_BUILD_FLAT=y
+CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+CONFIG_BUILTIN=y
+CONFIG_SAME70XPLND_CLICK_MB1_BEE=y
+CONFIG_SAME70XPLND_CLICK_MB1_SPI=y
+CONFIG_DEBUG_ALERT=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEV_CONSOLE=y
+CONFIG_DEV_NULL=y
+CONFIG_DISABLE_OS_API=y
+CONFIG_DISABLE_POLL=y
+CONFIG_DRIVERS_IEEE802154=y
+CONFIG_DRIVERS_WIRELESS=y
+CONFIG_EOL_IS_EITHER_CRLF=y
+CONFIG_ETH0_PHY_KSZ8081=y
+CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
+CONFIG_EXAMPLES_NSH=y
+CONFIG_FAT_LCNAMES=y
+CONFIG_FAT_LFN=y
+CONFIG_FAT_MAXFNAME=32
+CONFIG_FS_FAT=y
+CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
+CONFIG_FS_PROCFS=y
+CONFIG_FS_READABLE=y
+CONFIG_FS_WRITABLE=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_HOST_WINDOWS=y
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_IEEE802154_DEFAULT_EADDR=0x00fade00deadbeef
+CONFIG_IEEE802154_I8SAK_PRIORITY=100
+CONFIG_IEEE802154_I8SAK_STACKSIZE=2048
+CONFIG_IEEE802154_I8SAK=y
+CONFIG_IEEE802154_IND_IRQRESERVE=10
+CONFIG_IEEE802154_IND_PREALLOC=32
+CONFIG_IEEE802154_LIBMAC=y
+CONFIG_IEEE802154_LIBUTILS=y
+CONFIG_IEEE802154_MACDEV_RECVRPRIO=0
+CONFIG_IEEE802154_MACDEV=y
+CONFIG_IEEE802154_MRF24J40=y
+CONFIG_IEEE802154_NETDEV_LPWORK=y
+CONFIG_IEEE802154_NETDEV_RECVRPRIO=1
+CONFIG_IEEE802154_NETDEV=y
+CONFIG_INIT_ENTRYPOINT=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_IOB_BUFSIZE=128
+CONFIG_IOB_NBUFFERS=32
+CONFIG_IOB_NCHAINS=16
+CONFIG_IOB_THROTTLE=8
+CONFIG_LIB_BOARDCTL=y
+CONFIG_LIB_HOMEDIR="/"
+CONFIG_LIB_RAND_ORDER=1
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+CONFIG_LIBC_LONG_LONG=y
+CONFIG_LIBC_MAX_TMPFILE=32
+CONFIG_LIBC_NETDB=y
+CONFIG_LIBC_TMPDIR="/tmp"
+CONFIG_MAC802154_HPWORK=y
+CONFIG_MAC802154_NNOTIF=48
+CONFIG_MAC802154_NPANDESC=5
+CONFIG_MAC802154_NTXDESC=32
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MCU_SERIAL=y
+CONFIG_MM_IOB=y
+CONFIG_MM_REGIONS=1
+CONFIG_MMCSD_HAVECARDDETECT=y
+CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
+CONFIG_MMCSD_NSLOTS=1
+CONFIG_MMCSD_SDIO=y
+CONFIG_MMCSD=y
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MTD_AT24XX=y
+CONFIG_MTD_AT25=y
+CONFIG_MTD_CONFIG_ERASEDVALUE=0xff
+CONFIG_MTD_CONFIG=y
+CONFIG_MTD=y
+CONFIG_NAME_MAX=32
+CONFIG_NET_6LOWPAN_COMPRESSION_HC06=y
+CONFIG_NET_6LOWPAN_COMPRESSION_THRESHOLD=63
+CONFIG_NET_6LOWPAN_FRAG=y
+CONFIG_NET_6LOWPAN_FRAMELEN=127
+CONFIG_NET_6LOWPAN_MAX_MACTRANSMITS=4
+CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_0=0xaa
+CONFIG_NET_6LOWPAN_MAXADDRCONTEXT_PREFIX_0_1=0xaa
+CONFIG_NET_6LOWPAN_MAXADDRCONTEXT=1
+CONFIG_NET_6LOWPAN_MAXAGE=20
+CONFIG_NET_6LOWPAN_MTU=1294
+CONFIG_NET_6LOWPAN_TCP_RECVWNDO=1220
+CONFIG_NET_6LOWPAN=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_MTU=590
+CONFIG_NET_ETH_TCP_RECVWNDO=536
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_GUARDSIZE=2
+CONFIG_NET_HAVE_STAR=y
+CONFIG_NET_HOSTNAME="MRF24J40-Hub"
+CONFIG_NET_IPFORWARD=y
+# CONFIG_NET_IPv4 is not set
+CONFIG_NET_IPv6_NCONF_ENTRIES=8
+CONFIG_NET_IPv6=y
+CONFIG_NET_MAX_LISTENPORTS=20
+CONFIG_NET_NACTIVESOCKETS=16
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_STAR=y
+CONFIG_NET_STARHUB=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP_CONNS=8
+CONFIG_NET_TCP_NWRBCHAINS=8
+CONFIG_NET_TCP_READAHEAD=y
+CONFIG_NET_TCP_RECVDELAY=0
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_UDP_CHECKSUMS=y
+CONFIG_NET_UDP_CONNS=8
+CONFIG_NET_UDP_READAHEAD=y
+CONFIG_NET_UDP=y
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT_ENTRIES=8
+CONFIG_NETDB_DNSCLIENT_LIFESEC=3600
+CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=96
+CONFIG_NETDB_DNSCLIENT_NAMESIZE=32
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETDEV_IOCTL=y
+CONFIG_NETDEV_LATEINIT=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETDEV_TELNET=y
+CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETDEVICES=y
+CONFIG_NETUTILS_NETLIB=y
+CONFIG_NETUTILS_TELNETC=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NETUTILS_TFTPC=y
+CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_ARGCAT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_CMDOPT_HEXDUMP=y
+CONFIG_NSH_CMDPARMS=y
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_CONSOLE=y
+CONFIG_NSH_DISABLE_DATE=y
+CONFIG_NSH_DISABLE_GET=y
+CONFIG_NSH_DISABLE_LOSMART=y
+CONFIG_NSH_DISABLE_PRINTF=y
+CONFIG_NSH_DISABLE_PUT=y
+CONFIG_NSH_DISABLE_WGET=y
+CONFIG_NSH_DRIPADDR=0x0a000001
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_IOBUFFER_SIZE=512
+CONFIG_NSH_IPADDR=0x0a000002
+CONFIG_NSH_LIBRARY=y
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_MACADDR=0x00fade00deadbeef
+CONFIG_NSH_MAX_ROUNDTRIP=20
+CONFIG_NSH_MAXARGUMENTS=6
+CONFIG_NSH_MMCSDMINOR=0
+CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_NESTDEPTH=3
+CONFIG_NSH_NETINIT_MONITOR=y
+CONFIG_NSH_NETINIT_RETRYMSEC=2000
+CONFIG_NSH_NETINIT_SIGNO=18
+CONFIG_NSH_NETINIT_THREAD_PRIORITY=80
+CONFIG_NSH_NETINIT_THREAD_STACKSIZE=1568
+CONFIG_NSH_NETINIT_THREAD=y
+CONFIG_NSH_NETINIT=y
+CONFIG_NSH_NETLOCAL=y
+CONFIG_NSH_NETMASK=0xffffff00
+CONFIG_NSH_NOMAC=y
+CONFIG_NSH_PROC_MOUNTPOINT="/proc"
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_SWMAC=y
+CONFIG_NSH_TELNET=y
+CONFIG_NSH_TELNETD_CLIENTPRIO=100
+CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048
+CONFIG_NSH_TELNETD_DAEMONPRIO=100
+CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048
+CONFIG_NSH_TELNETD_PORT=23
+CONFIG_NSH_WGET_USERAGENT="NuttX/6.xx.x (; http://www.nuttx.org/)"
+CONFIG_NSOCKET_DESCRIPTORS=8
+CONFIG_NUNGET_CHARS=2
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=32
+CONFIG_PTHREAD_MUTEX_ROBUST=y
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_RAM_SIZE=393216
+CONFIG_RAM_START=0x20400000
+CONFIG_RAMLOG_BUFSIZE=8192
+CONFIG_RAMLOG_NONBLOCKING=y
+CONFIG_RAMLOG_NPOLLWAITERS=4
+CONFIG_RAMLOG_SYSLOG=y
+CONFIG_RAMLOG=y
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_ECHO=y
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SAMV7_EMAC_HPWORK=y
+CONFIG_SAMV7_EMAC=y
+CONFIG_SAMV7_EMAC0_AUTONEG=y
+CONFIG_SAMV7_EMAC0_ISETH0=y
+CONFIG_SAMV7_EMAC0_NRXBUFFERS=16
+CONFIG_SAMV7_EMAC0_NTXBUFFERS=8
+CONFIG_SAMV7_EMAC0_PHYADDR=1
+CONFIG_SAMV7_EMAC0_PHYSR_100FD=0x6
+CONFIG_SAMV7_EMAC0_PHYSR_100HD=0x2
+CONFIG_SAMV7_EMAC0_PHYSR_10FD=0x5
+CONFIG_SAMV7_EMAC0_PHYSR_10HD=0x1
+CONFIG_SAMV7_EMAC0_PHYSR_ALTCONFIG=y
+CONFIG_SAMV7_EMAC0_PHYSR_ALTMODE=0x7
+CONFIG_SAMV7_EMAC0_PHYSR=30
+CONFIG_SAMV7_EMAC0_RMII=y
+CONFIG_SAMV7_EMAC0=y
+CONFIG_SAMV7_ERASE_ENABLE=y
+CONFIG_SAMV7_GPIO_IRQ=y
+CONFIG_SAMV7_GPIOA_IRQ=y
+CONFIG_SAMV7_GPIOC_IRQ=y
+CONFIG_SAMV7_HAVE_EBI=y
+CONFIG_SAMV7_HAVE_HSMCI0=y
+CONFIG_SAMV7_HAVE_MCAN1=y
+CONFIG_SAMV7_HAVE_SDRAMC=y
+CONFIG_SAMV7_HAVE_SPI0=y
+CONFIG_SAMV7_HAVE_SPI1=y
+CONFIG_SAMV7_HAVE_TWIHS2=y
+CONFIG_SAMV7_HAVE_USART0=y
+CONFIG_SAMV7_HAVE_USART1=y
+CONFIG_SAMV7_HAVE_USART2=y
+CONFIG_SAMV7_HAVE_USBHS=y
+CONFIG_SAMV7_HSMCI_DMA=y
+CONFIG_SAMV7_HSMCI=y
+CONFIG_SAMV7_HSMCI0=y
+CONFIG_SAMV7_JTAG_FULL_ENABLE=y
+CONFIG_SAMV7_TWIHS0_FREQUENCY=100000
+CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1
+CONFIG_SAMV7_TWIHS0=y
+# CONFIG_SAMV7_UART0 is not set
+# CONFIG_SAMV7_UART1 is not set
+# CONFIG_SAMV7_UART2 is not set
+# CONFIG_SAMV7_UART3 is not set
+# CONFIG_SAMV7_UART4 is not set
+CONFIG_SAMV7_USART1=y
+CONFIG_SAMV7_XDMAC=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_HPWORKPERIOD=50000
+CONFIG_SCHED_HPWORKPRIORITY=224
+CONFIG_SCHED_HPWORKSTACKSIZE=2048
+CONFIG_SCHED_LPNTHREADS=1
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_LPWORKPERIOD=50000
+CONFIG_SCHED_LPWORKPRIORITY=160
+CONFIG_SCHED_LPWORKSTACKSIZE=2048
+CONFIG_SCHED_WAITPID=y
+CONFIG_SCHED_WORKQUEUE=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SDIO_BLOCKSETUP=y
+CONFIG_SDIO_DMA=y
+CONFIG_SERIAL_CONSOLE=y
+CONFIG_SERIAL_NPOLLWAITERS=2
+CONFIG_SERIAL=y
+CONFIG_SIG_SIGALARM=3
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGWORK=17
+CONFIG_SPI_EXCHANGE=y
+CONFIG_SPI=y
+CONFIG_STANDARD_SERIAL=y
+CONFIG_START_DAY=1
+CONFIG_START_MONTH=7
+CONFIG_START_YEAR=2017
+CONFIG_STDIO_BUFFER_SIZE=64
+CONFIG_STDIO_LINEBUFFER=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_SYSTEM_TELNET_CLIENT=y
+CONFIG_SYSTEM_TELNET_CLIENT_PRIORITY=100
+CONFIG_SYSTEM_TELNET_CLIENT_STACKSIZE=2048
+CONFIG_TASK_NAME_SIZE=31
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048
+CONFIG_TELNET_RXBUFFER_SIZE=256
+CONFIG_TELNET_TXBUFFER_SIZE=256
+CONFIG_TOOLCHAIN_WINDOWS=y
+CONFIG_USART1_2STOP=0
+CONFIG_USART1_BAUD=115200
+CONFIG_USART1_BITS=8
+CONFIG_USART1_PARITY=0
+CONFIG_USART1_RXBUFSIZE=256
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USART1_SERIALDRIVER=y
+CONFIG_USART1_TXBUFSIZE=256
+CONFIG_USEC_PER_TICK=10000
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_WDOG_INTRESERVE=4
+CONFIG_WEBCLIENT_TIMEOUT=10
+CONFIG_WINDOWS_CYGWIN=y
+CONFIG_WIRELESS_IEEE802154=y
+CONFIG_WIRELESS=y

configs/samv71-xult/src/Makefile

@@ -1,7 +1,7 @@
 ############################################################################
 # configs/samv71-xult/src/Makefile
 #
-#   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -115,4 +115,8 @@ CSRCS += sam_maxtouch.c sam_atmxtconfig.c
 endif
 endif
 
+ifeq ($(CONFIG_IEEE802154_MRF24J40),y)
+CSRCS += sam_mrf24j40.c
+endif
+
 include $(TOPDIR)/configs/Board.mk

configs/samv71-xult/src/sam_autoleds.c

@@ -41,7 +41,7 @@
  *
  *   ------ ----------- ---------------------
  *   SAMV71 Function    Shared functionality
- *   PIO
+ *   GPIO
  *   ------ ----------- ---------------------
  *   PA23   Yellow LED0 EDBG GPIO
  *   PC09   Yellow LED1 LCD, and Shield
@@ -103,7 +103,7 @@
 
 void board_autoled_initialize(void)
 {
-  /* Configure LED PIOs for output */
+  /* Configure LED GPIOs for output */
 
   sam_configgpio(GPIO_LED0);
   sam_configgpio(GPIO_LED1);

configs/samv71-xult/src/sam_buttons.c

@@ -146,7 +146,7 @@ void board_button_initialize(void)
   regval |= MATRIX_CCFG_SYSIO_SYSIO12;
   putreg32(regval, SAM_MATRIX_CCFG_SYSIO);
 
-  /* Configure button PIOs */
+  /* Configure button GPIOs */
 
   (void)sam_configgpio(GPIO_SW0);
   (void)sam_configgpio(GPIO_SW1);

configs/samv71-xult/src/sam_hsmci.c

@@ -84,8 +84,8 @@
 struct sam_hsmci_state_s
 {
   struct sdio_dev_s *hsmci;   /* R/W device handle */
-  gpio_pinset_t cdcfg;        /* Card detect PIO pin configuration */
+  gpio_pinset_t cdcfg;        /* Card detect GPIO pin configuration */
-  gpio_pinset_t pwrcfg;       /* Power PIO pin configuration */
+  gpio_pinset_t pwrcfg;       /* Power GPIO pin configuration */
   uint8_t irq;                /* Interrupt number (same as pid) */
   uint8_t slotno;             /* Slot number */
   bool cd;                    /* TRUE: card is inserted */
@@ -126,7 +126,7 @@ bool sam_cardinserted_internal(struct sam_hsmci_state_s *state)
 {
   bool inserted;
 
-  /* Get the state of the PIO pin */
+  /* Get the state of the GPIO pin */
 
   inserted = sam_gpioread(state->cdcfg);
   mcinfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES");
@@ -189,7 +189,7 @@ static int sam_hsmci0_cardetect(int irq, void *regs, FAR void *arg)
  * Name: sam_hsmci_state
  *
  * Description:
- *   Initialize HSMCI PIOs.
+ *   Initialize HSMCI GPIOs.
  *
  ****************************************************************************/
 
@@ -230,7 +230,7 @@ int sam_hsmci_initialize(int slotno, int minor)
       return -EINVAL;
     }
 
-  /* Initialize card-detect, write-protect, and power enable PIOs */
+  /* Initialize card-detect, write-protect, and power enable GPIOs */
 
   sam_configgpio(state->cdcfg);
   sam_dumpgpio(state->cdcfg, "HSMCI Card Detect");
@@ -297,7 +297,7 @@ bool sam_cardinserted(int slotno)
       return false;
     }
 
-  /* Return the state of the PIO pin */
+  /* Return the state of the GPIO pin */
 
   return sam_cardinserted_internal(state);
 }

configs/samv71-xult/src/sam_maxtouch.c

@@ -92,15 +92,15 @@ struct sama5d4ek_tscinfo_s
  * Private Function Prototypes
  ****************************************************************************/
 
-/* IRQ/PIO access callbacks.  These operations all hidden behind
+/* IRQ/GPIO access callbacks.  These operations all hidden behind
- * callbacks to isolate the maXTouch driver from differences in PIO
+ * callbacks to isolate the maXTouch driver from differences in GPIO
  * interrupt handling by varying boards and MCUs.  If possible,
  * interrupts should be configured on both rising and falling edges
  * so that contact and loss-of-contact events can be detected.
  *
- *   attach  - Attach the maXTouch interrupt handler to the PIO interrupt
+ *   attach  - Attach the maXTouch interrupt handler to the GPIO interrupt
- *   enable  - Enable or disable the PIO interrupt
+ *   enable  - Enable or disable the GPIO interrupt
- *   clear   - Acknowledge/clear any pending PIO interrupt
+ *   clear   - Acknowledge/clear any pending GPIO interrupt
  */
 
 static int  mxt_attach(FAR const struct mxt_lower_s *lower, mxt_handler_t isr,
@@ -141,15 +141,15 @@ static struct sama5d4ek_tscinfo_s g_mxtinfo =
  ****************************************************************************/
 
 /****************************************************************************
- * IRQ/PIO access callbacks.  These operations all hidden behind
+ * IRQ/GPIO access callbacks.  These operations all hidden behind
- * callbacks to isolate the maXTouch driver from differences in PIO
+ * callbacks to isolate the maXTouch driver from differences in GPIO
  * interrupt handling by varying boards and MCUs.  If possible,
  * interrupts should be configured on both rising and falling edges
  * so that contact and loss-of-contact events can be detected.
  *
- *   attach  - Attach the maXTouch interrupt handler to the PIO interrupt
+ *   attach  - Attach the maXTouch interrupt handler to the GPIO interrupt
- *   enable  - Enable or disable the PIO interrupt
+ *   enable  - Enable or disable the GPIO interrupt
- *   clear   - Acknowledge/clear any pending PIO interrupt
+ *   clear   - Acknowledge/clear any pending GPIO interrupt
  *
  ****************************************************************************/
 

configs/samv71-xult/src/sam_mrf24j40.c

@@ -0,0 +1,323 @@
+/****************************************************************************
+ * configs/samv71-xult/src/sam_mrf24j40.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt, All rights reserver
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <stdint.h>
+#include <errno.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/wireless/ieee802154/ieee802154_mac.h>
+#include <nuttx/wireless/ieee802154/mrf24j40.h>
+
+#include "sam_gpio.h"
+#include "sam_spi.h"
+
+#include "samv71-xult.h"
+
+#ifdef HAVE_MRF24J40
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct sam_priv_s
+{
+  struct mrf24j40_lower_s dev;
+  uint32_t intcfg;
+  uint8_t irq;
+  uint8_t spidev;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* IRQ/GPIO access callbacks.  These operations all hidden behind callbacks
+ * to isolate the MRF24J40 driver from differences in GPIO interrupt handling
+ * varying boards and MCUs.
+ *
+ *   irq_attach - Attach the MRF24J40 interrupt handler to the GPIO
+                  interrupt
+ *   irq_enable - Enable or disable the GPIO interrupt
+ */
+
+static int  sam_attach_irq(FAR const struct mrf24j40_lower_s *lower,
+                           xcpt_t handler, FAR void *arg);
+static void sam_enable_irq(FAR const struct mrf24j40_lower_s *lower,
+                           bool state);
+static int  sam_mrf24j40_devsetup(FAR struct sam_priv_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* A reference to a structure of this type must be passed to the MRF24J40
+ * driver.  This structure provides information about the configuration
+ * of the MRF24J40 and provides some board-specific hooks.
+ *
+ * Memory for this structure is provided by the caller.  It is not copied
+ * by the driver and is presumed to persist while the driver is active. The
+ * memory must be writable because, under certain circumstances, the driver
+ * may modify frequency or X plate resistance values.
+ */
+
+#ifdef CONFIG_SAMV71XULT_MB1_BEE
+static struct sam_priv_s g_mrf24j40_mb1_priv =
+{
+  .dev.attach  = sam_attach_irq,
+  .dev.enable  = sam_enable_irq,
+  .intcfg      = CLICK_MB1_INTR,
+  .irq         = IRQ_MB1,
+  .spidev      = 0,
+};
+#endif
+
+#ifdef CONFIG_SAMV71XULT_MB2_BEE
+static struct sam_priv_s g_mrf24j40_mb2_priv =
+{
+  .dev.attach  = sam_attach_irq,
+  .dev.enable  = sam_enable_irq,
+  .intcfg      = CLICK_MB2_INTR,
+  .irq         = IRQ_MB2,
+  .spidev      = 0,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* IRQ/GPIO access callbacks.  These operations all hidden behind
+ * callbacks to isolate the MRF24J40 driver from differences in GPIO
+ * interrupt handling by varying boards and MCUs.  If possible,
+ * interrupts should be configured on both rising and falling edges
+ * so that contact and loss-of-contact events can be detected.
+ *
+ *   irq_attach       - Attach the MRF24J40 interrupt handler to the GPIO
+ *                      interrupt
+ *   irq_enable       - Enable or disable the GPIO interrupt
+ */
+
+static int sam_attach_irq(FAR const struct mrf24j40_lower_s *lower,
+                            xcpt_t handler, FAR void *arg)
+{
+  FAR struct sam_priv_s *priv = (FAR struct sam_priv_s *)lower;
+  int ret;
+
+  DEBUGASSERT(priv != NULL);
+
+  ret = irq_attach(priv->irq, handler, arg);
+  if (ret < 0)
+    {
+      wlerr("ERROR: Failed to attach WM8904 interrupt: %d\n", ret);
+    }
+
+  return ret;
+}
+
+static void sam_enable_irq(FAR const struct mrf24j40_lower_s *lower,
+                             bool state)
+{
+  FAR struct sam_priv_s *piv = (FAR struct sam_priv_s *)lower;
+  static bool enabled;
+  irqstate_t flags;
+
+  /* The caller should not attempt to enable interrupts if the handler
+   * has not yet been 'attached'
+   */
+
+  wlinfo("state:%d\n", (int)state);
+  DEBUGASSERT(priv != NULL);
+
+  /* Has the interrupt state changed */
+
+  flags = enter_critical_section();
+  if (state != enabled)
+    {
+      /* Enable or disable interrupts */
+
+      if (state)
+        {
+          wlinfo("Enabling\n");
+          sam_gpioirqenable(priv->irq);
+          enabled = true;
+        }
+      else
+        {
+          wlinfo("Disabling\n");
+          sam_gpioirqdisable(priv->irq);
+          enabled = false;
+        }
+    }
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: sam_mrf24j40_devsetup
+ *
+ * Description:
+ *   Initialize one the MRF24J40 device in one mikroBUS slot
+ *
+ * Returned Value:
+ *   Zero is returned on success.  Otherwise, a negated errno value is
+ *   returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+static int sam_mrf24j40_devsetup(FAR struct sam_priv_s *priv)
+{
+  FAR struct ieee802154_radio_s *radio;
+  MACHANDLE mac;
+  FAR struct spi_dev_s *spi;
+  int ret;
+
+  /* Configure the interrupt pin */
+
+  (void)sam_configgpio(priv->intcfg);
+  sam_gpioirq(priv->intcfg);
+
+  /* Initialize the SPI bus and get an instance of the SPI interface */
+
+  spi = sam_spibus_initialize(priv->spidev);
+  if (spi == NULL)
+    {
+      wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev);
+      return -ENODEV;
+    }
+
+  /* Initialize and register the SPI MRF24J40 device */
+
+  radio = mrf24j40_init(spi, &priv->dev);
+  if (radio == NULL)
+    {
+      wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev);
+      return -ENODEV;
+    }
+
+  /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */
+
+  mac = mac802154_create(radio);
+  if (mac == NULL)
+    {
+      wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n");
+      return -ENODEV;
+    }
+
+#ifdef CONFIG_IEEE802154_NETDEV
+  /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN
+   * network interface by wrapping the MAC intrface instance in a
+   * network device driver via mac802154dev_register().
+   */
+
+  ret = mac802154netdev_register(mac);
+  if (ret < 0)
+    {
+      wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n",
+            0, ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_IEEE802154_MACDEV
+  /* If want to call these APIs from userspace, you have to wrap the MAC
+   * interface in a character device viamac802154dev_register().
+   */
+
+  ret = mac802154dev_register(mac, 0);
+  if (ret < 0)
+    {
+      wlerr("ERROR: Failed to register the MAC character driver /dev/ieee%d: %d\n",
+            0, ret);
+      return ret;
+    }
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam_mrf24j40_initialize
+ *
+ * Description:
+ *   Initialize the MRF24J40 device.
+ *
+ * Returned Value:
+ *   Zero is returned on success.  Otherwise, a negated errno value is
+ *   returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int sam_mrf24j40_initialize(void)
+{
+  int ret;
+
+#ifdef CONFIG_SAMV71XULT_MB1_BEE
+  wlinfo("Configuring BEE in mikroBUS1\n");
+
+  ret = sam_mrf24j40_devsetup(&g_mrf24j40_mb1_priv);
+  if (ret < 0)
+    {
+      wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_SAMV71XULT_MB2_BEE
+  wlinfo("Configuring BEE in mikroBUS2\n");
+
+  ret = sam_mrf24j40_devsetup(&g_mrf24j40_mb2_priv);
+  if (ret < 0)
+    {
+      wlerr("ERROR: Failed to initialize BD in mikroBUS2: %d\n", ret);
+    }
+#endif
+
+  UNUSED(ret);
+  return OK;
+}
+#endif /* HAVE_MRF24J40 */

configs/samv71-xult/src/sam_spi.c

@@ -63,13 +63,24 @@
  * Name: sam_spidev_initialize
  *
  * Description:
- *   Called to configure SPI chip select PIO pins for the SAMV71-XULT board.
+ *   Called to configure SPI chip select GPIO pins for the SAMV71-XULT board.
  *
  ************************************************************************************/
 
 void sam_spidev_initialize(void)
 {
 #ifdef CONFIG_SAMV7_SPI0_MASTER
+
+#ifdef CONFIG_SAMV71XULT_MB1_SPI
+  /* Enable chip select for mikroBUS1 */
+
+  (void)stm32_configgpio(CLICK_MB1_CS);
+#endif
+#ifdef CONFIG_SAMV71XULT_MB2_SPI
+  /* Enable chip select for mikroBUS2 */
+
+  (void)stm32_configgpio(CLICK_MB2_CS);
+
 #endif
 
 #ifdef CONFIG_SAMV7_SPI0_SLAVE
@@ -101,10 +112,10 @@ void sam_spidev_initialize(void)
  *      pins.
  *   2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in your board-
  *      specific logic.  These functions will perform chip selection and
- *      status operations using PIOs in the way your board is configured.
+ *      status operations using GPIOs in the way your board is configured.
  *   2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
  *      sam_spi[0|1]cmddata() functions in your board-specific logic.  This
- *      function will perform cmd/data selection operations using PIOs in
+ *      function will perform cmd/data selection operations using GPIOs in
  *      the way your board is configured.
  *   3. Add a call to sam_spibus_initialize() in your low level application
  *      initialization logic
@@ -119,16 +130,16 @@ void sam_spidev_initialize(void)
  * Name: sam_spi[0|1]select
  *
  * Description:
- *   PIO chip select pins may be programmed by the board specific logic in
+ *   GPIO chip select pins may be programmed by the board specific logic in
  *   one of two different ways.  First, the pins may be programmed as SPI
  *   peripherals.  In that case, the pins are completely controlled by the
  *   SPI driver.  This method still needs to be provided, but it may be only
  *   a stub.
  *
- *   An alternative way to program the PIO chip select pins is as a normal
+ *   An alternative way to program the GPIO chip select pins is as a normal
- *   PIO output.  In that case, the automatic control of the CS pins is
+ *   GPIO output.  In that case, the automatic control of the CS pins is
  *   bypassed and this function must provide control of the chip select.
- *   NOTE:  In this case, the PIO output pin does *not* have to be the
+ *   NOTE:  In this case, the GPIO output pin does *not* have to be the
  *   same as the NPCS pin normal associated with the chip select number.
  *
  * Input Parameters:
@@ -143,12 +154,32 @@ void sam_spidev_initialize(void)
 #ifdef CONFIG_SAMV7_SPI0_MASTER
 void sam_spi0select(uint32_t devid, bool selected)
 {
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+
+  switch (devid)
+    {
+#ifdef CONFIG_IEEE802154_MRF24J40
+      case SPIDEV_IEEE802154(0):
+        /* Set the GPIO low to select and high to de-select */
+
+#if defined(CONFIG_SAMV71XULT_MB1_BEE)
+        stm32_gpiowrite(CLICK_MB1_CS, !selected);
+#elif defined(CONFIG_SAMV71XULT_MB2_BEE)
+        stm32_gpiowrite(CLICK_MB2_CS, !selected);
+#endif
+        break;
+#endif
+
+      default:
+        break;
+    }
 }
 #endif
 
 #ifdef CONFIG_SAMV7_SPI1_MASTER
 void sam_spi1select(uint32_t devid, bool selected)
 {
+  spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 #endif
 

configs/samv71-xult/src/sam_userleds.c

@@ -66,7 +66,7 @@
 
 void board_userled_initialize(void)
 {
-  /* Configure LED PIOs for output */
+  /* Configure LED GPIOs for output */
 
   sam_configgpio(GPIO_LED0);
   sam_configgpio(GPIO_LED1);

configs/samv71-xult/src/sam_wm8904.c

@@ -87,14 +87,14 @@ struct samv71xult_mwinfo_s
  * Private Function Prototypes
  ****************************************************************************/
 
-/* IRQ/PIO access callbacks.  These operations all hidden behind
+/* IRQ/GPIO access callbacks.  These operations all hidden behind
- * callbacks to isolate the WM8904 driver from differences in PIO
+ * callbacks to isolate the WM8904 driver from differences in GPIO
  * interrupt handling by varying boards and MCUs.  If possible,
  * interrupts should be configured on both rising and falling edges
  * so that contact and loss-of-contact events can be detected.
  *
- *   attach  - Attach the WM8904 interrupt handler to the PIO interrupt
+ *   attach  - Attach the WM8904 interrupt handler to the GPIO interrupt
- *   enable  - Enable or disable the PIO interrupt
+ *   enable  - Enable or disable the GPIO interrupt
  */
 
 static int  wm8904_attach(FAR const struct wm8904_lower_s *lower,
@@ -136,15 +136,15 @@ static struct samv71xult_mwinfo_s g_wm8904info =
  ****************************************************************************/
 
 /****************************************************************************
- * IRQ/PIO access callbacks.  These operations all hidden behind
+ * IRQ/GPIO access callbacks.  These operations all hidden behind
- * callbacks to isolate the WM8904 driver from differences in PIO
+ * callbacks to isolate the WM8904 driver from differences in GPIO
  * interrupt handling by varying boards and MCUs.  If possible,
  * interrupts should be configured on both rising and falling edges
  * so that contact and loss-of-contact events can be detected.
  *
- *   attach  - Attach the WM8904 interrupt handler to the PIO interrupt
+ *   attach  - Attach the WM8904 interrupt handler to the GPIO interrupt
- *   enable  - Enable or disable the PIO interrupt
+ *   enable  - Enable or disable the GPIO interrupt
- *   clear   - Acknowledge/clear any pending PIO interrupt
+ *   clear   - Acknowledge/clear any pending GPIO interrupt
  *
  ****************************************************************************/
 

configs/samv71-xult/src/samv71-xult.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * configs/samv71-xult/src/samv71-xult.h
  *
- *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,7 @@
 #define HAVE_RTC_PCF85263    1
 #define HAVE_I2CTOOL         1
 #define HAVE_LED_DRIVER      1
+#define HAVE_MRF24J40        1
 
 /* HSMCI */
 /* Can't support MMC/SD if the card interface is not enabled */
@@ -87,10 +88,10 @@
 #  undef HAVE_HSMCI
 #endif
 
-/* We need PIO interrupts on GPIOD to support card detect interrupts */
+/* We need GPIO interrupts on GPIOD to support card detect interrupts */
 
 #if defined(HAVE_HSMCI) && !defined(CONFIG_SAMV7_GPIOD_IRQ)
-#  warning PIOD interrupts not enabled.  No MMC/SD support.
+#  warning GPIOD interrupts not enabled.  No MMC/SD support.
 #  undef HAVE_HSMCI
 #endif
 
@@ -375,6 +376,24 @@
 #  endif
 #endif
 
+/* Check if the MRF24J40 is supported in this configuration */
+
+#ifndef CONFIG_IEEE802154_MRF24J40
+#  undef HAVE_MRF24J40
+#endif
+
+#ifndef CONFIG_SAMV71XULT_CLICKSHIELD
+#  undef HAVE_MRF24J40
+#endif
+
+#ifndef CONFIG_SAMV7_SPI0_MASTER
+#  undef HAVE_MRF24J40
+#endif
+
+#ifndef CONFIG_SAMV7_GPIOA_IRQ
+#  undef HAVE_MRF24J40
+#endif
+
 /* SAMV71-XULT GPIO Pin Definitions *************************************************/
 
 /* Ethernet MAC.
@@ -419,7 +438,7 @@
  *
  *   ------ ----------- ---------------------
  *   SAMV71 Function    Shared functionality
- *   PIO
+ *   GPIO
  *   ------ ----------- ---------------------
  *   PA23   Yellow LED0 EDBG GPIO
  *   PC09   Yellow LED1 LCD, and Shield
@@ -440,7 +459,7 @@
  *
  *   ------ ----------- ---------------------
  *   SAMV71 Function    Shared functionality
- *   PIO
+ *   GPIO
  *   ------ ----------- ---------------------
  *   RESET  RESET       Trace, Shield, and EDBG
  *   PA09   SW0         EDBG GPIO and Camera
@@ -503,7 +522,7 @@
 /* WM8904 Audio Codec ***************************************************************/
 /* SAMV71 Interface        WM8904 Interface
  * ---- ------------ ------- ----------------------------------
- * PIO  Usage        Pin     Function
+ * GPIO Usage        Pin     Function
  * ---- ------------ ------- ----------------------------------
  * PA3  TWD0         SDA     I2C control interface, data line
  * PA4  TWCK0        SCLK    I2C control interface, clock line
@@ -522,8 +541,8 @@
  * interrupt on the high level.
  */
 
-#define GPIO_INT_WM8904    (PIO_INPUT | PIO_CFG_DEFAULT | PIO_CFG_DEGLITCH | \
+#define GPIO_INT_WM8904    (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_CFG_DEGLITCH | \
-                            PIO_INT_HIGHLEVEL | PIO_PORT_PIOD | PIO_PIN11)
+                            GPIO_INT_HIGHLEVEL | GPIO_PORT_PIOD | GPIO_PIN11)
 #define IRQ_INT_WM8904     SAM_IRQ_PD11
 
 /* The MW8904 communicates on TWI0, I2C address 0x1a for control operations */
@@ -535,6 +554,30 @@
 
 #define WM8904_SSC_BUS     0
 
+/* Click Shield */
+/* Reset (RST#) Pulled-up on the click board */
+
+#define CLICK_MB1_RESET    (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+                            GPIO_PORT_PIOD | GPIO_PIN30)
+#define CLICK_MB2_RESET    (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_CLEAR | \
+                            GPIO_PORT_PIOA | GPIO_PIN19)
+/* Interrupts */
+
+#define CLICK_MB1_INTR     (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_CFG_DEGLITCH | \
+                            GPIO_INT_HIGHLEVEL | GPIO_PORT_PIOA | GPIO_PIN0)
+#define CLICK_MB2_INTR     (GPIO_INPUT | GPIO_CFG_DEFAULT | GPIO_CFG_DEGLITCH | \
+                            GPIO_INT_HIGHLEVEL | GPIO_PORT_PIOA | GPIO_PIN6)
+
+#define IRQ_MB1            SAM_IRQ_PA0
+#define IRQ_MB2            SAM_IRQ_PA6
+
+/* SP chip selects */
+
+#define CLICK_MB1_CS       (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
+                            GPIO_PORT_PIOD | GPIO_PIN25)
+#define CLICK_MB2_CS       (GPIO_OUTPUT | GPIO_CFG_DEFAULT | GPIO_OUTPUT_SET | \
+                            GPIO_PORT_PIOC | GPIO_PIN9)
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/

include/nuttx/net/icmpv6.h

@@ -127,7 +127,20 @@
  * Public Type Definitions
  ****************************************************************************/
 
-/* The ICMP and IP headers */
+/* The ICMPv6 header */
+
+struct icmpv6_hdr_s
+{
+  uint8_t  type;             /* Defines the format of the ICMP message */
+  uint8_t  code;             /* Further qualifies the ICMP messages */
+  uint16_t chksum;           /* Checksum of ICMP header and data */
+
+  /* Data following the ICMP header contains the data specific to the
+   * message type indicated by the Type and Code fields.
+   */
+};
+
+/* The ICMPv6 and IPv6 headers */
 
 struct icmpv6_iphdr_s
 {

net/devif/ipv6_forward.c

@@ -42,6 +42,7 @@
 #include <debug.h>
 #include <errno.h>
 
+#include <nuttx/net/net.h>
 #include <nuttx/net/netdev.h>
 #include <nuttx/net/netstats.h>
 

net/sixlowpan/sixlowpan_input.c

@@ -60,6 +60,7 @@
 
 #include "nuttx/net/netdev.h"
 #include "nuttx/net/ip.h"
+#include "nuttx/net/icmpv6.h"
 #include "nuttx/net/sixlowpan.h"
 #include "nuttx/wireless/ieee802154/ieee802154_mac.h"
 

net/sixlowpan/sixlowpan_tcpsend.c

@@ -51,6 +51,7 @@
 #include "netdev/netdev.h"
 #include "devif/devif.h"
 #include "socket/socket.h"
+#include "icmpv6/icmpv6.h"
 #include "tcp/tcp.h"
 #include "utils/utils.h"
 #include "sixlowpan/sixlowpan_internal.h"

net/sixlowpan/sixlowpan_udpsend.c

@@ -50,6 +50,7 @@
 
 #include "netdev/netdev.h"
 #include "socket/socket.h"
+#include "icmpv6/icmpv6.h"
 #include "udp/udp.h"
 #include "utils/utils.h"
 #include "sixlowpan/sixlowpan_internal.h"