STM32 SDIO: CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE should not be available unless CONFIG_MMCSD_SDIO=y

drivers/mmcsd/Kconfig

@@ -38,28 +38,6 @@ config MMCSD_HAVECARDDETECT
 		SDIO driver card detection is
 		100% accurate
 
-config ARCH_HAVE_SDIOWAIT_WRCOMPLETE
-	bool
-	default n
-
-config MMCSD_SDIOWAIT_WRCOMPLETE
-	bool "Use SDIO_D Busy to detect Write Complete"
-	default n
-	depends on ARCH_HAVE_SDIOWAIT_WRCOMPLETE
-	---help---
-		SDIO driver will use SDIO_D Busy signalling to detect Write Complete.
-		This option when selected, will enable the MMCSD driver to use the
-		underlying (stm32_sdio only) drivers implementation of the SD specs
-		SDIO_D Busy signalling to detect Write Complete. This will avoid
-		potentially very long (600Ms+) busy waiting in the MMCSD driver.
-
-		To implement SDIO_D Busy signalling, the underlying driver must
-		be capable of switching the GPIO_SDIO_D0 to be a rising edge sensitive
-		interrupt pin. It must then, condition that pin to detect the rising edge
-		on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
-		return it back to regular SDIO mode, when either the ISR fires or pin is
-		found to be high in the SDIO_EVENTWAIT call.
-
 config MMCSD_SPI
 	bool "MMC/SD SPI transfer support"
 	default y
@@ -111,6 +89,28 @@ config SDIO_MUXBUS
 		Set this SDIO interface if the SDIO interface
 		or hardware resources are shared with other drivers.
 
+config ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+	bool
+	default n
+
+config MMCSD_SDIOWAIT_WRCOMPLETE
+	bool "Use D0 Busy to detect Write Complete"
+	default n
+	depends on ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+	---help---
+		SDIO driver will use D0 Busy signalling to detect Write Complete.
+		This option when selected, will enable the MMCSD driver to use the
+		underlying SDIO drivers implementation of the SD specification's
+		D0 Busy signalling to detect Write Complete.  This will avoid
+		potentially very long (600Ms+) busy waiting in the MMCSD driver.
+
+		To implement D0 Busy signalling, the underlying driver must
+		be capable of switching the D0 GPIO to be a rising edge sensitive
+		interrupt pin. It must then, condition that pin to detect the rising edge
+		on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
+		return it back to regular SDIO mode, when either the ISR fires or pin is
+		found to be high in the SDIO_EVENTWAIT call.
+
 config SDIO_WIDTH_D1_ONLY
 	bool "SDIO 1-bit transfer"
 	default n

include/nuttx/sdio.h

@@ -63,15 +63,12 @@
 #define SDIOWAIT_TIMEOUT       (1 << 3) /* Bit 3: Timeout */
 #define SDIOWAIT_ERROR         (1 << 4) /* Bit 4: Some other error occurred */
 
-/* SDIOWAIT_WRCOMPLETE (optional) : SDIO driver will use SDIO_D Busy
+/* SDIOWAIT_WRCOMPLETE (optional) : Certain SDIO driver can use D0 busy
- *   signalling to detect Write Complete.  This option when selected, will
+ *   signalling to detect Write Complete.  Used of D0 busy signalling will
- *   enable the MMCSD driver to use the underlying (stm32_sdio only) drivers
+ *   avoid potentially very long (600Ms+) busy waiting in the MMCSD driver.
- *   implementation of the SD specs SDIO_D Busy signalling to detect Write
- *   Complete. This will avoid potentially very long (600Ms+) busy waiting
- *   in the MMCSD driver.
  *
- *   To implement SDIO_D Busy signalling, the underlying driver must be
+ *   To implement D0 Busy signalling, the underlying SDIO driver must be
- *   capable of switching the GPIO_SDIO_D0 to be a rising edge sensitive
+ *   capable of switching the the D0 GPIO to be a rising edge sensitive
  *   interrupt pin. It must then, condition that pin to detect the rising
  *   edge on receipt of SDWAIT_WRCOMPLETE in the SDIO_WAITENABLE call and
  *   return it back to regular SDIO mode, when either the ISR fires or pin