diff --git a/arch/risc-v/include/litex/irq.h b/arch/risc-v/include/litex/irq.h
index e0b4b075099..02713e29d44 100644
--- a/arch/risc-v/include/litex/irq.h
+++ b/arch/risc-v/include/litex/irq.h
@@ -33,33 +33,8 @@
 
 /* Map RISC-V exception code to NuttX IRQ */
 
-/* IRQ 0-15 : (exception:interrupt=0) */
-
-#define LITEX_IRQ_IAMISALIGNED  (0) /* Instruction Address Misaligned */
-#define LITEX_IRQ_IAFAULT       (1) /* Instruction Address Fault */
-#define LITEX_IRQ_IINSTRUCTION  (2) /* Illegal Instruction */
-#define LITEX_IRQ_BPOINT        (3) /* Break Point */
-#define LITEX_IRQ_LAMISALIGNED  (4) /* Load Address Misaligned */
-#define LITEX_IRQ_LAFAULT       (5) /* Load Access Fault */
-#define LITEX_IRQ_SAMISALIGNED  (6) /* Store/AMO Address Misaligned */
-#define LITEX_IRQ_SAFAULT       (7) /* Store/AMO Access Fault */
-#define LITEX_IRQ_ECALLU        (8) /* Environment Call from U-mode */
-                                    /* 9-10: Reserved */
-
-#define LITEX_IRQ_ECALLM       (11) /* Environment Call from M-mode */
-                                    /* 12-15: Reserved */
-
-/* IRQ 16- : (async event:interrupt=1) */
-
-#define LITEX_IRQ_ASYNC        (16)
-#define LITEX_IRQ_MSOFT    (LITEX_IRQ_ASYNC + 3)  /* Machine Software Int */
-#define LITEX_IRQ_MTIMER   (LITEX_IRQ_ASYNC + 7)  /* Machine Timer Int */
-#define LITEX_IRQ_MEXT     (LITEX_IRQ_ASYNC + 11) /* Machine External Int */
-
-/* Machine Global External Interrupt */
-
-#define LITEX_IRQ_UART0    (LITEX_IRQ_MEXT + 1)
-#define LITEX_IRQ_TIMER0   (LITEX_IRQ_MEXT + 2)
+#define LITEX_IRQ_UART0    (RISCV_IRQ_MEXT + 1)
+#define LITEX_IRQ_TIMER0   (RISCV_IRQ_MEXT + 2)
 
 /* Total number of IRQs */
 
diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c
index f4d23bc9959..7ef89ce8e40 100644
--- a/arch/risc-v/src/litex/litex_irq.c
+++ b/arch/risc-v/src/litex/litex_irq.c
@@ -72,7 +72,7 @@ void up_irqinitialize(void)
 
   /* Attach the ecall interrupt handler */
 
-  irq_attach(LITEX_IRQ_ECALLM, riscv_swint, NULL);
+  irq_attach(RISCV_IRQ_ECALLM, riscv_swint, NULL);
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
 
@@ -96,21 +96,21 @@ void up_disable_irq(int irq)
   int mask;
   uint32_t oldstat;
 
-  if (irq == LITEX_IRQ_MSOFT)
+  if (irq == RISCV_IRQ_MSOFT)
     {
       /* Read mstatus & clear machine software interrupt enable in mie */
 
       asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
     }
-  else if (irq == LITEX_IRQ_MTIMER)
+  else if (irq == RISCV_IRQ_MTIMER)
     {
       /* Read mstatus & clear machine timer interrupt enable in mie */
 
       asm volatile ("csrrc %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
     }
-  else if (irq > LITEX_IRQ_MEXT)
+  else if (irq > RISCV_IRQ_MEXT)
     {
-      extirq = irq - LITEX_IRQ_MEXT;
+      extirq = irq - RISCV_IRQ_MEXT;
       extirq--;
 
       /* Clear enable bit for the irq */
@@ -142,21 +142,21 @@ void up_enable_irq(int irq)
   int mask;
   uint32_t oldstat;
 
-  if (irq == LITEX_IRQ_MSOFT)
+  if (irq == RISCV_IRQ_MSOFT)
     {
       /* Read mstatus & set machine software interrupt enable in mie */
 
       asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MSIE));
     }
-  else if (irq == LITEX_IRQ_MTIMER)
+  else if (irq == RISCV_IRQ_MTIMER)
     {
       /* Read mstatus & set machine timer interrupt enable in mie */
 
       asm volatile ("csrrs %0, mie, %1": "=r" (oldstat) : "r"(MIE_MTIE));
     }
-  else if (irq > LITEX_IRQ_MEXT)
+  else if (irq > RISCV_IRQ_MEXT)
     {
-      extirq = irq - LITEX_IRQ_MEXT;
+      extirq = irq - RISCV_IRQ_MEXT;
       extirq--;
 
       /* Set enable bit for the irq */
diff --git a/arch/risc-v/src/litex/litex_irq_dispatch.c b/arch/risc-v/src/litex/litex_irq_dispatch.c
index 23f92ebf6e2..c29a87a1580 100644
--- a/arch/risc-v/src/litex/litex_irq_dispatch.c
+++ b/arch/risc-v/src/litex/litex_irq_dispatch.c
@@ -59,7 +59,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
 
   /* Firstly, check if the irq is machine external interrupt */
 
-  if (LITEX_IRQ_MEXT == irq)
+  if (RISCV_IRQ_MEXT == irq)
     {
       /* litex vexriscv dont follow riscv plic standard */
 
@@ -86,7 +86,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
 
   /* NOTE: In case of ecall, we need to adjust mepc in the context */
 
-  if (LITEX_IRQ_ECALLM == irq)
+  if (RISCV_IRQ_ECALLM == irq)
     {
       *mepc += 4;
     }
diff --git a/arch/risc-v/src/litex/litex_timerisr.c b/arch/risc-v/src/litex/litex_timerisr.c
index 266016e7b76..f4138b2fb50 100644
--- a/arch/risc-v/src/litex/litex_timerisr.c
+++ b/arch/risc-v/src/litex/litex_timerisr.c
@@ -161,7 +161,7 @@ void up_timer_initialize(void)
 {
   /* Attach timer interrupt handler */
 
-  irq_attach(LITEX_IRQ_MTIMER, litex_timerisr, NULL);
+  irq_attach(RISCV_IRQ_MTIMER, litex_timerisr, NULL);
 
   /* Reload CLINT mtimecmp */
 
@@ -169,5 +169,5 @@ void up_timer_initialize(void)
 
   /* And enable the timer interrupt */
 
-  up_enable_irq(LITEX_IRQ_MTIMER);
+  up_enable_irq(RISCV_IRQ_MTIMER);
 }