Fix STM32 F2/F4 SDIO clocking; Clean-up files in sched/ directory

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4940 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-07-14 19:30:31 +00:00
parent ee460442a1
commit 0819c01cec
6 changed files with 474 additions and 51 deletions
+15 -13
View File
@@ -34,17 +34,19 @@
*
************************************************************************************/
#ifndef __ARCH_BOARD_BOARD_H
#define __ARCH_BOARD_BOARD_H
#ifndef __CONFIGS_STM3220G_EVAL_INCLUDE_BOARD_H
#define __CONFIGS_STM3220G_EVAL_INCLUDE_BOARD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include "stm32_rcc.h"
#include "stm32_sdio.h"
#include "stm32_internal.h"
@@ -168,29 +170,29 @@
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
*
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
*/
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(0+2)= 24 MHz
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* Ethernet *************************************************************************/
@@ -531,4 +533,4 @@ EXTERN void stm3220g_lcdclear(uint16_t color);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_BOARD_BOARD_H */
#endif /* __CONFIGS_STM3220G_EVAL_INCLUDE_BOARD_H */
+10 -11
View File
@@ -518,8 +518,8 @@ CONFIG_DEBUG_I2C=n
CONFIG_DEBUG_INPUT=n
CONFIG_DEBUG_DMA=n
CONFIG_HAVE_CXX=n
CONFIG_HAVE_CXXINITIALIZE=n
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_MM_REGIONS=1
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
@@ -813,7 +813,6 @@ CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
CONFIG_MMCSD_MMCSUPPORT=n
CONFIG_MMCSD_HAVECARDDETECT=n
#
# TCP/IP and UDP support via uIP
#
@@ -1342,8 +1341,8 @@ CONFIG_STM32_ILI9325_DISABLE=n
#
# Settings for examples/uip
#
CONFIG_EXAMPLE_UIP_IPADDR==(192<<24|168<<16|21<<8|15)
CONFIG_EXAMPLE_UIP_DRIPADDR=(192<<24|168<<16|21<<8|10)
CONFIG_EXAMPLE_UIP_IPADDR=(10<<24|0<<16|0<<8|2)
CONFIG_EXAMPLE_UIP_DRIPADDR=(10<<24|0<<16|0<<8|1)
CONFIG_EXAMPLE_UIP_NETMASK=(255<<24|255<<16|255<<8|0)
CONFIG_EXAMPLE_UIP_DHCPC=n
@@ -1352,10 +1351,10 @@ CONFIG_EXAMPLE_UIP_DHCPC=n
CONFIG_EXAMPLE_NETTEST_SERVER=n
CONFIG_EXAMPLE_NETTEST_PERFORMANCE=n
CONFIG_EXAMPLE_NETTEST_NOMAC=y
CONFIG_EXAMPLE_NETTEST_IPADDR==(192<<24|168<<16|21<<8|15)
CONFIG_EXAMPLE_NETTEST_DRIPADDR=(192<<24|168<<16|21<<8|10)
CONFIG_EXAMPLE_NETTEST_IPADDR=(10<<24|0<<16|0<<8|2)
CONFIG_EXAMPLE_NETTEST_DRIPADDR=(10<<24|0<<16|0<<8|1)
CONFIG_EXAMPLE_NETTEST_NETMASK=(255<<24|255<<16|255<<8|0)
CONFIG_EXAMPLE_NETTEST_CLIENTIP=(192<<24|168<<16|21<<8|10)
CONFIG_EXAMPLE_NETTEST_CLIENTIP=(10<<24|0<<16|0<<8|1)
#
# Settings for examples/ostest
@@ -1410,12 +1409,12 @@ CONFIG_NSH_DISABLEBG=n
CONFIG_NSH_ROMFSETC=n
CONFIG_NSH_CONSOLE=y
CONFIG_NSH_TELNET=y
CONFIG_NSH_ARCHINIT=n
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_IOBUFFER_SIZE=512
CONFIG_NSH_DHCPC=n
CONFIG_NSH_NOMAC=y
CONFIG_NSH_IPADDR=(192<<24|168<<16|13<<8|161)
CONFIG_NSH_DRIPADDR=(192<<24|168<<16|13<<8|1)
CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2)
CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1)
CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0)
CONFIG_NSH_ROMFSMOUNTPT="/etc"
CONFIG_NSH_INITSCRIPT="init.d/rcS"
+13
View File
@@ -80,6 +80,10 @@ ifeq ($(CONFIG_WATCHDOG),y)
CONFIGURED_APPS += examples/watchdog
endif
ifeq ($(CONFIG_INPUT_STMPE811),y)
CONFIGURED_APPS += examples/touchscreen
endif
# Uncomment examples/ftpc to include the FTP client example
# Uncomment examples/ftpd to include the FTP daemon example
@@ -87,3 +91,12 @@ ifeq ($(CONFIG_NET),y)
#CONFIGURED_APPS += examples/ftpc
#CONFIGURED_APPS += examples/ftpd
endif
# Uncomment to select a graphics example
ifeq ($(CONFIG_NX),y)
#CONFIGURED_APPS += examples/nx
#CONFIGURED_APPS += examples/nxhello
#CONFIGURED_APPS += examples/nximage
#CONFIGURED_APPS += examples/nxlines
endif
File diff suppressed because it is too large Load Diff
+10 -10
View File
@@ -167,29 +167,29 @@
* to service FIFOs in interrupt driven mode. These values have not been
* tuned!!!
*
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
*/
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
/* DMA ON: HSDIOCLK=48MHz, SDIO_CK=SDIOCLK/(0+2)=24 MHz
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
*/
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (0 << SDIO_CLKCR_CLKDIV_SHIFT)
#else
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* Ethernet *************************************************************************/
+2 -2
View File
@@ -541,7 +541,7 @@ CONFIG_START_MONTH=12
CONFIG_START_DAY=6
CONFIG_GREGORIAN_TIME=n
CONFIG_JULIAN_TIME=n
CONFIG_DEV_CONSOLE=y
CONFIG_DEV_CONSOLE=n
CONFIG_DEV_LOWCONSOLE=n
CONFIG_MUTEX_TYPES=n
CONFIG_PRIORITY_INHERITANCE=n
@@ -1268,7 +1268,7 @@ CONFIG_NSH_NESTDEPTH=3
CONFIG_NSH_DISABLESCRIPT=n
CONFIG_NSH_DISABLEBG=n
CONFIG_NSH_ROMFSETC=n
CONFIG_NSH_CONSOLE=y
CONFIG_NSH_CONSOLE=n
CONFIG_NSH_TELNET=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_IOBUFFER_SIZE=512