diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index 2d462bebcb9..be780bc43fd 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -779,6 +779,8 @@ config ARCH_CHIP_STM32F446M
 	select STM32_STM32F40XX
 	select STM32_STM32F446
 	select ARCH_HAVE_FPU
+	select STM32_HAVE_SAIPLL
+	select STM32_HAVE_I2SPLL
 
 config ARCH_CHIP_STM32F446R
 	bool "STM32F446R"
@@ -786,6 +788,8 @@ config ARCH_CHIP_STM32F446R
 	select STM32_STM32F40XX
 	select STM32_STM32F446
 	select ARCH_HAVE_FPU
+	select STM32_HAVE_SAIPLL
+	select STM32_HAVE_I2SPLL
 
 config ARCH_CHIP_STM32F446V
 	bool "STM32F446V"
@@ -793,6 +797,8 @@ config ARCH_CHIP_STM32F446V
 	select STM32_STM32F40XX
 	select STM32_STM32F446
 	select ARCH_HAVE_FPU
+	select STM32_HAVE_SAIPLL
+	select STM32_HAVE_I2SPLL
 
 config ARCH_CHIP_STM32F446Z
 	bool "STM32F446Z"
@@ -800,7 +806,8 @@ config ARCH_CHIP_STM32F446Z
 	select STM32_STM32F40XX
 	select STM32_STM32F446
 	select ARCH_HAVE_FPU
-
+	select STM32_HAVE_SAIPLL
+	select STM32_HAVE_I2SPLL
 
 endchoice
 
@@ -1382,6 +1389,14 @@ config STM32_HAVE_SPI6
 	bool
 	default n
 
+config STM32_HAVE_SAIPLL
+  bool
+  default n
+
+config STM32_HAVE_I2SPLL
+  bool
+  default n
+
 # These are the peripheral selections proper
 
 config STM32_ADC1
@@ -2045,6 +2060,24 @@ config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
 	---help---
 		Enables special, board-specific STM32 clock configuration.
 
+config STM32_SAIPLL
+	bool "SAIPLL"
+	default n
+	depends on STM32_HAVE_SAIPLL
+	---help---
+		The STM32F446 has a separate PLL for the SAI block.
+		Set this true and provide configuration parameters in
+		board.h to use this PLL.
+
+config STM32_I2SPLL
+	bool "I2SPLL"
+	default n
+	depends on STM32_HAVE_I2SPLL
+	---help---
+		The STM32F446 has a separate PLL for the I2S block.
+		Set this true and provide configuration parameters in
+		board.h to use this PLL.
+
 config STM32_CCMEXCLUDE
 	bool "Exclude CCM SRAM from the heap"
 	default y if  ARCH_DMA || ELF
diff --git a/arch/arm/src/stm32/chip/stm32f44xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f44xxx_rcc.h
index 4ea159e16a6..61de03cfc7e 100644
--- a/arch/arm/src/stm32/chip/stm32f44xxx_rcc.h
+++ b/arch/arm/src/stm32/chip/stm32f44xxx_rcc.h
@@ -537,12 +537,9 @@
 #define RCC_PLLI2SCFGR_PLLI2SN_MASK  (0x1ff << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
 #  define RCC_PLLI2SCFGR_PLLI2SN(n)  ((n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT)
 #define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16)   /* Bits 16-17: PLLI2S division factor for SPDIF-Rx clock */
-#define RCC_PLLI2SCFGR_PLLI2SP_MASK  (0x1ff << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
-#  define RCC_PLLI2SCFGR_PLLI2SP(n)  ((n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
-#  define RCC_PLLI2SCFGR_PLLI2SP_2    RCC_PLLI2SCFGR_PLLI2SP(0)  /* 00: PLLI2S = 2 */
-#  define RCC_PLLI2SCFGR_PLLI2SP_4    RCC_PLLI2SCFGR_PLLI2SP(1)  /* 01: PLLI2S = 4 */
-#  define RCC_PLLI2SCFGR_PLLI2SP_6    RCC_PLLI2SCFGR_PLLI2SP(2)  /* 10: PLLI2S = 6 */
-#  define RCC_PLLI2SCFGR_PLLI2SP_8    RCC_PLLI2SCFGR_PLLI2SP(3)  /* 11: PLLI2S = 8 */
+#define RCC_PLLI2SCFGR_PLLI2SP_MASK  (0x3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT)
+                                             /* Set PLLI2S P to 2,4,6,8 */
+#  define RCC_PLLI2SCFGR_PLLI2SP(n)  (((((n)-2)/2) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) & RCC_PLLI2SCFGR_PLLI2SP_MASK)
 
 #define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24)   /* Bits 24-27: PLLI2S division factor for SAI1 clock*/
 #define RCC_PLLI2SCFGR_PLLI2SQ_MASK  (0xf << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT)
@@ -565,11 +562,9 @@
 
 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16)   /* Bits 16-17: PLLSAI division factor for 48 MHz clock */
 #define RCC_PLLSAICFGR_PLLSAIP_MASK  (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
-#  define RCC_PLLSAICFGR_PLLSAIP(n)  ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT)
-#  define RCC_PLLSAICFGR_PLLSAI_2     RCC_PLLSAICFGR_PLLSAIP(0)  /* 00: PLLSAI = 2 */
-#  define RCC_PLLSAICFGR_PLLSAI_4     RCC_PLLSAICFGR_PLLSAIP(1)  /* 01: PLLSAI = 4 */
-#  define RCC_PLLSAICFGR_PLLSAI_6     RCC_PLLSAICFGR_PLLSAIP(2)  /* 10: PLLSAI = 6 */
-#  define RCC_PLLSAICFGR_PLLSAI_8     RCC_PLLSAICFGR_PLLSAIP(3)  /* 11: PLLSAI = 8 */
+                                             /* Set PLLSAI P to 2,4,6,8 */
+#  define RCC_PLLSAICFGR_PLLSAIP(n)  (((((n)-2)/2) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) & RCC_PLLSAICFGR_PLLSAIP_MASK)
+
 #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24)     /* Bits 24-27: PLLSAI division factor for SAI clock */
 #define RCC_PLLSAICFGR_PLLSAIQ_MASK  (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
 #  define RCC_PLLSAICFGR_PLLSAIQ(n)  ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT)
diff --git a/arch/arm/src/stm32/stm32f44xxx_rcc.c b/arch/arm/src/stm32/stm32f44xxx_rcc.c
index 903d4183afa..e0b396e9174 100644
--- a/arch/arm/src/stm32/stm32f44xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f44xxx_rcc.c
@@ -693,7 +693,7 @@ static void stm32_stdclockconfig(void)
         {
         }
 
-#ifdef CONFIG_STM32_USE_PLLSAI
+#if defined(CONFIG_STM32_SAIPLL)
 
       /* Configure PLLSAI */
 
@@ -739,7 +739,7 @@ static void stm32_stdclockconfig(void)
         }
 #endif
 
-#ifdef CONFIG_STM32_USE_PLLI2S
+#if defined(CONFIG_STM32_I2SPLL)
 
       /* Configure PLLI2S */