diff --git a/ChangeLog b/ChangeLog index 76a55e2c539..9a98b006fa5 100644 --- a/ChangeLog +++ b/ChangeLog @@ -6192,5 +6192,7 @@ * include/nuttx/fs/smart.h: Move smart.h to include/fs/smart.h (2013-12-10). * include/nuttx/fs/ramdisk.h: Move ramdisk.h to include/fs/ramdisk.h - (2013012-10). + (2013-12-10). + * arch/arm/src/a1x/chip/a1x_pio.h and a10_piocfg.h: PIO register + defintion header files (2013-12-10). diff --git a/arch/arm/src/a1x/chip/a10_piocfg.h b/arch/arm/src/a1x/chip/a10_piocfg.h new file mode 100644 index 00000000000..1f8c04669ba --- /dev/null +++ b/arch/arm/src/a1x/chip/a10_piocfg.h @@ -0,0 +1,1297 @@ +/************************************************************************************ + * arch/arm/src/a1x/chip/a10_piocfg.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H +#define __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/a1x_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register bit field definitions ***************************************************/ + +/* Port A Configure Register 0 */ + +#define PIO_CFG0_PA0_SHIFT (0) +#define PIO_CFG0_PA0_MASK (7 << PIO_CFG0_PA0_SHIFT) +# define PIO_CFG0_PA0_INPUT (0 << PIO_CFG0_PA0_SHIFT) +# define PIO_CFG0_PA0_OUTPUT (1 << PIO_CFG0_PA0_SHIFT) +# define PIO_CFG0_PA0_ERXD3 (2 << PIO_CFG0_PA0_SHIFT) +# define PIO_CFG0_PA0_SPI1_CS0 (3 << PIO_CFG0_PA0_SHIFT) +# define PIO_CFG0_PA0_UART2_RTS (4 << PIO_CFG0_PA0_SHIFT) +#define PIO_CFG0_PA1_SHIFT (4) +#define PIO_CFG0_PA1_MASK (7 << PIO_CFG0_PA1_SHIFT) +# define PIO_CFG0_PA1_INPUT (0 << PIO_CFG0_PA1_SHIFT) +# define PIO_CFG0_PA1_OUTPUT (1 << PIO_CFG0_PA1_SHIFT) +# define PIO_CFG0_PA1_ERXD2 (2 << PIO_CFG0_PA1_SHIFT) +# define PIO_CFG0_PA1_SPI1_CLK (3 << PIO_CFG0_PA1_SHIFT) +# define PIO_CFG0_PA1_UART2_CTS (4 << PIO_CFG0_PA1_SHIFT) +#define PIO_CFG0_PA2_SHIFT (8) +#define PIO_CFG0_PA2_MASK (7 << PIO_CFG0_PA2_SHIFT) +# define PIO_CFG0_PA2_INPUT (0 << PIO_CFG0_PA2_SHIFT) +# define PIO_CFG0_PA2_OUTPUT (1 << PIO_CFG0_PA2_SHIFT) +# define PIO_CFG0_PA2_ERXD1 (2 << PIO_CFG0_PA2_SHIFT) +# define PIO_CFG0_PA2_SPI1_MOSI (3 << PIO_CFG0_PA2_SHIFT) +# define PIO_CFG0_PA2_UART2_TX (4 << PIO_CFG0_PA2_SHIFT) +#define PIO_CFG0_PA3_SHIFT (12) +#define PIO_CFG0_PA3_MASK (7 << PIO_CFG0_PA3_SHIFT) +# define PIO_CFG0_PA3_INPUT (0 << PIO_CFG0_PA3_SHIFT) +# define PIO_CFG0_PA3_OUTPUT (1 << PIO_CFG0_PA3_SHIFT) +# define PIO_CFG0_PA3_ERXD0 (2 << PIO_CFG0_PA3_SHIFT) +# define PIO_CFG0_PA3_SPI1_MISO (3 << PIO_CFG0_PA3_SHIFT) +# define PIO_CFG0_PA3_UART2_RX (4 << PIO_CFG0_PA3_SHIFT) +#define PIO_CFG0_PA4_SHIFT (16) +#define PIO_CFG0_PA4_MASK (7 << PIO_CFG0_PA4_SHIFT) +# define PIO_CFG0_PA4_INPUT (0 << PIO_CFG0_PA4_SHIFT) +# define PIO_CFG0_PA4_OUTPUT (1 << PIO_CFG0_PA4_SHIFT) +# define PIO_CFG0_PA4_ETXD3 (2 << PIO_CFG0_PA4_SHIFT) +# define PIO_CFG0_PA4_SPI1_CS1 (3 << PIO_CFG0_PA4_SHIFT) +#define PIO_CFG0_PA5_SHIFT (20) +#define PIO_CFG0_PA5_MASK (7 << PIO_CFG0_PA5_SHIFT) +# define PIO_CFG0_PA5_INPUT (0 << PIO_CFG0_PA5_SHIFT) +# define PIO_CFG0_PA5_OUTPUT (1 << PIO_CFG0_PA5_SHIFT) +# define PIO_CFG0_PA5_ETXD2 (2 << PIO_CFG0_PA5_SHIFT) +# define PIO_CFG0_PA5_SPI3_CS0 (3 << PIO_CFG0_PA5_SHIFT) +#define PIO_CFG0_PA6_SHIFT (24) +#define PIO_CFG0_PA6_MASK (7 << PIO_CFG0_PA6_SHIFT) +# define PIO_CFG0_PA6_INPUT (0 << PIO_CFG0_PA6_SHIFT) +# define PIO_CFG0_PA6_OUTPUT (1 << PIO_CFG0_PA6_SHIFT) +# define PIO_CFG0_PA6_ETXD1 (2 << PIO_CFG0_PA6_SHIFT) +# define PIO_CFG0_PA6_SPI3_CLK (3 << PIO_CFG0_PA6_SHIFT) +#define PIO_CFG0_PA7_SHIFT (28) +#define PIO_CFG0_PA7_MASK (7 << PIO_CFG0_PA7_SHIFT) +# define PIO_CFG0_PA7_INPUT (0 << PIO_CFG0_PA7_SHIFT) +# define PIO_CFG0_PA7_OUTPUT (1 << PIO_CFG0_PA7_SHIFT) +# define PIO_CFG0_PA7_ETXD0 (2 << PIO_CFG0_PA7_SHIFT) +# define PIO_CFG0_PA7_SPI3_MOSI (3 << PIO_CFG0_PA7_SHIFT) + +/* Port A Configure Register 1 */ + +#define PIO_CFG1_PA8_SHIFT (0) +#define PIO_CFG1_PA8_MASK (7 << PIO_CFG1_PA8_SHIFT) +# define PIO_CFG1_PA8_INPUT (0 << PIO_CFG1_PA8_SHIFT) +# define PIO_CFG1_PA8_OUTPUT (1 << PIO_CFG1_PA8_SHIFT) +# define PIO_CFG1_PA8_ERXCK (2 << PIO_CFG1_PA8_SHIFT) +# define PIO_CFG1_PA8_SPI3_MISO (3 << PIO_CFG1_PA8_SHIFT) +#define PIO_CFG1_PA9_SHIFT (4) +#define PIO_CFG1_PA9_MASK (7 << PIO_CFG1_PA9_SHIFT) +# define PIO_CFG1_PA9_INPUT (0 << PIO_CFG1_PA9_SHIFT) +# define PIO_CFG1_PA9_OUTPUT (1 << PIO_CFG1_PA9_SHIFT) +# define PIO_CFG1_PA9_ERXERR (2 << PIO_CFG1_PA9_SHIFT) +# define PIO_CFG1_PA9_SPI3_CS1 (3 << PIO_CFG1_PA9_SHIFT) +#define PIO_CFG1_PA10_SHIFT (8) +#define PIO_CFG1_PA10_MASK (3 << PIO_CFG1_PA10_SHIFT) +# define PIO_CFG1_PA10_INPUT (0 << PIO_CFG1_PA10_SHIFT) +# define PIO_CFG1_PA10_OUTPUT (1 << PIO_CFG1_PA10_SHIFT) +# define PIO_CFG1_PA10_ERXDV (2 << PIO_CFG1_PA10_SHIFT) +# define PIO_CFG1_PA10_UART1_TX (4 << PIO_CFG1_PA10_SHIFT) +#define PIO_CFG1_PA11_SHIFT (12) +#define PIO_CFG1_PA11_MASK (3 << PIO_CFG1_PA11_SHIFT) +# define PIO_CFG1_PA11_INPUT (0 << PIO_CFG1_PA11_SHIFT) +# define PIO_CFG1_PA11_OUTPUT (1 << PIO_CFG1_PA11_SHIFT) +# define PIO_CFG1_PA11_EMDC (2 << PIO_CFG1_PA11_SHIFT) +# define PIO_CFG1_PA11_UART1_RX (4 << PIO_CFG1_PA11_SHIFT) +#define PIO_CFG1_PA12_SHIFT (16) +#define PIO_CFG1_PA12_MASK (3 << PIO_CFG1_PA12_SHIFT) +# define PIO_CFG1_PA12_INPUT (0 << PIO_CFG1_PA12_SHIFT) +# define PIO_CFG1_PA12_OUTPUT (1 << PIO_CFG1_PA12_SHIFT) +# define PIO_CFG1_PA12_EMDIO (2 << PIO_CFG1_PA12_SHIFT) +# define PIO_CFG1_PA12_UART6_TX (3 << PIO_CFG1_PA12_SHIFT) +# define PIO_CFG1_PA12_UART1_RTS (4 << PIO_CFG1_PA12_SHIFT) +#define PIO_CFG1_PA13_SHIFT (20) +#define PIO_CFG1_PA13_MASK (3 << PIO_CFG1_PA13_SHIFT) +# define PIO_CFG1_PA13_INPUT (0 << PIO_CFG1_PA13_SHIFT) +# define PIO_CFG1_PA13_OUTPUT (1 << PIO_CFG1_PA13_SHIFT) +# define PIO_CFG1_PA13_ETXEN (2 << PIO_CFG1_PA13_SHIFT) +# define PIO_CFG1_PA13_UART6_RX (3 << PIO_CFG1_PA13_SHIFT) +# define PIO_CFG1_PA13_UART1_CTS (4 << PIO_CFG1_PA13_SHIFT) +#define PIO_CFG1_PA14_SHIFT (24) +#define PIO_CFG1_PA14_MASK (3 << PIO_CFG1_PA14_SHIFT) +# define PIO_CFG1_PA14_INPUT (0 << PIO_CFG1_PA14_SHIFT) +# define PIO_CFG1_PA14_OUTPUT (1 << PIO_CFG1_PA14_SHIFT) +# define PIO_CFG1_PA14_ETXCK (2 << PIO_CFG1_PA14_SHIFT) +# define PIO_CFG1_PA14_UART7_TX (3 << PIO_CFG1_PA14_SHIFT) +# define PIO_CFG1_PA14_UART1_DTR (4 << PIO_CFG1_PA14_SHIFT) +#define PIO_CFG1_PA15_SHIFT (28) +#define PIO_CFG1_PA15_MASK (3 << PIO_CFG1_PA15_SHIFT) +# define PIO_CFG1_PA15_INPUT (0 << PIO_CFG1_PA15_SHIFT) +# define PIO_CFG1_PA15_OUTPUT (1 << PIO_CFG1_PA15_SHIFT) +# define PIO_CFG1_PA15_ECRS (2 << PIO_CFG1_PA15_SHIFT) +# define PIO_CFG1_PA15_UART7_RX (3 << PIO_CFG1_PA15_SHIFT) +# define PIO_CFG1_PA15_UART1_DSR (4 << PIO_CFG1_PA15_SHIFT) + +/* Port A Configure Register 2 */ + +#define PIO_CFG2_PA16_SHIFT (0) +#define PIO_CFG2_PA16_MASK (7 << PIO_CFG2_PA16_SHIFT) +# define PIO_CFG2_PA16_INPUT (0 << PIO_CFG2_PA16_SHIFT) +# define PIO_CFG2_PA16_OUTPUT (1 << PIO_CFG2_PA16_SHIFT) +# define PIO_CFG2_PA16_ETXERR (2 << PIO_CFG2_PA16_SHIFT) +# define PIO_CFG2_PA16_CAN_RX (3 << PIO_CFG2_PA16_SHIFT) +# define PIO_CFG2_PA16_UART1_RING (4 << PIO_CFG2_PA16_SHIFT) +#define PIO_CFG2_PA17_SHIFT (4) +#define PIO_CFG2_PA17_MASK (7 << PIO_CFG2_PA17_SHIFT) +# define PIO_CFG2_PA17_INPUT (0 << PIO_CFG2_PA17_SHIFT) +# define PIO_CFG2_PA17_OUTPUT (1 << PIO_CFG2_PA17_SHIFT) +# define PIO_CFG2_PA17_ECOL (2 << PIO_CFG2_PA17_SHIFT) +# define PIO_CFG2_PA17_CAN_TX (3 << PIO_CFG2_PA17_SHIFT) +# define PIO_CFG2_PA17_UART1_DCD (4 << PIO_CFG2_PA17_SHIFT) + +/* Port A Configure Register 3 (not used) */ + +/* Port B Configure Register 0 */ + +#define PIO_CFG0_PB0_SHIFT (0) +#define PIO_CFG0_PB0_MASK (7 << PIO_CFG0_PB0_SHIFT) +# define PIO_CFG0_PB0_INPUT (0 << PIO_CFG0_PB0_SHIFT) +# define PIO_CFG0_PB0_OUTPUT (1 << PIO_CFG0_PB0_SHIFT) +# define PIO_CFG0_PB0_TWI0_SCK (2 << PIO_CFG0_PB0_SHIFT) +#define PIO_CFG0_PB1_SHIFT (4) +#define PIO_CFG0_PB1_MASK (7 << PIO_CFG0_PB1_SHIFT) +# define PIO_CFG0_PB1_INPUT (0 << PIO_CFG0_PB1_SHIFT) +# define PIO_CFG0_PB1_OUTPUT (1 << PIO_CFG0_PB1_SHIFT) +# define PIO_CFG0_PB1_TWI0_SDA (2 << PIO_CFG0_PB1_SHIFT) +#define PIO_CFG0_PB2_SHIFT (8) +#define PIO_CFG0_PB2_MASK (7 << PIO_CFG0_PB2_SHIFT) +# define PIO_CFG0_PB2_INPUT (0 << PIO_CFG0_PB2_SHIFT) +# define PIO_CFG0_PB2_OUTPUT (1 << PIO_CFG0_PB2_SHIFT) +# define PIO_CFG0_PB2_PWM0 (2 << PIO_CFG0_PB2_SHIFT) +#define PIO_CFG0_PB3_SHIFT (12) +#define PIO_CFG0_PB3_MASK (7 << PIO_CFG0_PB3_SHIFT) +# define PIO_CFG0_PB3_INPUT (0 << PIO_CFG0_PB3_SHIFT) +# define PIO_CFG0_PB3_OUTPUT (1 << PIO_CFG0_PB3_SHIFT) +# define PIO_CFG0_PB3_IR0_TX (2 << PIO_CFG0_PB3_SHIFT) +# define PIO_CFG0_PB3_NC (3 << PIO_CFG0_PB3_SHIFT) +# define PIO_CFG0_PB3_STANBYWFI (4 << PIO_CFG0_PB3_SHIFT) +#define PIO_CFG0_PB4_SHIFT (16) +#define PIO_CFG0_PB4_MASK (7 << PIO_CFG0_PB4_SHIFT) +# define PIO_CFG0_PB4_INPUT (0 << PIO_CFG0_PB4_SHIFT) +# define PIO_CFG0_PB4_OUTPUT (1 << PIO_CFG0_PB4_SHIFT) +# define PIO_CFG0_PB4_IR0_RX (2 << PIO_CFG0_PB4_SHIFT) +#define PIO_CFG0_PB5_SHIFT (20) +#define PIO_CFG0_PB5_MASK (7 << PIO_CFG0_PB5_SHIFT) +# define PIO_CFG0_PB5_INPUT (0 << PIO_CFG0_PB5_SHIFT) +# define PIO_CFG0_PB5_OUTPUT (1 << PIO_CFG0_PB5_SHIFT) +# define PIO_CFG0_PB5_I2S_MCLK (2 << PIO_CFG0_PB5_SHIFT) +# define PIO_CFG0_PB5_AC97_MCLK (3 << PIO_CFG0_PB5_SHIFT) +#define PIO_CFG0_PB6_SHIFT (24) +#define PIO_CFG0_PB6_MASK (7 << PIO_CFG0_PB6_SHIFT) +# define PIO_CFG0_PB6_INPUT (0 << PIO_CFG0_PB6_SHIFT) +# define PIO_CFG0_PB6_OUTPUT (1 << PIO_CFG0_PB6_SHIFT) +# define PIO_CFG0_PB6_I2S_BCLK (2 << PIO_CFG0_PB6_SHIFT) +# define PIO_CFG0_PB6_AC97_BCLK (3 << PIO_CFG0_PB6_SHIFT) +#define PIO_CFG0_PB7_SHIFT (28) +#define PIO_CFG0_PB7_MASK (7 << PIO_CFG0_PB7_SHIFT) +# define PIO_CFG0_PB7_INPUT (0 << PIO_CFG0_PB7_SHIFT) +# define PIO_CFG0_PB7_OUTPUT (1 << PIO_CFG0_PB7_SHIFT) +# define PIO_CFG0_PB7_I2S_LRCK (2 << PIO_CFG0_PB7_SHIFT) +# define PIO_CFG0_PB7_AC97_SYNC (3 << PIO_CFG0_PB7_SHIFT) + +/* Port B Configure Register 1 */ + +#define PIO_CFG1_PB8_SHIFT (0) +#define PIO_CFG1_PB8_MASK (7 << PIO_CFG1_PB8_SHIFT) +# define PIO_CFG1_PB8_INPUT (0 << PIO_CFG1_PB8_SHIFT) +# define PIO_CFG1_PB8_OUTPUT (1 << PIO_CFG1_PB8_SHIFT) +# define PIO_CFG1_PB8_I2S_DO0 (2 << PIO_CFG1_PB8_SHIFT) +# define PIO_CFG1_PB8_AC97_DO (3 << PIO_CFG1_PB8_SHIFT) +#define PIO_CFG1_PB9_SHIFT (4) +#define PIO_CFG1_PB9_MASK (7 << PIO_CFG1_PB9_SHIFT) +# define PIO_CFG1_PB9_INPUT (0 << PIO_CFG1_PB9_SHIFT) +# define PIO_CFG1_PB9_OUTPUT (1 << PIO_CFG1_PB9_SHIFT) +# define PIO_CFG1_PB9_I2S_DO1 (2 << PIO_CFG1_PB9_SHIFT) +#define PIO_CFG1_PB10_SHIFT (8) +#define PIO_CFG1_PB10_MASK (3 << PIO_CFG1_PB10_SHIFT) +# define PIO_CFG1_PB10_INPUT (0 << PIO_CFG1_PB10_SHIFT) +# define PIO_CFG1_PB10_OUTPUT (1 << PIO_CFG1_PB10_SHIFT) +# define PIO_CFG1_PB10_I2S_DO2 (2 << PIO_CFG1_PB10_SHIFT) +#define PIO_CFG1_PB11_SHIFT (12) +#define PIO_CFG1_PB11_MASK (3 << PIO_CFG1_PB11_SHIFT) +# define PIO_CFG1_PB11_INPUT (0 << PIO_CFG1_PB11_SHIFT) +# define PIO_CFG1_PB11_OUTPUT (1 << PIO_CFG1_PB11_SHIFT) +# define PIO_CFG1_PB11_I2S_DO3 (2 << PIO_CFG1_PB11_SHIFT) +#define PIO_CFG1_PB12_SHIFT (16) +#define PIO_CFG1_PB12_MASK (3 << PIO_CFG1_PB12_SHIFT) +# define PIO_CFG1_PB12_INPUT (0 << PIO_CFG1_PB12_SHIFT) +# define PIO_CFG1_PB12_OUTPUT (1 << PIO_CFG1_PB12_SHIFT) +# define PIO_CFG1_PB12_I2S_DI (2 << PIO_CFG1_PB12_SHIFT) +# define PIO_CFG1_PB12_AC97_DI (3 << PIO_CFG1_PB12_SHIFT) +#define PIO_CFG1_PB13_SHIFT (20) +#define PIO_CFG1_PB13_MASK (3 << PIO_CFG1_PB13_SHIFT) +# define PIO_CFG1_PB13_INPUT (0 << PIO_CFG1_PB13_SHIFT) +# define PIO_CFG1_PB13_OUTPUT (1 << PIO_CFG1_PB13_SHIFT) +# define PIO_CFG1_PB13_SPI2_CS1 (2 << PIO_CFG1_PB13_SHIFT) +#define PIO_CFG1_PB14_SHIFT (24) +#define PIO_CFG1_PB14_MASK (3 << PIO_CFG1_PB14_SHIFT) +# define PIO_CFG1_PB14_INPUT (0 << PIO_CFG1_PB14_SHIFT) +# define PIO_CFG1_PB14_OUTPUT (1 << PIO_CFG1_PB14_SHIFT) +# define PIO_CFG1_PB14_SPI2_CS0 (2 << PIO_CFG1_PB14_SHIFT) +# define PIO_CFG1_PB14_JTAG_MS0 (3 << PIO_CFG1_PB14_SHIFT) +#define PIO_CFG1_PB15_SHIFT (28) +#define PIO_CFG1_PB15_MASK (3 << PIO_CFG1_PB15_SHIFT) +# define PIO_CFG1_PB15_INPUT (0 << PIO_CFG1_PB15_SHIFT) +# define PIO_CFG1_PB15_OUTPUT (1 << PIO_CFG1_PB15_SHIFT) +# define PIO_CFG1_PB15_SPI2_CLK (2 << PIO_CFG1_PB15_SHIFT) +# define PIO_CFG1_PB15_JTAG_CK0 (3 << PIO_CFG1_PB15_SHIFT) + +/* Port B Configure Register 2 */ + +#define PIO_CFG2_PB16_SHIFT (0) +#define PIO_CFG2_PB16_MASK (7 << PIO_CFG2_PB16_SHIFT) +# define PIO_CFG2_PB16_INPUT (0 << PIO_CFG2_PB16_SHIFT) +# define PIO_CFG2_PB16_OUTPUT (1 << PIO_CFG2_PB16_SHIFT) +# define PIO_CFG2_PB16_SPI2_MOSI (2 << PIO_CFG2_PB16_SHIFT) +# define PIO_CFG2_PB16_JTAG_DO0 (3 << PIO_CFG2_PB16_SHIFT) +#define PIO_CFG2_PB17_SHIFT (4) +#define PIO_CFG2_PB17_MASK (7 << PIO_CFG2_PB17_SHIFT) +# define PIO_CFG2_PB17_INPUT (0 << PIO_CFG2_PB17_SHIFT) +# define PIO_CFG2_PB17_OUTPUT (1 << PIO_CFG2_PB17_SHIFT) +# define PIO_CFG2_PB17_SPI2_MISO (2 << PIO_CFG2_PB17_SHIFT) +# define PIO_CFG2_PB17_JTAG_DI0 (3 << PIO_CFG2_PB17_SHIFT) +#define PIO_CFG2_PB18_SHIFT (8) +#define PIO_CFG2_PB18_MASK (7 << PIO_CFG2_PB18_SHIFT) +# define PIO_CFG2_PB18_INPUT (0 << PIO_CFG2_PB18_SHIFT) +# define PIO_CFG2_PB18_OUTPUT (1 << PIO_CFG2_PB18_SHIFT) +# define PIO_CFG2_PB18_TWI1_SCK (2 << PIO_CFG2_PB18_SHIFT) +#define PIO_CFG2_PB19_SHIFT (12) +#define PIO_CFG2_PB19_MASK (7 << PIO_CFG2_PB19_SHIFT) +# define PIO_CFG2_PB19_INPUT (0 << PIO_CFG2_PB19_SHIFT) +# define PIO_CFG2_PB19_OUTPUT (1 << PIO_CFG2_PB19_SHIFT) +# define PIO_CFG2_PB19_TWI1_SDA (2 << PIO_CFG2_PB19_SHIFT) +#define PIO_CFG2_PB20_SHIFT (16) +#define PIO_CFG2_PB20_MASK (7 << PIO_CFG2_PB20_SHIFT) +# define PIO_CFG2_PB20_INPUT (0 << PIO_CFG2_PB20_SHIFT) +# define PIO_CFG2_PB20_OUTPUT (1 << PIO_CFG2_PB20_SHIFT) +# define PIO_CFG2_PB20_TWI2_SCK (2 << PIO_CFG2_PB20_SHIFT) +#define PIO_CFG2_PB21_SHIFT (20) +#define PIO_CFG2_PB21_MASK (7 << PIO_CFG2_PB21_SHIFT) +# define PIO_CFG2_PB21_INPUT (0 << PIO_CFG2_PB21_SHIFT) +# define PIO_CFG2_PB21_OUTPUT (1 << PIO_CFG2_PB21_SHIFT) +# define PIO_CFG2_PB21_TWI2_SDA (2 << PIO_CFG2_PB21_SHIFT) +#define PIO_CFG2_PB22_SHIFT (24) +#define PIO_CFG2_PB22_MASK (7 << PIO_CFG2_PB22_SHIFT) +# define PIO_CFG2_PB22_INPUT (0 << PIO_CFG2_PB22_SHIFT) +# define PIO_CFG2_PB22_OUTPUT (1 << PIO_CFG2_PB22_SHIFT) +# define PIO_CFG2_PB22_UART0_TX (2 << PIO_CFG2_PB22_SHIFT) +# define PIO_CFG2_PB22_IR1_TX (3 << PIO_CFG2_PB22_SHIFT) +#define PIO_CFG2_PB23_SHIFT (28) +#define PIO_CFG2_PB23_MASK (7 << PIO_CFG2_PB23_SHIFT) +# define PIO_CFG2_PB23_INPUT (0 << PIO_CFG2_PB23_SHIFT) +# define PIO_CFG2_PB23_OUTPUT (1 << PIO_CFG2_PB23_SHIFT) +# define PIO_CFG2_PB23_UART0_RX (2 << PIO_CFG2_PB23_SHIFT) +# define PIO_CFG2_PB23_IR1_RX (3 << PIO_CFG2_PB23_SHIFT) + +/* Port B Configure Register 3 (not used) */ + +/* Port C Configure Register 0 */ + +#define PIO_CFG0_PC0_SHIFT (0) +#define PIO_CFG0_PC0_MASK (7 << PIO_CFG0_PC0_SHIFT) +# define PIO_CFG0_PC0_INPUT (0 << PIO_CFG0_PC0_SHIFT) +# define PIO_CFG0_PC0_OUTPUT (1 << PIO_CFG0_PC0_SHIFT) +# define PIO_CFG0_PC0_NWE (2 << PIO_CFG0_PC0_SHIFT) +# define PIO_CFG0_PC0_SPI0_MOSI (3 << PIO_CFG0_PC0_SHIFT) +#define PIO_CFG0_PC1_SHIFT (4) +#define PIO_CFG0_PC1_MASK (7 << PIO_CFG0_PC1_SHIFT) +# define PIO_CFG0_PC1_INPUT (0 << PIO_CFG0_PC1_SHIFT) +# define PIO_CFG0_PC1_OUTPUT (1 << PIO_CFG0_PC1_SHIFT) +# define PIO_CFG0_PC1_NALE (2 << PIO_CFG0_PC1_SHIFT) +# define PIO_CFG0_PC1_SPI0_MISO (3 << PIO_CFG0_PC1_SHIFT) +#define PIO_CFG0_PC2_SHIFT (8) +#define PIO_CFG0_PC2_MASK (7 << PIO_CFG0_PC2_SHIFT) +# define PIO_CFG0_PC2_INPUT (0 << PIO_CFG0_PC2_SHIFT) +# define PIO_CFG0_PC2_OUTPUT (1 << PIO_CFG0_PC2_SHIFT) +# define PIO_CFG0_PC2_NCLE (2 << PIO_CFG0_PC2_SHIFT) +# define PIO_CFG0_PC2_SPI0_CLK (3 << PIO_CFG0_PC2_SHIFT) +#define PIO_CFG0_PC3_SHIFT (12) +#define PIO_CFG0_PC3_MASK (7 << PIO_CFG0_PC3_SHIFT) +# define PIO_CFG0_PC3_INPUT (0 << PIO_CFG0_PC3_SHIFT) +# define PIO_CFG0_PC3_OUTPUT (1 << PIO_CFG0_PC3_SHIFT) +# define PIO_CFG0_PC3_NCE1 (3 << PIO_CFG0_PC3_SHIFT) +#define PIO_CFG0_PC4_SHIFT (16) +#define PIO_CFG0_PC4_MASK (7 << PIO_CFG0_PC4_SHIFT) +# define PIO_CFG0_PC4_INPUT (0 << PIO_CFG0_PC4_SHIFT) +# define PIO_CFG0_PC4_OUTPUT (1 << PIO_CFG0_PC4_SHIFT) +# define PIO_CFG0_PC4_NCE0 (2 << PIO_CFG0_PC4_SHIFT) +#define PIO_CFG0_PC5_SHIFT (20) +#define PIO_CFG0_PC5_MASK (7 << PIO_CFG0_PC5_SHIFT) +# define PIO_CFG0_PC5_INPUT (0 << PIO_CFG0_PC5_SHIFT) +# define PIO_CFG0_PC5_OUTPUT (1 << PIO_CFG0_PC5_SHIFT) +# define PIO_CFG0_PC5_NRE (2 << PIO_CFG0_PC5_SHIFT) +#define PIO_CFG0_PC6_SHIFT (24) +#define PIO_CFG0_PC6_MASK (7 << PIO_CFG0_PC6_SHIFT) +# define PIO_CFG0_PC6_INPUT (0 << PIO_CFG0_PC6_SHIFT) +# define PIO_CFG0_PC6_OUTPUT (1 << PIO_CFG0_PC6_SHIFT) +# define PIO_CFG0_PC6_NRB0 (2 << PIO_CFG0_PC6_SHIFT) +# define PIO_CFG0_PC6_SDC2_CMD (3 << PIO_CFG0_PC6_SHIFT) +#define PIO_CFG0_PC7_SHIFT (28) +#define PIO_CFG0_PC7_MASK (7 << PIO_CFG0_PC7_SHIFT) +# define PIO_CFG0_PC7_INPUT (0 << PIO_CFG0_PC7_SHIFT) +# define PIO_CFG0_PC7_OUTPUT (1 << PIO_CFG0_PC7_SHIFT) +# define PIO_CFG0_PC7_NRB1 (2 << PIO_CFG0_PC7_SHIFT) +# define PIO_CFG0_PC7_SDC2_CLK (3 << PIO_CFG0_PC7_SHIFT) + +/* Port C Configure Register 1 */ + +#define PIO_CFG1_PC8_SHIFT (0) +#define PIO_CFG1_PC8_MASK (7 << PIO_CFG1_PC8_SHIFT) +# define PIO_CFG1_PC8_INPUT (0 << PIO_CFG1_PC8_SHIFT) +# define PIO_CFG1_PC8_OUTPUT (1 << PIO_CFG1_PC8_SHIFT) +# define PIO_CFG1_PC8_NDQ0 (2 << PIO_CFG1_PC8_SHIFT) +# define PIO_CFG1_PC8_SDC2_D0 (3 << PIO_CFG1_PC8_SHIFT) +#define PIO_CFG1_PC9_SHIFT (4) +#define PIO_CFG1_PC9_MASK (7 << PIO_CFG1_PC9_SHIFT) +# define PIO_CFG1_PC9_INPUT (0 << PIO_CFG1_PC9_SHIFT) +# define PIO_CFG1_PC9_OUTPUT (1 << PIO_CFG1_PC9_SHIFT) +# define PIO_CFG1_PC9_NDQ1 (2 << PIO_CFG1_PC9_SHIFT) +# define PIO_CFG1_PC9_SDC2_D1 (3 << PIO_CFG1_PC9_SHIFT) +#define PIO_CFG1_PC10_SHIFT (8) +#define PIO_CFG1_PC10_MASK (3 << PIO_CFG1_PC10_SHIFT) +# define PIO_CFG1_PC10_INPUT (0 << PIO_CFG1_PC10_SHIFT) +# define PIO_CFG1_PC10_OUTPUT (1 << PIO_CFG1_PC10_SHIFT) +# define PIO_CFG1_PC10_NDQ2 (2 << PIO_CFG1_PC10_SHIFT) +# define PIO_CFG1_PC10_SDC2_D2 (3 << PIO_CFG1_PC10_SHIFT) +#define PIO_CFG1_PC11_SHIFT (12) +#define PIO_CFG1_PC11_MASK (3 << PIO_CFG1_PC11_SHIFT) +# define PIO_CFG1_PC11_INPUT (0 << PIO_CFG1_PC11_SHIFT) +# define PIO_CFG1_PC11_OUTPUT (1 << PIO_CFG1_PC11_SHIFT) +# define PIO_CFG1_PC11_NDQ3 (2 << PIO_CFG1_PC11_SHIFT) +# define PIO_CFG1_PC11_SDC2_D3 (3 << PIO_CFG1_PC11_SHIFT) +#define PIO_CFG1_PC12_SHIFT (16) +#define PIO_CFG1_PC12_MASK (3 << PIO_CFG1_PC12_SHIFT) +# define PIO_CFG1_PC12_INPUT (0 << PIO_CFG1_PC12_SHIFT) +# define PIO_CFG1_PC12_OUTPUT (1 << PIO_CFG1_PC12_SHIFT) +# define PIO_CFG1_PC12_NDQ4 (2 << PIO_CFG1_PC12_SHIFT) +#define PIO_CFG1_PC13_SHIFT (20) +#define PIO_CFG1_PC13_MASK (3 << PIO_CFG1_PC13_SHIFT) +# define PIO_CFG1_PC13_INPUT (0 << PIO_CFG1_PC13_SHIFT) +# define PIO_CFG1_PC13_OUTPUT (1 << PIO_CFG1_PC13_SHIFT) +# define PIO_CFG1_PC13_NDQ5 (2 << PIO_CFG1_PC13_SHIFT) +#define PIO_CFG1_PC14_SHIFT (24) +#define PIO_CFG1_PC14_MASK (3 << PIO_CFG1_PC14_SHIFT) +# define PIO_CFG1_PC14_INPUT (0 << PIO_CFG1_PC14_SHIFT) +# define PIO_CFG1_PC14_OUTPUT (1 << PIO_CFG1_PC14_SHIFT) +# define PIO_CFG1_PC14_NDQ6 (2 << PIO_CFG1_PC14_SHIFT) +#define PIO_CFG1_PC15_SHIFT (28) +#define PIO_CFG1_PC15_MASK (3 << PIO_CFG1_PC15_SHIFT) +# define PIO_CFG1_PC15_INPUT (0 << PIO_CFG1_PC15_SHIFT) +# define PIO_CFG1_PC15_OUTPUT (1 << PIO_CFG1_PC15_SHIFT) +# define PIO_CFG1_PC15_NDQ7 (2 << PIO_CFG1_PC15_SHIFT) + +/* Port C Configure Register 2 */ + +#define PIO_CFG2_PC16_SHIFT (0) +#define PIO_CFG2_PC16_MASK (7 << PIO_CFG2_PC16_SHIFT) +# define PIO_CFG2_PC16_INPUT (0 << PIO_CFG2_PC16_SHIFT) +# define PIO_CFG2_PC16_OUTPUT (1 << PIO_CFG2_PC16_SHIFT) +# define PIO_CFG2_PC16_NWP (2 << PIO_CFG2_PC16_SHIFT) +#define PIO_CFG2_PC17_SHIFT (4) +#define PIO_CFG2_PC17_MASK (7 << PIO_CFG2_PC17_SHIFT) +# define PIO_CFG2_PC17_INPUT (0 << PIO_CFG2_PC17_SHIFT) +# define PIO_CFG2_PC17_OUTPUT (1 << PIO_CFG2_PC17_SHIFT) +# define PIO_CFG2_PC17_NCE2 (2 << PIO_CFG2_PC17_SHIFT) +#define PIO_CFG2_PC18_SHIFT (8) +#define PIO_CFG2_PC18_MASK (7 << PIO_CFG2_PC18_SHIFT) +# define PIO_CFG2_PC18_INPUT (0 << PIO_CFG2_PC18_SHIFT) +# define PIO_CFG2_PC18_OUTPUT (1 << PIO_CFG2_PC18_SHIFT) +# define PIO_CFG2_PC18_NCE3 (2 << PIO_CFG2_PC18_SHIFT) +#define PIO_CFG2_PC19_SHIFT (12) +#define PIO_CFG2_PC19_MASK (7 << PIO_CFG2_PC19_SHIFT) +# define PIO_CFG2_PC19_INPUT (0 << PIO_CFG2_PC19_SHIFT) +# define PIO_CFG2_PC19_OUTPUT (1 << PIO_CFG2_PC19_SHIFT) +# define PIO_CFG2_PC19_NCE4 (2 << PIO_CFG2_PC19_SHIFT) +# define PIO_CFG2_PC19_SPI2_CS0 (3 << PIO_CFG2_PC19_SHIFT) +#define PIO_CFG2_PC20_SHIFT (16) +#define PIO_CFG2_PC20_MASK (7 << PIO_CFG2_PC20_SHIFT) +# define PIO_CFG2_PC20_INPUT (0 << PIO_CFG2_PC20_SHIFT) +# define PIO_CFG2_PC20_OUTPUT (1 << PIO_CFG2_PC20_SHIFT) +# define PIO_CFG2_PC20_NCE5 (2 << PIO_CFG2_PC20_SHIFT) +# define PIO_CFG2_PC20_SPI2_CLK (3 << PIO_CFG2_PC20_SHIFT) +#define PIO_CFG2_PC21_SHIFT (20) +#define PIO_CFG2_PC21_MASK (7 << PIO_CFG2_PC21_SHIFT) +# define PIO_CFG2_PC21_INPUT (0 << PIO_CFG2_PC21_SHIFT) +# define PIO_CFG2_PC21_OUTPUT (1 << PIO_CFG2_PC21_SHIFT) +# define PIO_CFG2_PC21_NCE6 (2 << PIO_CFG2_PC21_SHIFT) +# define PIO_CFG2_PC21_SPI2_MOSI (3 << PIO_CFG2_PC21_SHIFT) +#define PIO_CFG2_PC22_SHIFT (24) +#define PIO_CFG2_PC22_MASK (7 << PIO_CFG2_PC22_SHIFT) +# define PIO_CFG2_PC22_INPUT (0 << PIO_CFG2_PC22_SHIFT) +# define PIO_CFG2_PC22_OUTPUT (1 << PIO_CFG2_PC22_SHIFT) +# define PIO_CFG2_PC22_NCE7 (2 << PIO_CFG2_PC22_SHIFT) +# define PIO_CFG2_PC22_SPI2_MISO (3 << PIO_CFG2_PC22_SHIFT) +#define PIO_CFG2_PC23_SHIFT (28) +#define PIO_CFG2_PC23_MASK (7 << PIO_CFG2_PC23_SHIFT) +# define PIO_CFG2_PC23_INPUT (0 << PIO_CFG2_PC23_SHIFT) +# define PIO_CFG2_PC23_OUTPUT (1 << PIO_CFG2_PC23_SHIFT) +# define PIO_CFG2_PC23_SPI0_CS0 (3 << PIO_CFG2_PC23_SHIFT) + +/* Port C Configure Register 3 */ + +#define PIO_CFG2_PC24_SHIFT (0) +#define PIO_CFG2_PC24_MASK (7 << PIO_CFG2_PC24_SHIFT) +# define PIO_CFG2_PC24_INPUT (0 << PIO_CFG2_PC24_SHIFT) +# define PIO_CFG2_PC24_OUTPUT (1 << PIO_CFG2_PC24_SHIFT) +# define PIO_CFG2_PC24_NDQS (2 << PIO_CFG2_PC24_SHIFT) + +/* Port D Configure Register 0 */ + +#define PIO_CFG0_PD0_SHIFT (0) +#define PIO_CFG0_PD0_MASK (7 << PIO_CFG0_PD0_SHIFT) +# define PIO_CFG0_PD0_INPUT (0 << PIO_CFG0_PD0_SHIFT) +# define PIO_CFG0_PD0_OUTPUT (1 << PIO_CFG0_PD0_SHIFT) +# define PIO_CFG0_PD0_LCD0_D0 (2 << PIO_CFG0_PD0_SHIFT) +# define PIO_CFG0_PD0_LVDS0_VP0 (3 << PIO_CFG0_PD0_SHIFT) +#define PIO_CFG0_PD1_SHIFT (4) +#define PIO_CFG0_PD1_MASK (7 << PIO_CFG0_PD1_SHIFT) +# define PIO_CFG0_PD1_INPUT (0 << PIO_CFG0_PD1_SHIFT) +# define PIO_CFG0_PD1_OUTPUT (1 << PIO_CFG0_PD1_SHIFT) +# define PIO_CFG0_PD1_LCD0_D1 (2 << PIO_CFG0_PD1_SHIFT) +# define PIO_CFG0_PD1_LVDS0_VN0 (3 << PIO_CFG0_PD1_SHIFT) +#define PIO_CFG0_PD2_SHIFT (8) +#define PIO_CFG0_PD2_MASK (7 << PIO_CFG0_PD2_SHIFT) +# define PIO_CFG0_PD2_INPUT (0 << PIO_CFG0_PD2_SHIFT) +# define PIO_CFG0_PD2_OUTPUT (1 << PIO_CFG0_PD2_SHIFT) +# define PIO_CFG0_PD2_LCD0_D2 (2 << PIO_CFG0_PD2_SHIFT) +# define PIO_CFG0_PD2_LVDS0_VP1 (3 << PIO_CFG0_PD2_SHIFT) +#define PIO_CFG0_PD3_SHIFT (12) +#define PIO_CFG0_PD3_MASK (7 << PIO_CFG0_PD3_SHIFT) +# define PIO_CFG0_PD3_INPUT (0 << PIO_CFG0_PD3_SHIFT) +# define PIO_CFG0_PD3_OUTPUT (1 << PIO_CFG0_PD3_SHIFT) +# define PIO_CFG0_PD3_LCD0_D3 (2 << PIO_CFG0_PD3_SHIFT) +# define PIO_CFG0_PD3_LVDS0_VN1 (3 << PIO_CFG0_PD3_SHIFT) +#define PIO_CFG0_PD4_SHIFT (16) +#define PIO_CFG0_PD4_MASK (7 << PIO_CFG0_PD4_SHIFT) +# define PIO_CFG0_PD4_INPUT (0 << PIO_CFG0_PD4_SHIFT) +# define PIO_CFG0_PD4_OUTPUT (1 << PIO_CFG0_PD4_SHIFT) +# define PIO_CFG0_PD4_LCD0_D4 (2 << PIO_CFG0_PD4_SHIFT) +# define PIO_CFG0_PD4_LVDS0_VP2 (3 << PIO_CFG0_PD4_SHIFT) +#define PIO_CFG0_PD5_SHIFT (20) +#define PIO_CFG0_PD5_MASK (7 << PIO_CFG0_PD5_SHIFT) +# define PIO_CFG0_PD5_INPUT (0 << PIO_CFG0_PD5_SHIFT) +# define PIO_CFG0_PD5_OUTPUT (1 << PIO_CFG0_PD5_SHIFT) +# define PIO_CFG0_PD5_LCD0_D5 (2 << PIO_CFG0_PD5_SHIFT) +# define PIO_CFG0_PD5_LVDS0_VN2 (3 << PIO_CFG0_PD5_SHIFT) +#define PIO_CFG0_PD6_SHIFT (24) +#define PIO_CFG0_PD6_MASK (7 << PIO_CFG0_PD6_SHIFT) +# define PIO_CFG0_PD6_INPUT (0 << PIO_CFG0_PD6_SHIFT) +# define PIO_CFG0_PD6_OUTPUT (1 << PIO_CFG0_PD6_SHIFT) +# define PIO_CFG0_PD6_LCD0_D6 (2 << PIO_CFG0_PD6_SHIFT) +# define PIO_CFG0_PD6_LVDS0_VPC (3 << PIO_CFG0_PD6_SHIFT) +#define PIO_CFG0_PD7_SHIFT (28) +#define PIO_CFG0_PD7_MASK (7 << PIO_CFG0_PD7_SHIFT) +# define PIO_CFG0_PD7_INPUT (0 << PIO_CFG0_PD7_SHIFT) +# define PIO_CFG0_PD7_OUTPUT (1 << PIO_CFG0_PD7_SHIFT) +# define PIO_CFG0_PD7_LCD0_D7 (2 << PIO_CFG0_PD7_SHIFT) +# define PIO_CFG0_PD7_LVDS0_VNC (3 << PIO_CFG0_PD7_SHIFT) + +/* Port D Configure Register 1 */ + +#define PIO_CFG1_PD8_SHIFT (0) +#define PIO_CFG1_PD8_MASK (7 << PIO_CFG1_PD8_SHIFT) +# define PIO_CFG1_PD8_INPUT (0 << PIO_CFG1_PD8_SHIFT) +# define PIO_CFG1_PD8_OUTPUT (1 << PIO_CFG1_PD8_SHIFT) +# define PIO_CFG1_PD8_LCD0_D8 (2 << PIO_CFG1_PD8_SHIFT) +# define PIO_CFG1_PD8_LVDS0_VP3 (3 << PIO_CFG1_PD8_SHIFT) +#define PIO_CFG1_PD9_SHIFT (4) +#define PIO_CFG1_PD9_MASK (7 << PIO_CFG1_PD9_SHIFT) +# define PIO_CFG1_PD9_INPUT (0 << PIO_CFG1_PD9_SHIFT) +# define PIO_CFG1_PD9_OUTPUT (1 << PIO_CFG1_PD9_SHIFT) +# define PIO_CFG1_PD9_LCD0_D9 (2 << PIO_CFG1_PD9_SHIFT) +# define PIO_CFG1_PD9_LVDS0_VM3 (3 << PIO_CFG1_PD9_SHIFT) +#define PIO_CFG1_PD10_SHIFT (8) +#define PIO_CFG1_PD10_MASK (3 << PIO_CFG1_PD10_SHIFT) +# define PIO_CFG1_PD10_INPUT (0 << PIO_CFG1_PD10_SHIFT) +# define PIO_CFG1_PD10_OUTPUT (1 << PIO_CFG1_PD10_SHIFT) +# define PIO_CFG1_PD10_LCD0_D10 (2 << PIO_CFG1_PD10_SHIFT) +# define PIO_CFG1_PD10_LVDS1_VP0 (3 << PIO_CFG1_PD10_SHIFT) +#define PIO_CFG1_PD11_SHIFT (12) +#define PIO_CFG1_PD11_MASK (3 << PIO_CFG1_PD11_SHIFT) +# define PIO_CFG1_PD11_INPUT (0 << PIO_CFG1_PD11_SHIFT) +# define PIO_CFG1_PD11_OUTPUT (1 << PIO_CFG1_PD11_SHIFT) +# define PIO_CFG1_PD11_LCD0_D11 (2 << PIO_CFG1_PD11_SHIFT) +# define PIO_CFG1_PD11_LVDS1_VN0 (3 << PIO_CFG1_PD11_SHIFT) +#define PIO_CFG1_PD12_SHIFT (16) +#define PIO_CFG1_PD12_MASK (3 << PIO_CFG1_PD12_SHIFT) +# define PIO_CFG1_PD12_INPUT (0 << PIO_CFG1_PD12_SHIFT) +# define PIO_CFG1_PD12_OUTPUT (1 << PIO_CFG1_PD12_SHIFT) +# define PIO_CFG1_PD12_LCD0_D12 (2 << PIO_CFG1_PD12_SHIFT) +# define PIO_CFG1_PD12_LVDS1_VP1 (3 << PIO_CFG1_PD12_SHIFT) +#define PIO_CFG1_PD13_SHIFT (20) +#define PIO_CFG1_PD13_MASK (3 << PIO_CFG1_PD13_SHIFT) +# define PIO_CFG1_PD13_INPUT (0 << PIO_CFG1_PD13_SHIFT) +# define PIO_CFG1_PD13_OUTPUT (1 << PIO_CFG1_PD13_SHIFT) +# define PIO_CFG1_PD13_LCD0_D13 (2 << PIO_CFG1_PD13_SHIFT) +# define PIO_CFG1_PD13_LVDS1_VN (3 << PIO_CFG1_PD13_SHIFT) +#define PIO_CFG1_PD14_SHIFT (24) +#define PIO_CFG1_PD14_MASK (3 << PIO_CFG1_PD14_SHIFT) +# define PIO_CFG1_PD14_INPUT (0 << PIO_CFG1_PD14_SHIFT) +# define PIO_CFG1_PD14_OUTPUT (1 << PIO_CFG1_PD14_SHIFT) +# define PIO_CFG1_PD14_LCD0_D14 (2 << PIO_CFG1_PD14_SHIFT) +# define PIO_CFG1_PD14_LVDS1_VP2 (3 << PIO_CFG1_PD14_SHIFT) +#define PIO_CFG1_PD15_SHIFT (28) +#define PIO_CFG1_PD15_MASK (3 << PIO_CFG1_PD15_SHIFT) +# define PIO_CFG1_PD15_INPUT (0 << PIO_CFG1_PD15_SHIFT) +# define PIO_CFG1_PD15_OUTPUT (1 << PIO_CFG1_PD15_SHIFT) +# define PIO_CFG1_PD15_LCD0_D15 (2 << PIO_CFG1_PD15_SHIFT) +# define PIO_CFG1_PD15_LVDS1_VN2 (3 << PIO_CFG1_PD15_SHIFT) + +/* Port D Configure Register 2 */ + +#define PIO_CFG2_PD16_SHIFT (0) +#define PIO_CFG2_PD16_MASK (7 << PIO_CFG2_PD16_SHIFT) +# define PIO_CFG2_PD16_INPUT (0 << PIO_CFG2_PD16_SHIFT) +# define PIO_CFG2_PD16_OUTPUT (1 << PIO_CFG2_PD16_SHIFT) +# define PIO_CFG2_PD16_LCD0_D16 (2 << PIO_CFG2_PD16_SHIFT) +# define PIO_CFG2_PD16_LVDS1_VPC (3 << PIO_CFG2_PD16_SHIFT) +#define PIO_CFG2_PD17_SHIFT (4) +#define PIO_CFG2_PD17_MASK (7 << PIO_CFG2_PD17_SHIFT) +# define PIO_CFG2_PD17_INPUT (0 << PIO_CFG2_PD17_SHIFT) +# define PIO_CFG2_PD17_OUTPUT (1 << PIO_CFG2_PD17_SHIFT) +# define PIO_CFG2_PD17_CD0_D17 (2 << PIO_CFG2_PD17_SHIFT) +# define PIO_CFG2_PD17_LVDS1_VNC (3 << PIO_CFG2_PD17_SHIFT) +#define PIO_CFG2_PD18_SHIFT (8) +#define PIO_CFG2_PD18_MASK (7 << PIO_CFG2_PD18_SHIFT) +# define PIO_CFG2_PD18_INPUT (0 << PIO_CFG2_PD18_SHIFT) +# define PIO_CFG2_PD18_OUTPUT (1 << PIO_CFG2_PD18_SHIFT) +# define PIO_CFG2_PD18_LCD0_D18 (2 << PIO_CFG2_PD18_SHIFT) +# define PIO_CFG2_PD18_LVDS1_VP3 (3 << PIO_CFG2_PD18_SHIFT) +#define PIO_CFG2_PD19_SHIFT (12) +#define PIO_CFG2_PD19_MASK (7 << PIO_CFG2_PD19_SHIFT) +# define PIO_CFG2_PD19_INPUT (0 << PIO_CFG2_PD19_SHIFT) +# define PIO_CFG2_PD19_OUTPUT (1 << PIO_CFG2_PD19_SHIFT) +# define PIO_CFG2_PD19_LCD0_D19 (2 << PIO_CFG2_PD19_SHIFT) +# define PIO_CFG2_PD19_LVDS1_VN3 (3 << PIO_CFG2_PD19_SHIFT) +#define PIO_CFG2_PD20_SHIFT (16) +#define PIO_CFG2_PD20_MASK (7 << PIO_CFG2_PD20_SHIFT) +# define PIO_CFG2_PD20_INPUT (0 << PIO_CFG2_PD20_SHIFT) +# define PIO_CFG2_PD20_OUTPUT (1 << PIO_CFG2_PD20_SHIFT) +# define PIO_CFG2_PD20_LCD0_D20 (2 << PIO_CFG2_PD20_SHIFT) +# define PIO_CFG2_PD20_CSI1_MCLK (3 << PIO_CFG2_PD20_SHIFT) +#define PIO_CFG2_PD21_SHIFT (20) +#define PIO_CFG2_PD21_MASK (7 << PIO_CFG2_PD21_SHIFT) +# define PIO_CFG2_PD21_INPUT (0 << PIO_CFG2_PD21_SHIFT) +# define PIO_CFG2_PD21_OUTPUT (1 << PIO_CFG2_PD21_SHIFT) +# define PIO_CFG2_PD21_LCD0_D21 (2 << PIO_CFG2_PD21_SHIFT) +# define PIO_CFG2_PD21_SMC_VPPEN (3 << PIO_CFG2_PD21_SHIFT) +#define PIO_CFG2_PD22_SHIFT (24) +#define PIO_CFG2_PD22_MASK (7 << PIO_CFG2_PD22_SHIFT) +# define PIO_CFG2_PD22_INPUT (0 << PIO_CFG2_PD22_SHIFT) +# define PIO_CFG2_PD22_OUTPUT (1 << PIO_CFG2_PD22_SHIFT) +# define PIO_CFG2_PD22_LCD0_D22 (2 << PIO_CFG2_PD22_SHIFT) +# define PIO_CFG2_PD22_SMC_VPPPP (3 << PIO_CFG2_PD22_SHIFT) +#define PIO_CFG2_PD23_SHIFT (28) +#define PIO_CFG2_PD23_MASK (7 << PIO_CFG2_PD23_SHIFT) +# define PIO_CFG2_PD23_INPUT (0 << PIO_CFG2_PD23_SHIFT) +# define PIO_CFG2_PD23_OUTPUT (1 << PIO_CFG2_PD23_SHIFT) +# define PIO_CFG2_PD23_LCD0_D23 (2 << PIO_CFG2_PD23_SHIFT) +# define PIO_CFG2_PD23_SMC_DET (3 << PIO_CFG2_PD23_SHIFT) + +/* Port D Configure Register 3 */ + +#define PIO_CFG2_PD24_SHIFT (0) +#define PIO_CFG2_PD24_MASK (7 << PIO_CFG2_PD24_SHIFT) +# define PIO_CFG2_PD24_INPUT (0 << PIO_CFG2_PD24_SHIFT) +# define PIO_CFG2_PD24_OUTPUT (1 << PIO_CFG2_PD24_SHIFT) +# define PIO_CFG2_PD24_LCD0_CLK (2 << PIO_CFG2_PD24_SHIFT) +# define PIO_CFG2_PD24_SMC_VCCEN (3 << PIO_CFG2_PD24_SHIFT) +#define PIO_CFG2_PD25_SHIFT (4) +#define PIO_CFG2_PD25_MASK (7 << PIO_CFG2_PD25_SHIFT) +# define PIO_CFG2_PD25_INPUT (0 << PIO_CFG2_PD25_SHIFT) +# define PIO_CFG2_PD25_OUTPUT (1 << PIO_CFG2_PD25_SHIFT) +# define PIO_CFG2_PD25_LCD0_DE (2 << PIO_CFG2_PD25_SHIFT) +# define PIO_CFG2_PD25_SMC_RST (3 << PIO_CFG2_PD25_SHIFT) +#define PIO_CFG2_PD26_SHIFT (8) +#define PIO_CFG2_PD26_MASK (7 << PIO_CFG2_PD26_SHIFT) +# define PIO_CFG2_PD26_INPUT (0 << PIO_CFG2_PD26_SHIFT) +# define PIO_CFG2_PD26_OUTPUT (1 << PIO_CFG2_PD26_SHIFT) +# define PIO_CFG2_PD26_LCD0_HSYNC (2 << PIO_CFG2_PD26_SHIFT) +# define PIO_CFG2_PD26_SMC_SCK (3 << PIO_CFG2_PD26_SHIFT) +#define PIO_CFG2_PD27_SHIFT (12) +#define PIO_CFG2_PD27_MASK (7 << PIO_CFG2_PD27_SHIFT) +# define PIO_CFG2_PD27_INPUT (0 << PIO_CFG2_PD27_SHIFT) +# define PIO_CFG2_PD27_OUTPUT (1 << PIO_CFG2_PD27_SHIFT) +# define PIO_CFG2_PD27_LCD0_VSYNC (2 << PIO_CFG2_PD27_SHIFT) +# define PIO_CFG2_PD27_SMC_SDA (3 << PIO_CFG2_PD27_SHIFT) + +/* Port E Configure Register 0 */ + +#define PIO_CFG0_PE0_SHIFT (0) +#define PIO_CFG0_PE0_MASK (7 << PIO_CFG0_PE0_SHIFT) +# define PIO_CFG0_PE0_INPUT (0 << PIO_CFG0_PE0_SHIFT) +# define PIO_CFG0_PE0_OUTPUT (1 << PIO_CFG0_PE0_SHIFT) +# define PIO_CFG0_PE0_TS0_CLK (2 << PIO_CFG0_PE0_SHIFT) +# define PIO_CFG0_PE0_CSI0_PCK (3 << PIO_CFG0_PE0_SHIFT) +#define PIO_CFG0_PE1_SHIFT (4) +#define PIO_CFG0_PE1_MASK (7 << PIO_CFG0_PE1_SHIFT) +# define PIO_CFG0_PE1_INPUT (0 << PIO_CFG0_PE1_SHIFT) +# define PIO_CFG0_PE1_OUTPUT (1 << PIO_CFG0_PE1_SHIFT) +# define PIO_CFG0_PE1_TS0_ERR (2 << PIO_CFG0_PE1_SHIFT) +# define PIO_CFG0_PE1_CSI0_CK (3 << PIO_CFG0_PE1_SHIFT) +#define PIO_CFG0_PE2_SHIFT (8) +#define PIO_CFG0_PE2_MASK (7 << PIO_CFG0_PE2_SHIFT) +# define PIO_CFG0_PE2_INPUT (0 << PIO_CFG0_PE2_SHIFT) +# define PIO_CFG0_PE2_OUTPUT (1 << PIO_CFG0_PE2_SHIFT) +# define PIO_CFG0_PE2_TS0_SYNC (2 << PIO_CFG0_PE2_SHIFT) +# define PIO_CFG0_PE2_CSI0_HSYNC (3 << PIO_CFG0_PE2_SHIFT) +#define PIO_CFG0_PE3_SHIFT (12) +#define PIO_CFG0_PE3_MASK (7 << PIO_CFG0_PE3_SHIFT) +# define PIO_CFG0_PE3_INPUT (0 << PIO_CFG0_PE3_SHIFT) +# define PIO_CFG0_PE3_OUTPUT (1 << PIO_CFG0_PE3_SHIFT) +# define PIO_CFG0_PE3_TS0_DVLD (2 << PIO_CFG0_PE3_SHIFT) +# define PIO_CFG0_PE3_CSI0_VSYNC (3 << PIO_CFG0_PE3_SHIFT) +#define PIO_CFG0_PE4_SHIFT (16) +#define PIO_CFG0_PE4_MASK (7 << PIO_CFG0_PE4_SHIFT) +# define PIO_CFG0_PE4_INPUT (0 << PIO_CFG0_PE4_SHIFT) +# define PIO_CFG0_PE4_OUTPUT (1 << PIO_CFG0_PE4_SHIFT) +# define PIO_CFG0_PE4_TS0_D0 (2 << PIO_CFG0_PE4_SHIFT) +# define PIO_CFG0_PE4_CSI0_D0 (3 << PIO_CFG0_PE4_SHIFT) +#define PIO_CFG0_PE5_SHIFT (20) +#define PIO_CFG0_PE5_MASK (7 << PIO_CFG0_PE5_SHIFT) +# define PIO_CFG0_PE5_INPUT (0 << PIO_CFG0_PE5_SHIFT) +# define PIO_CFG0_PE5_OUTPUT (1 << PIO_CFG0_PE5_SHIFT) +# define PIO_CFG0_PE5_TS0_D1 (2 << PIO_CFG0_PE5_SHIFT) +# define PIO_CFG0_PE5_CSI0_D1 (3 << PIO_CFG0_PE5_SHIFT) +# define PIO_CFG0_PE5_SMC_VPPEN (4 << PIO_CFG0_PE5_SHIFT) +#define PIO_CFG0_PE6_SHIFT (24) +#define PIO_CFG0_PE6_MASK (7 << PIO_CFG0_PE6_SHIFT) +# define PIO_CFG0_PE6_INPUT (0 << PIO_CFG0_PE6_SHIFT) +# define PIO_CFG0_PE6_OUTPUT (1 << PIO_CFG0_PE6_SHIFT) +# define PIO_CFG0_PE6_TS0_D2 (2 << PIO_CFG0_PE6_SHIFT) +# define PIO_CFG0_PE6_CSI0_D2 (3 << PIO_CFG0_PE6_SHIFT) +#define PIO_CFG0_PE7_SHIFT (28) +#define PIO_CFG0_PE7_MASK (7 << PIO_CFG0_PE7_SHIFT) +# define PIO_CFG0_PE7_INPUT (0 << PIO_CFG0_PE7_SHIFT) +# define PIO_CFG0_PE7_OUTPUT (1 << PIO_CFG0_PE7_SHIFT) +# define PIO_CFG0_PE7_TS0_D3 (2 << PIO_CFG0_PE7_SHIFT) +# define PIO_CFG0_PE7_CSI0_D3 (3 << PIO_CFG0_PE7_SHIFT) + +/* Port E Configure Register 1 */ + +#define PIO_CFG1_PE8_SHIFT (0) +#define PIO_CFG1_PE8_MASK (7 << PIO_CFG1_PE8_SHIFT) +# define PIO_CFG1_PE8_INPUT (0 << PIO_CFG1_PE8_SHIFT) +# define PIO_CFG1_PE8_OUTPUT (1 << PIO_CFG1_PE8_SHIFT) +# define PIO_CFG1_PE8_TS0_D4 (2 << PIO_CFG1_PE8_SHIFT) +# define PIO_CFG1_PE8_CSI0_D4 (3 << PIO_CFG1_PE8_SHIFT) +#define PIO_CFG1_PE9_SHIFT (4) +#define PIO_CFG1_PE9_MASK (7 << PIO_CFG1_PE9_SHIFT) +# define PIO_CFG1_PE9_INPUT (0 << PIO_CFG1_PE9_SHIFT) +# define PIO_CFG1_PE9_OUTPUT (1 << PIO_CFG1_PE9_SHIFT) +# define PIO_CFG1_PE9_TS0_D5 (2 << PIO_CFG1_PE9_SHIFT) +# define PIO_CFG1_PE9_CSI0_D5 (3 << PIO_CFG1_PE9_SHIFT) +#define PIO_CFG1_PE10_SHIFT (8) +#define PIO_CFG1_PE10_MASK (3 << PIO_CFG1_PE10_SHIFT) +# define PIO_CFG1_PE10_INPUT (0 << PIO_CFG1_PE10_SHIFT) +# define PIO_CFG1_PE10_OUTPUT (1 << PIO_CFG1_PE10_SHIFT) +# define PIO_CFG1_PE10_TS0_D6 (2 << PIO_CFG1_PE10_SHIFT) +# define PIO_CFG1_PE10_CSI0_D6 (3 << PIO_CFG1_PE10_SHIFT) +#define PIO_CFG1_PE11_SHIFT (12) +#define PIO_CFG1_PE11_MASK (3 << PIO_CFG1_PE11_SHIFT) +# define PIO_CFG1_PE11_INPUT (0 << PIO_CFG1_PE11_SHIFT) +# define PIO_CFG1_PE11_OUTPUT (1 << PIO_CFG1_PE11_SHIFT) +# define PIO_CFG1_PE11_TS0_D7 (2 << PIO_CFG1_PE11_SHIFT) +# define PIO_CFG1_PE11_CSI0_D7 (3 << PIO_CFG1_PE11_SHIFT) + +/* Port E Configure Register 2-3 (not used) */ + +/* Port F Configure Register 0 */ + +#define PIO_CFG0_PF0_SHIFT (0) +#define PIO_CFG0_PF0_MASK (7 << PIO_CFG0_PF0_SHIFT) +# define PIO_CFG0_PF0_INPUT (0 << PIO_CFG0_PF0_SHIFT) +# define PIO_CFG0_PF0_OUTPUT (1 << PIO_CFG0_PF0_SHIFT) +# define PIO_CFG0_PF0_SDC0_D1 (2 << PIO_CFG0_PF0_SHIFT) +# define PIO_CFG0_PF0_JTAG_MS1 (4 << PIO_CFG0_PF0_SHIFT) +#define PIO_CFG0_PF1_SHIFT (4) +#define PIO_CFG0_PF1_MASK (7 << PIO_CFG0_PF1_SHIFT) +# define PIO_CFG0_PF1_INPUT (0 << PIO_CFG0_PF1_SHIFT) +# define PIO_CFG0_PF1_OUTPUT (1 << PIO_CFG0_PF1_SHIFT) +# define PIO_CFG0_PF1_SDC0_D0 (2 << PIO_CFG0_PF1_SHIFT) +# define PIO_CFG0_PF1_JTAG_DI1 (4 << PIO_CFG0_PF1_SHIFT) +#define PIO_CFG0_PF2_SHIFT (8) +#define PIO_CFG0_PF2_MASK (7 << PIO_CFG0_PF2_SHIFT) +# define PIO_CFG0_PF2_INPUT (0 << PIO_CFG0_PF2_SHIFT) +# define PIO_CFG0_PF2_OUTPUT (1 << PIO_CFG0_PF2_SHIFT) +# define PIO_CFG0_PF2_SDC0_CLK (2 << PIO_CFG0_PF2_SHIFT) +# define PIO_CFG0_PF2_UART0_TX (4 << PIO_CFG0_PF2_SHIFT) +#define PIO_CFG0_PF3_SHIFT (12) +#define PIO_CFG0_PF3_MASK (7 << PIO_CFG0_PF3_SHIFT) +# define PIO_CFG0_PF3_INPUT (0 << PIO_CFG0_PF3_SHIFT) +# define PIO_CFG0_PF3_OUTPUT (1 << PIO_CFG0_PF3_SHIFT) +# define PIO_CFG0_PF3_SDC0_CMD (2 << PIO_CFG0_PF3_SHIFT) +# define PIO_CFG0_PF3_JTAG_DO1 (4 << PIO_CFG0_PF3_SHIFT) +#define PIO_CFG0_PF4_SHIFT (16) +#define PIO_CFG0_PF4_MASK (7 << PIO_CFG0_PF4_SHIFT) +# define PIO_CFG0_PF4_INPUT (0 << PIO_CFG0_PF4_SHIFT) +# define PIO_CFG0_PF4_OUTPUT (1 << PIO_CFG0_PF4_SHIFT) +# define PIO_CFG0_PF4_SDC0_D3 (2 << PIO_CFG0_PF4_SHIFT) +# define PIO_CFG0_PF4_UART0_RX (4 << PIO_CFG0_PF4_SHIFT) +#define PIO_CFG0_PF5_SHIFT (20) +#define PIO_CFG0_PF5_MASK (7 << PIO_CFG0_PF5_SHIFT) +# define PIO_CFG0_PF5_INPUT (0 << PIO_CFG0_PF5_SHIFT) +# define PIO_CFG0_PF5_OUTPUT (1 << PIO_CFG0_PF5_SHIFT) +# define PIO_CFG0_PF5_SDC0_D2 (2 << PIO_CFG0_PF5_SHIFT) +# define PIO_CFG0_PF5_JTAG_CK1 (4 << PIO_CFG0_PF5_SHIFT) + +/* Port F Configure Register 1-3 (not used) */ + +/* Port G Configure Register 0 */ + +#define PIO_CFG0_PG0_SHIFT (0) +#define PIO_CFG0_PG0_MASK (7 << PIO_CFG0_PG0_SHIFT) +# define PIO_CFG0_PG0_INPUT (0 << PIO_CFG0_PG0_SHIFT) +# define PIO_CFG0_PG0_OUTPUT (1 << PIO_CFG0_PG0_SHIFT) +# define PIO_CFG0_PG0_TS1_CLK (2 << PIO_CFG0_PG0_SHIFT) +# define PIO_CFG0_PG0_CSI1_PCK (3 << PIO_CFG0_PG0_SHIFT) +# define PIO_CFG0_PG0_SDC1_CMD (4 << PIO_CFG0_PG0_SHIFT) +#define PIO_CFG0_PG1_SHIFT (4) +#define PIO_CFG0_PG1_MASK (7 << PIO_CFG0_PG1_SHIFT) +# define PIO_CFG0_PG1_INPUT (0 << PIO_CFG0_PG1_SHIFT) +# define PIO_CFG0_PG1_OUTPUT (1 << PIO_CFG0_PG1_SHIFT) +# define PIO_CFG0_PG1_TS1_ERR (2 << PIO_CFG0_PG1_SHIFT) +# define PIO_CFG0_PG1_CSI1_CK (3 << PIO_CFG0_PG1_SHIFT) +# define PIO_CFG0_PG1_SDC1_CLK (4 << PIO_CFG0_PG1_SHIFT) +#define PIO_CFG0_PG2_SHIFT (8) +#define PIO_CFG0_PG2_MASK (7 << PIO_CFG0_PG2_SHIFT) +# define PIO_CFG0_PG2_INPUT (0 << PIO_CFG0_PG2_SHIFT) +# define PIO_CFG0_PG2_OUTPUT (1 << PIO_CFG0_PG2_SHIFT) +# define PIO_CFG0_PG2_TS1_SYNC (2 << PIO_CFG0_PG2_SHIFT) +# define PIO_CFG0_PG2_CSI1_HSYNC (3 << PIO_CFG0_PG2_SHIFT) +# define PIO_CFG0_PG2_SDC1_D0 (4 << PIO_CFG0_PG2_SHIFT) +#define PIO_CFG0_PG3_SHIFT (12) +#define PIO_CFG0_PG3_MASK (7 << PIO_CFG0_PG3_SHIFT) +# define PIO_CFG0_PG3_INPUT (0 << PIO_CFG0_PG3_SHIFT) +# define PIO_CFG0_PG3_OUTPUT (1 << PIO_CFG0_PG3_SHIFT) +# define PIO_CFG0_PG3_TS1_DVLD (2 << PIO_CFG0_PG3_SHIFT) +# define PIO_CFG0_PG3_CSI1_VSYNC (3 << PIO_CFG0_PG3_SHIFT) +# define PIO_CFG0_PG3_SDC1_D1 (4 << PIO_CFG0_PG3_SHIFT) +#define PIO_CFG0_PG4_SHIFT (16) +#define PIO_CFG0_PG4_MASK (7 << PIO_CFG0_PG4_SHIFT) +# define PIO_CFG0_PG4_INPUT (0 << PIO_CFG0_PG4_SHIFT) +# define PIO_CFG0_PG4_OUTPUT (1 << PIO_CFG0_PG4_SHIFT) +# define PIO_CFG0_PG4_TS1_D0 (2 << PIO_CFG0_PG4_SHIFT) +# define PIO_CFG0_PG4_CSI1_D0 (3 << PIO_CFG0_PG4_SHIFT) +# define PIO_CFG0_PG4_SDC1_D2 (4 << PIO_CFG0_PG4_SHIFT) +# define PIO_CFG0_PG4_CSI0_D8 (5 << PIO_CFG0_PG4_SHIFT) +#define PIO_CFG0_PG5_SHIFT (20) +#define PIO_CFG0_PG5_MASK (7 << PIO_CFG0_PG5_SHIFT) +# define PIO_CFG0_PG5_INPUT (0 << PIO_CFG0_PG5_SHIFT) +# define PIO_CFG0_PG5_OUTPUT (1 << PIO_CFG0_PG5_SHIFT) +# define PIO_CFG0_PG5_TS1_D1 (2 << PIO_CFG0_PG5_SHIFT) +# define PIO_CFG0_PG5_CSI1_D1 (3 << PIO_CFG0_PG5_SHIFT) +# define PIO_CFG0_PG5_SDC1_D3 (4 << PIO_CFG0_PG5_SHIFT) +# define PIO_CFG0_PG5_CSI0_D9 (5 << PIO_CFG0_PG5_SHIFT) +#define PIO_CFG0_PG6_SHIFT (24) +#define PIO_CFG0_PG6_MASK (7 << PIO_CFG0_PG6_SHIFT) +# define PIO_CFG0_PG6_INPUT (0 << PIO_CFG0_PG6_SHIFT) +# define PIO_CFG0_PG6_OUTPUT (1 << PIO_CFG0_PG6_SHIFT) +# define PIO_CFG0_PG6_TS1_D2 (2 << PIO_CFG0_PG6_SHIFT) +# define PIO_CFG0_PG6_CSI1_D2 (3 << PIO_CFG0_PG6_SHIFT) +# define PIO_CFG0_PG6_UART3_TX (4 << PIO_CFG0_PG6_SHIFT) +# define PIO_CFG0_PG6_CSI0_D10 (5 << PIO_CFG0_PG6_SHIFT) +#define PIO_CFG0_PG7_SHIFT (28) +#define PIO_CFG0_PG7_MASK (7 << PIO_CFG0_PG7_SHIFT) +# define PIO_CFG0_PG7_INPUT (0 << PIO_CFG0_PG7_SHIFT) +# define PIO_CFG0_PG7_OUTPUT (1 << PIO_CFG0_PG7_SHIFT) +# define PIO_CFG0_PG7_TS1_D3 (2 << PIO_CFG0_PG7_SHIFT) +# define PIO_CFG0_PG7_CSI1_D3 (3 << PIO_CFG0_PG7_SHIFT) +# define PIO_CFG0_PG7_UART3_RX (4 << PIO_CFG0_PG7_SHIFT) +# define PIO_CFG0_PG7_CSI0_D11 (5 << PIO_CFG0_PG7_SHIFT) + +/* Port G Configure Register 1 */ + +#define PIO_CFG1_PG8_SHIFT (0) +#define PIO_CFG1_PG8_MASK (7 << PIO_CFG1_PG8_SHIFT) +# define PIO_CFG1_PG8_INPUT (0 << PIO_CFG1_PG8_SHIFT) +# define PIO_CFG1_PG8_OUTPUT (1 << PIO_CFG1_PG8_SHIFT) +# define PIO_CFG1_PG8_TS1_D4 (2 << PIO_CFG1_PG8_SHIFT) +# define PIO_CFG1_PG8_CSI1_D4 (3 << PIO_CFG1_PG8_SHIFT) +# define PIO_CFG1_PG8_UART3_RTS (4 << PIO_CFG1_PG8_SHIFT) +# define PIO_CFG1_PG8_CSI0_D12 (5 << PIO_CFG1_PG8_SHIFT) +#define PIO_CFG1_PG9_SHIFT (4) +#define PIO_CFG1_PG9_MASK (7 << PIO_CFG1_PG9_SHIFT) +# define PIO_CFG1_PG9_INPUT (0 << PIO_CFG1_PG9_SHIFT) +# define PIO_CFG1_PG9_OUTPUT (1 << PIO_CFG1_PG9_SHIFT) +# define PIO_CFG1_PG9_TS1_D5 (2 << PIO_CFG1_PG9_SHIFT) +# define PIO_CFG1_PG9_CSI1_D5 (3 << PIO_CFG1_PG9_SHIFT) +# define PIO_CFG1_PG9_UART3_CTS (4 << PIO_CFG1_PG9_SHIFT) +# define PIO_CFG1_PG9_CSI0_D13 (5 << PIO_CFG1_PG9_SHIFT) +#define PIO_CFG1_PG10_SHIFT (8) +#define PIO_CFG1_PG10_MASK (3 << PIO_CFG1_PG10_SHIFT) +# define PIO_CFG1_PG10_INPUT (0 << PIO_CFG1_PG10_SHIFT) +# define PIO_CFG1_PG10_OUTPUT (1 << PIO_CFG1_PG10_SHIFT) +# define PIO_CFG1_PG10_TS1_D6 (2 << PIO_CFG1_PG10_SHIFT) +# define PIO_CFG1_PG10_CSI1_D6 (3 << PIO_CFG1_PG10_SHIFT) +# define PIO_CFG1_PG10_UART4_TX (4 << PIO_CFG1_PG10_SHIFT) +# define PIO_CFG1_PG10_CSI0_D14 (5 << PIO_CFG1_PG10_SHIFT) +#define PIO_CFG1_PG11_SHIFT (12) +#define PIO_CFG1_PG11_MASK (3 << PIO_CFG1_PG11_SHIFT) +# define PIO_CFG1_PG11_INPUT (0 << PIO_CFG1_PG11_SHIFT) +# define PIO_CFG1_PG11_OUTPUT (1 << PIO_CFG1_PG11_SHIFT) +# define PIO_CFG1_PG11_TS1_D7 (2 << PIO_CFG1_PG11_SHIFT) +# define PIO_CFG1_PG11_CSI1_D7 (3 << PIO_CFG1_PG11_SHIFT) +# define PIO_CFG1_PG11_UART4_RX (4 << PIO_CFG1_PG11_SHIFT) +# define PIO_CFG1_PG11_CSI0_D15 (5 << PIO_CFG1_PG11_SHIFT) + +/* Port G Configure Register 2-3 (not used) */ + +/* Port H Configure Register 0 */ + +#define PIO_CFG0_PH0_SHIFT (0) +#define PIO_CFG0_PH0_MASK (7 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_INPUT (0 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_OUTPUT (1 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_LCD1_D0 (2 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_ATAA0 (3 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_UART3_TX (4 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_EINT0 (6 << PIO_CFG0_PH0_SHIFT) +# define PIO_CFG0_PH0_CSI1_D0 (7 << PIO_CFG0_PH0_SHIFT) +#define PIO_CFG0_PH1_SHIFT (4) +#define PIO_CFG0_PH1_MASK (7 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_INPUT (0 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_OUTPUT (1 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_LCD1_D0 (2 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_ATAA1 (3 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_UART3_RX (4 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_EINT1 (6 << PIO_CFG0_PH1_SHIFT) +# define PIO_CFG0_PH1_CSI1_D1 (7 << PIO_CFG0_PH1_SHIFT) +#define PIO_CFG0_PH2_SHIFT (8) +#define PIO_CFG0_PH2_MASK (7 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_INPUT (0 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_OUTPUT (1 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_LCD1_D2 (2 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_ATAA2 (3 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_UART3_RTS (4 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_EINT2 (6 << PIO_CFG0_PH2_SHIFT) +# define PIO_CFG0_PH2_CSI1_D2 (7 << PIO_CFG0_PH2_SHIFT) +#define PIO_CFG0_PH3_SHIFT (12) +#define PIO_CFG0_PH3_MASK (7 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_INPUT (0 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_OUTPUT (1 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_LCD1_D3 (2 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_ATAIRQ (3 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_UART3_CTS (4 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_EINT3 (6 << PIO_CFG0_PH3_SHIFT) +# define PIO_CFG0_PH3_CSI1_D3 (7 << PIO_CFG0_PH3_SHIFT) +#define PIO_CFG0_PH4_SHIFT (16) +#define PIO_CFG0_PH4_MASK (7 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_INPUT (0 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_OUTPUT (1 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_LCD1_D4 (2 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_ATAD0 (3 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_UART4_TX (4 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_EINT4 (6 << PIO_CFG0_PH4_SHIFT) +# define PIO_CFG0_PH4_CSI1_D4 (7 << PIO_CFG0_PH4_SHIFT) +#define PIO_CFG0_PH5_SHIFT (20) +#define PIO_CFG0_PH5_MASK (7 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_INPUT (0 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_OUTPUT (1 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_LCD1_D5 (2 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_ATAD1 (3 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_UART4_RX (4 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_EINT5 (6 << PIO_CFG0_PH5_SHIFT) +# define PIO_CFG0_PH5_CSI1_D5 (7 << PIO_CFG0_PH5_SHIFT) +#define PIO_CFG0_PH6_SHIFT (24) +#define PIO_CFG0_PH6_MASK (7 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_INPUT (0 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_OUTPUT (1 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_LCD1_D6 (2 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_ATAD2 (3 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_UART5_TX (4 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_MS_BS (5 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_EINT6 (6 << PIO_CFG0_PH6_SHIFT) +# define PIO_CFG0_PH6_CSI1_D6 (7 << PIO_CFG0_PH6_SHIFT) +#define PIO_CFG0_PH7_SHIFT (28) +#define PIO_CFG0_PH7_MASK (7 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_INPUT (0 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_OUTPUT (1 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_LCD1_D7 (2 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_ATAD3 (3 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_UART5_RX (4 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_MS_CLK (5 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_EINT7 (6 << PIO_CFG0_PH7_SHIFT) +# define PIO_CFG0_PH7_CSI1_D7 (7 << PIO_CFG0_PH7_SHIFT) + +/* Port H Configure Register 1 */ + +#define PIO_CFG1_PH8_SHIFT (0) +#define PIO_CFG1_PH8_MASK (7 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_INPUT (0 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_OUTPUT (1 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_LCD1_D8 (2 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_ATAD4 (3 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_KP_IN0 (4 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_MS_D0 (5 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_EINT8 (6 << PIO_CFG1_PH8_SHIFT) +# define PIO_CFG1_PH8_CSI1_D8 (7 << PIO_CFG1_PH8_SHIFT) +#define PIO_CFG1_PH9_SHIFT (4) +#define PIO_CFG1_PH9_MASK (7 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_INPUT (0 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_OUTPUT (1 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_LCD1_D9 (2 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_ATAD5 (3 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_KP_IN1 (4 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_MS_D1 (5 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_EINT9 (6 << PIO_CFG1_PH9_SHIFT) +# define PIO_CFG1_PH9_CSI1_D9 (7 << PIO_CFG1_PH9_SHIFT) +#define PIO_CFG1_PH10_SHIFT (8) +#define PIO_CFG1_PH10_MASK (3 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_INPUT (0 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_OUTPUT (1 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_LCD1_D10 (2 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_ATAD6 (3 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_KP_IN2 (4 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_MS_D2 (5 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_EINT10 (6 << PIO_CFG1_PH10_SHIFT) +# define PIO_CFG1_PH10_CSI1_D10 (7 << PIO_CFG1_PH10_SHIFT) +#define PIO_CFG1_PH11_SHIFT (12) +#define PIO_CFG1_PH11_MASK (3 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_INPUT (0 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_OUTPUT (1 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_LCD1_D11 (2 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_ATAD7 (3 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_KP_IN3 (4 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_MS_D3 (5 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_EINT11 (6 << PIO_CFG1_PH11_SHIFT) +# define PIO_CFG1_PH11_CSI1_D11 (7 << PIO_CFG1_PH11_SHIFT) +#define PIO_CFG1_PH12_SHIFT (16) +#define PIO_CFG1_PH12_MASK (3 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_INPUT (0 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_OUTPUT (1 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_LCD1_D12 (2 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_ATAD8 (3 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_PS2_SCK1 (4 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_EINT12 (6 << PIO_CFG1_PH12_SHIFT) +# define PIO_CFG1_PH12_CSI1_D12 (7 << PIO_CFG1_PH12_SHIFT) +#define PIO_CFG1_PH13_SHIFT (20) +#define PIO_CFG1_PH13_MASK (3 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_INPUT (0 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_OUTPUT (1 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_LCD1_D13 (2 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_ATAD9 (3 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_PS2_SDA1 (4 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_SMC_RST (5 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_EINT13 (6 << PIO_CFG1_PH13_SHIFT) +# define PIO_CFG1_PH13_CSI1_D13 (7 << PIO_CFG1_PH13_SHIFT) +#define PIO_CFG1_PH14_SHIFT (24) +#define PIO_CFG1_PH14_MASK (3 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_INPUT (0 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_OUTPUT (1 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_LCD1_D14 (2 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_ATAD10 (3 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_KP_IN4 (4 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_SMC_VPPEN (5 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_EINT14 (6 << PIO_CFG1_PH14_SHIFT) +# define PIO_CFG1_PH14_CSI1_D14 (7 << PIO_CFG1_PH14_SHIFT) +#define PIO_CFG1_PH15_SHIFT (28) +#define PIO_CFG1_PH15_MASK (3 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_INPUT (0 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_OUTPUT (1 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_LCD1_D15 (2 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_ATAD11 (3 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_KP_IN5 (4 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_SMC_VPPPP (5 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_EINT15 (6 << PIO_CFG1_PH15_SHIFT) +# define PIO_CFG1_PH15_CSI1_D15 (7 << PIO_CFG1_PH15_SHIFT) + +/* Port H Configure Register 2 */ + +#define PIO_CFG2_PH16_SHIFT (0) +#define PIO_CFG2_PH16_MASK (7 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_INPUT (0 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_OUTPUT (1 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_LCD1_D16 (2 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_ATAD12 (3 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_KP_IN6 (4 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_EINT16 (6 << PIO_CFG2_PH16_SHIFT) +# define PIO_CFG2_PH16_CSI1_D16 (7 << PIO_CFG2_PH16_SHIFT) +#define PIO_CFG2_PH17_SHIFT (4) +#define PIO_CFG2_PH17_MASK (7 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_INPUT (0 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_OUTPUT (1 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_LCD1_D17 (2 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_ATAD13 (3 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_KP_IN7 (4 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_SMC_VCCEN (5 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_EINT17 (6 << PIO_CFG2_PH17_SHIFT) +# define PIO_CFG2_PH17_CSI1_D17 (7 << PIO_CFG2_PH17_SHIFT) +#define PIO_CFG2_PH18_SHIFT (8) +#define PIO_CFG2_PH18_MASK (7 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_INPUT (0 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_OUTPUT (1 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_LCD1_D18 (2 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_ATAD14 (3 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_KP_OUT0 (4 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_SMC_SCK (5 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_EINT18 (6 << PIO_CFG2_PH18_SHIFT) +# define PIO_CFG2_PH18_CSI1_D18 (7 << PIO_CFG2_PH18_SHIFT) +#define PIO_CFG2_PH19_SHIFT (12) +#define PIO_CFG2_PH19_MASK (7 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_INPUT (0 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_OUTPUT (1 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_LCD1_D19 (2 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_ATAD15 (3 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_KP_OUT1 (4 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_SMC_SDA (5 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_EINT19 (6 << PIO_CFG2_PH19_SHIFT) +# define PIO_CFG2_PH19_CSI1_D19 (7 << PIO_CFG2_PH19_SHIFT) +#define PIO_CFG2_PH20_SHIFT (16) +#define PIO_CFG2_PH20_MASK (7 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_INPUT (0 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_OUTPUT (1 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_LCD1_D20 (2 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_ATAOE (3 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_CAN_TX (4 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_EINT20 (6 << PIO_CFG2_PH20_SHIFT) +# define PIO_CFG2_PH20_CSI1_D20 (7 << PIO_CFG2_PH20_SHIFT) +#define PIO_CFG2_PH21_SHIFT (20) +#define PIO_CFG2_PH21_MASK (7 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_INPUT (0 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_OUTPUT (1 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_LCD1_D21 (2 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_ATADREQ (3 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_CAN_RX (4 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_EINT21 (6 << PIO_CFG2_PH21_SHIFT) +# define PIO_CFG2_PH21_CSI1_D21 (7 << PIO_CFG2_PH21_SHIFT) +#define PIO_CFG2_PH22_SHIFT (24) +#define PIO_CFG2_PH22_MASK (7 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_INPUT (0 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_OUTPUT (1 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_LCD1_D22 (2 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_ATADACK (3 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_KP_OUT2 (4 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_SDC1_CMD (5 << PIO_CFG2_PH22_SHIFT) +# define PIO_CFG2_PH22_CSI1_D22 (7 << PIO_CFG2_PH22_SHIFT) +#define PIO_CFG2_PH23_SHIFT (28) +#define PIO_CFG2_PH23_MASK (7 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_INPUT (0 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_OUTPUT (1 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_LCD1_D23 (2 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_ATACS0 (3 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_KP_OUT3 (4 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_SDC1_CLK (5 << PIO_CFG2_PH23_SHIFT) +# define PIO_CFG2_PH23_CSI1_D23 (7 << PIO_CFG2_PH23_SHIFT) + +/* Port H Configure Register 3 */ + +#define PIO_CFG2_PH24_SHIFT (0) +#define PIO_CFG2_PH24_MASK (7 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_INPUT (0 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_OUTPUT (1 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_LCD1_CLK (2 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_ATACS1 (3 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_KP_OUT4 (4 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_SDC1_D0 (5 << PIO_CFG2_PH24_SHIFT) +# define PIO_CFG2_PH24_CSI1_PCLK (7 << PIO_CFG2_PH24_SHIFT) +#define PIO_CFG2_PH25_SHIFT (4) +#define PIO_CFG2_PH25_MASK (7 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_INPUT (0 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_OUTPUT (1 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_LCD1_DE (2 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_ATAIORDY (3 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_KP_OUT5 (4 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_SDC1_D1 (5 << PIO_CFG2_PH25_SHIFT) +# define PIO_CFG2_PH25_CSI1_FIELD (7 << PIO_CFG2_PH25_SHIFT) +#define PIO_CFG2_PH26_SHIFT (8) +#define PIO_CFG2_PH26_MASK (7 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_INPUT (0 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_OUTPUT (1 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_LCD1_HSYNC (2 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_ATAIOR (3 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_KP_OUT6 (4 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_SDC1_D2 (5 << PIO_CFG2_PH26_SHIFT) +# define PIO_CFG2_PH26_CSI1_HSYNC (7 << PIO_CFG2_PH26_SHIFT) +#define PIO_CFG2_PH27_SHIFT (12) +#define PIO_CFG2_PH27_MASK (7 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_INPUT (0 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_OUTPUT (1 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_LCD1_VSYNC (2 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_ATAIOW (3 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_KP_OUT7 (4 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_SDC1_D3 (5 << PIO_CFG2_PH27_SHIFT) +# define PIO_CFG2_PH27_CSI1_VSYNC (7 << PIO_CFG2_PH27_SHIFT) + +/* Port I Configure Register 0 */ + +#define PIO_CFG0_PI0_SHIFT (0) +#define PIO_CFG0_PI0_MASK (7 << PIO_CFG0_PI0_SHIFT) +# define PIO_CFG0_PI0_INPUT (0 << PIO_CFG0_PI0_SHIFT) +# define PIO_CFG0_PI0_OUTPUT (1 << PIO_CFG0_PI0_SHIFT) +#define PIO_CFG0_PI1_SHIFT (4) +#define PIO_CFG0_PI1_MASK (7 << PIO_CFG0_PI1_SHIFT) +# define PIO_CFG0_PI1_INPUT (0 << PIO_CFG0_PI1_SHIFT) +# define PIO_CFG0_PI1_OUTPUT (1 << PIO_CFG0_PI1_SHIFT) +#define PIO_CFG0_PI2_SHIFT (8) +#define PIO_CFG0_PI2_MASK (7 << PIO_CFG0_PI2_SHIFT) +# define PIO_CFG0_PI2_INPUT (0 << PIO_CFG0_PI2_SHIFT) +# define PIO_CFG0_PI2_OUTPUT (1 << PIO_CFG0_PI2_SHIFT) +#define PIO_CFG0_PI3_SHIFT (12) +#define PIO_CFG0_PI3_MASK (7 << PIO_CFG0_PI3_SHIFT) +# define PIO_CFG0_PI3_INPUT (0 << PIO_CFG0_PI3_SHIFT) +# define PIO_CFG0_PI3_OUTPUT (1 << PIO_CFG0_PI3_SHIFT) +# define PIO_CFG0_PI3_PWM1 (2 << PIO_CFG0_PI3_SHIFT) +#define PIO_CFG0_PI4_SHIFT (16) +#define PIO_CFG0_PI4_MASK (7 << PIO_CFG0_PI4_SHIFT) +# define PIO_CFG0_PI4_INPUT (0 << PIO_CFG0_PI4_SHIFT) +# define PIO_CFG0_PI4_OUTPUT (1 << PIO_CFG0_PI4_SHIFT) +# define PIO_CFG0_PI4_SDC3_CMD (2 << PIO_CFG0_PI4_SHIFT) +#define PIO_CFG0_PI5_SHIFT (20) +#define PIO_CFG0_PI5_MASK (7 << PIO_CFG0_PI5_SHIFT) +# define PIO_CFG0_PI5_INPUT (0 << PIO_CFG0_PI5_SHIFT) +# define PIO_CFG0_PI5_OUTPUT (1 << PIO_CFG0_PI5_SHIFT) +# define PIO_CFG0_PI5_SDC3_CLK (2 << PIO_CFG0_PI5_SHIFT) +#define PIO_CFG0_PI6_SHIFT (24) +#define PIO_CFG0_PI6_MASK (7 << PIO_CFG0_PI6_SHIFT) +# define PIO_CFG0_PI6_INPUT (0 << PIO_CFG0_PI6_SHIFT) +# define PIO_CFG0_PI6_OUTPUT (1 << PIO_CFG0_PI6_SHIFT) +# define PIO_CFG0_PI6_SDC3_D0 (2 << PIO_CFG0_PI6_SHIFT) +#define PIO_CFG0_PI7_SHIFT (28) +#define PIO_CFG0_PI7_MASK (7 << PIO_CFG0_PI7_SHIFT) +# define PIO_CFG0_PI7_INPUT (0 << PIO_CFG0_PI7_SHIFT) +# define PIO_CFG0_PI7_OUTPUT (1 << PIO_CFG0_PI7_SHIFT) +# define PIO_CFG0_PI7_SDC3_D1 (2 << PIO_CFG0_PI7_SHIFT) + +/* Port I Configure Register 1 */ + +#define PIO_CFG1_PI8_SHIFT (0) +#define PIO_CFG1_PI8_MASK (7 << PIO_CFG1_PI8_SHIFT) +# define PIO_CFG1_PI8_INPUT (0 << PIO_CFG1_PI8_SHIFT) +# define PIO_CFG1_PI8_OUTPUT (1 << PIO_CFG1_PI8_SHIFT) +# define PIO_CFG1_PI8_SDC3_D2 (2 << PIO_CFG1_PI8_SHIFT) +#define PIO_CFG1_PI9_SHIFT (4) +#define PIO_CFG1_PI9_MASK (7 << PIO_CFG1_PI9_SHIFT) +# define PIO_CFG1_PI9_INPUT (0 << PIO_CFG1_PI9_SHIFT) +# define PIO_CFG1_PI9_OUTPUT (1 << PIO_CFG1_PI9_SHIFT) +# define PIO_CFG1_PI9_SDC3_D3 (2 << PIO_CFG1_PI9_SHIFT) +#define PIO_CFG1_PI10_SHIFT (8) +#define PIO_CFG1_PI10_MASK (3 << PIO_CFG1_PI10_SHIFT) +# define PIO_CFG1_PI10_INPUT (0 << PIO_CFG1_PI10_SHIFT) +# define PIO_CFG1_PI10_OUTPUT (1 << PIO_CFG1_PI10_SHIFT) +# define PIO_CFG1_PI10_SPI0_CS0 (2 << PIO_CFG1_PI10_SHIFT) +# define PIO_CFG1_PI10_UART5_TX (3 << PIO_CFG1_PI10_SHIFT) +# define PIO_CFG1_PI10_EINT22 (6 << PIO_CFG1_PI10_SHIFT) +#define PIO_CFG1_PI11_SHIFT (12) +#define PIO_CFG1_PI11_MASK (3 << PIO_CFG1_PI11_SHIFT) +# define PIO_CFG1_PI11_INPUT (0 << PIO_CFG1_PI11_SHIFT) +# define PIO_CFG1_PI11_OUTPUT (1 << PIO_CFG1_PI11_SHIFT) +# define PIO_CFG1_PI11_SPI0_CLK (2 << PIO_CFG1_PI11_SHIFT) +# define PIO_CFG1_PI11_UART5_RX (3 << PIO_CFG1_PI11_SHIFT) +# define PIO_CFG1_PI11_EINT23 (6 << PIO_CFG1_PI11_SHIFT) +#define PIO_CFG1_PI12_SHIFT (16) +#define PIO_CFG1_PI12_MASK (3 << PIO_CFG1_PI12_SHIFT) +# define PIO_CFG1_PI12_INPUT (0 << PIO_CFG1_PI12_SHIFT) +# define PIO_CFG1_PI12_OUTPUT (1 << PIO_CFG1_PI12_SHIFT) +# define PIO_CFG1_PI12_SPI0_MOSI (2 << PIO_CFG1_PI12_SHIFT) +# define PIO_CFG1_PI12_UART6_TX (3 << PIO_CFG1_PI12_SHIFT) +# define PIO_CFG1_PI12_EINT24 (6 << PIO_CFG1_PI12_SHIFT) +#define PIO_CFG1_PI13_SHIFT (20) +#define PIO_CFG1_PI13_MASK (3 << PIO_CFG1_PI13_SHIFT) +# define PIO_CFG1_PI13_INPUT (0 << PIO_CFG1_PI13_SHIFT) +# define PIO_CFG1_PI13_OUTPUT (1 << PIO_CFG1_PI13_SHIFT) +# define PIO_CFG1_PI13_SPI0_MISO (2 << PIO_CFG1_PI13_SHIFT) +# define PIO_CFG1_PI13_UART6_RX (3 << PIO_CFG1_PI13_SHIFT) +# define PIO_CFG1_PI13_EINT25 (6 << PIO_CFG1_PI13_SHIFT) +#define PIO_CFG1_PI14_SHIFT (24) +#define PIO_CFG1_PI14_MASK (3 << PIO_CFG1_PI14_SHIFT) +# define PIO_CFG1_PI14_INPUT (0 << PIO_CFG1_PI14_SHIFT) +# define PIO_CFG1_PI14_OUTPUT (1 << PIO_CFG1_PI14_SHIFT) +# define PIO_CFG1_PI14_SPI0_CS1 (2 << PIO_CFG1_PI14_SHIFT) +# define PIO_CFG1_PI14_PS2_SCK1 (3 << PIO_CFG1_PI14_SHIFT) +# define PIO_CFG1_PI14_TCLKIN0 (4 << PIO_CFG1_PI14_SHIFT) +# define PIO_CFG1_PI14_EINT26 (6 << PIO_CFG1_PI14_SHIFT) +#define PIO_CFG1_PI15_SHIFT (28) +#define PIO_CFG1_PI15_MASK (3 << PIO_CFG1_PI15_SHIFT) +# define PIO_CFG1_PI15_INPUT (0 << PIO_CFG1_PI15_SHIFT) +# define PIO_CFG1_PI15_OUTPUT (1 << PIO_CFG1_PI15_SHIFT) +# define PIO_CFG1_PI15_SPI1_CS1 (2 << PIO_CFG1_PI15_SHIFT) +# define PIO_CFG1_PI15_PS2_SDA1 (3 << PIO_CFG1_PI15_SHIFT) +# define PIO_CFG1_PI15_TCLKIN1 (4 << PIO_CFG1_PI15_SHIFT) +# define PIO_CFG1_PI15_EINT27 (6 << PIO_CFG1_PI15_SHIFT) + +/* Port I Configure Register 2 */ + +#define PIO_CFG2_PI16_SHIFT (0) +#define PIO_CFG2_PI16_MASK (7 << PIO_CFG2_PI16_SHIFT) +# define PIO_CFG2_PI16_INPUT (0 << PIO_CFG2_PI16_SHIFT) +# define PIO_CFG2_PI16_OUTPUT (1 << PIO_CFG2_PI16_SHIFT) +# define PIO_CFG2_PI16_SPI1_CS0 (2 << PIO_CFG2_PI16_SHIFT) +# define PIO_CFG2_PI16_UART2_RTS (3 << PIO_CFG2_PI16_SHIFT) +# define PIO_CFG2_PI16_EINT28 (6 << PIO_CFG2_PI16_SHIFT) +#define PIO_CFG2_PI17_SHIFT (4) +#define PIO_CFG2_PI17_MASK (7 << PIO_CFG2_PI17_SHIFT) +# define PIO_CFG2_PI17_INPUT (0 << PIO_CFG2_PI17_SHIFT) +# define PIO_CFG2_PI17_OUTPUT (1 << PIO_CFG2_PI17_SHIFT) +# define PIO_CFG2_PI17_SPI1_CLK (2 << PIO_CFG2_PI17_SHIFT) +# define PIO_CFG2_PI17_UART2_CTS (3 << PIO_CFG2_PI17_SHIFT) +# define PIO_CFG2_PI17_EINT29 (6 << PIO_CFG2_PI17_SHIFT) +#define PIO_CFG2_PI18_SHIFT (8) +#define PIO_CFG2_PI18_MASK (7 << PIO_CFG2_PI18_SHIFT) +# define PIO_CFG2_PI18_INPUT (0 << PIO_CFG2_PI18_SHIFT) +# define PIO_CFG2_PI18_OUTPUT (1 << PIO_CFG2_PI18_SHIFT) +# define PIO_CFG2_PI18_SPI1_MOSI (2 << PIO_CFG2_PI18_SHIFT) +# define PIO_CFG2_PI18_UART2_TX (3 << PIO_CFG2_PI18_SHIFT) +# define PIO_CFG2_PI18_EINT30 (6 << PIO_CFG2_PI18_SHIFT) +#define PIO_CFG2_PI19_SHIFT (12) +#define PIO_CFG2_PI19_MASK (7 << PIO_CFG2_PI19_SHIFT) +# define PIO_CFG2_PI19_INPUT (0 << PIO_CFG2_PI19_SHIFT) +# define PIO_CFG2_PI19_OUTPUT (1 << PIO_CFG2_PI19_SHIFT) +# define PIO_CFG2_PI19_SPI1_MISO (2 << PIO_CFG2_PI19_SHIFT) +# define PIO_CFG2_PI19_UART2_RX (3 << PIO_CFG2_PI19_SHIFT) +# define PIO_CFG2_PI19_EINT31 (6 << PIO_CFG2_PI19_SHIFT) +#define PIO_CFG2_PI20_SHIFT (16) +#define PIO_CFG2_PI20_MASK (7 << PIO_CFG2_PI20_SHIFT) +# define PIO_CFG2_PI20_INPUT (0 << PIO_CFG2_PI20_SHIFT) +# define PIO_CFG2_PI20_OUTPUT (1 << PIO_CFG2_PI20_SHIFT) +# define PIO_CFG2_PI20_PS2_SCK (2 << PIO_CFG2_PI20_SHIFT) +# define PIO_CFG2_PI20_UART7_TX (3 << PIO_CFG2_PI20_SHIFT) +# define PIO_CFG2_PI20_HSCL (4 << PIO_CFG2_PI20_SHIFT) +#define PIO_CFG2_PI21_SHIFT (20) +#define PIO_CFG2_PI21_MASK (7 << PIO_CFG2_PI21_SHIFT) +# define PIO_CFG2_PI21_INPUT (0 << PIO_CFG2_PI21_SHIFT) +# define PIO_CFG2_PI21_OUTPUT (1 << PIO_CFG2_PI21_SHIFT) +# define PIO_CFG2_PI21_PS2_SDA0 (2 << PIO_CFG2_PI21_SHIFT) +# define PIO_CFG2_PI21_UART7_RX (3 << PIO_CFG2_PI21_SHIFT) +# define PIO_CFG2_PI21_HSDA (4 << PIO_CFG2_PI21_SHIFT) + +/* Port I Configure Register 3 (not used) */ + +#endif /* __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H */ diff --git a/arch/arm/src/a1x/chip/a1x_pio.h b/arch/arm/src/a1x/chip/a1x_pio.h new file mode 100644 index 00000000000..e1c2f3640b2 --- /dev/null +++ b/arch/arm/src/a1x/chip/a1x_pio.h @@ -0,0 +1,228 @@ +/************************************************************************************ + * arch/arm/src/a1x/chip/a1x_pio.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H +#define __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/a1x_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define PIO_PORTA 0 +#define PIO_PORTB 1 +#define PIO_PORTC 2 +#define PIO_PORTD 3 +#define PIO_PORTE 4 +#define PIO_PORTF 5 +#define PIO_PORTG 6 +#define PIO_PORTH 7 +#define PIO_PORTI 8 +#define PIO_PORTS 9 + +#define PIO_CFG_INPUT 0 +#define PIO_CFG_OUTPUT 1 + +#define PIO_DRV_LEVEL0 0 +#define PIO_DRV_LEVEL1 1 +#define PIO_DRV_LEVEL2 2 +#define PIO_DRV_LEVEL3 3 + +#define PIO_PULL_NONE 0 +#define PIO_PULL_UP 1 +#define PIO_PULL_DOWN 2 + +#define PIO_INT_POSEDGE 0 +#define PIO_INT_NEGEDGE 1 +#define PIO_INT_HILEVEL 2 +#define PIO_INT_LOWLEVEL 3 +#define PIO_INT_BOTHEDGES 4 + +/* Register offsets *****************************************************************/ + +#define A1X_PIO_CFG0_OFFSET(n) (0x0000 + (n)*0x24) /* Port Configure Register 0, n=0-9 */ +#define A1X_PIO_CFG1_OFFSET(n) (0x0004 + (n)*0x24) /* Port Configure Register 1, n=0-9 */ +#define A1X_PIO_CFG2_OFFSET(n) (0x0008 + (n)*0x24) /* Port Configure Register 2, n=0-9 */ +#define A1X_PIO_CFG3_OFFSET(n) (0x000c + (n)*0x24) /* Port Configure Register 3, n=0-9 */ +#define A1X_PIO_DAT_OFFSET(n) (0x0010 + (n)*0x24) /* Port Data Register, n=0-9 */ +#define A1X_PIO_DRV0_OFFSET(n) (0x0014 + (n)*0x24) /* Port Multi-Driving Register 0, n=0-9 */ +#define A1X_PIO_DRV1_OFFSET(n) (0x0018 + (n)*0x24) /* Port Multi-Driving Register 1, n=0-9 */ +#define A1X_PIO_PUL0_OFFSET(n) (0x001c + (n)*0x24) /* Port Pull Register 0, n=0-9 */ +#define A1X_PIO_PUL1_OFFSET(n) (0x0020 + (n)*0x24) /* Port Pull Register 1, n=0-9 */ +#define A1X_PIO_INT_CFG0_OFFSET 0x0200 /* PIO Interrupt Configure Register 0 */ +#define A1X_PIO_INT_CFG1_OFFSET 0x0204 /* PIO Interrupt Configure Register 1 */ +#define A1X_PIO_INT_CFG2_OFFSET 0x0208 /* PIO Interrupt Configure Register 2 */ +#define A1X_PIO_INT_CFG3_OFFSET 0x020c /* PIO Interrupt Configure Register 3 */ +#define A1X_PIO_INT_CTL_OFFSET 0x0210 /* PIO Interrupt Control Register */ +#define A1X_PIO_INT_STA_OFFSET 0x0214 /* PIO Interrupt Status Register */ +#define A1X_PIO_INT_DEB_OFFSET 0x0218 /* PIO Interrupt Debounce Register */ +#define A1X_SDR_PAD_DRV_OFFSET 0x0220 /* SDRAM Pad Multi-Driving Register */ +#define A1X_SDR_PAD_PUL_OFFSET 0x0224 /* SDRAM Pad Pull Register */ + +/* Register virtual addresses *******************************************************/ + +#define A1X_PIO_CFG0(n) (A1X_PIO_VADDR+A1X_PIO_CFG0_OFFSET(n)) +#define A1X_PIO_CFG1(n) (A1X_PIO_VADDR+A1X_PIO_CFG1_OFFSET(n)) +#define A1X_PIO_CFG2(n) (A1X_PIO_VADDR+A1X_PIO_CFG2_OFFSET(n)) +#define A1X_PIO_CFG3(n) (A1X_PIO_VADDR+A1X_PIO_CFG3_OFFSET(n)) +#define A1X_PIO_DAT(n) (A1X_PIO_VADDR+A1X_PIO_DAT_OFFSET(n)) +#define A1X_PIO_DRV0(n) (A1X_PIO_VADDR+A1X_PIO_DRV0_OFFSET(n)) +#define A1X_PIO_DRV1(n) (A1X_PIO_VADDR+A1X_PIO_DRV1_OFFSET(n)) +#define A1X_PIO_PUL0(n) (A1X_PIO_VADDR+A1X_PIO_PUL0_OFFSET(n)) +#define A1X_PIO_PUL1(n) (A1X_PIO_VADDR+A1X_PIO_PUL1_OFFSET(n)) +#define A1X_PIO_INT_CFG0 (A1X_PIO_VADDR+A1X_PIO_INT_CFG0_OFFSET) +#define A1X_PIO_INT_CFG1 (A1X_PIO_VADDR+A1X_PIO_INT_CFG1_OFFSET) +#define A1X_PIO_INT_CFG2 (A1X_PIO_VADDR+A1X_PIO_INT_CFG2_OFFSET) +#define A1X_PIO_INT_CFG3 (A1X_PIO_VADDR+A1X_PIO_INT_CFG3_OFFSET) +#define A1X_PIO_INT_CTL (A1X_PIO_VADDR+A1X_PIO_INT_CTL_OFFSET) +#define A1X_PIO_INT_STA (A1X_PIO_VADDR+A1X_PIO_INT_STA_OFFSET) +#define A1X_PIO_INT_DEB (A1X_PIO_VADDR+A1X_PIO_INT_DEB_OFFSET) +#define A1X_SDR_PAD_DRV (A1X_PIO_VADDR+A1X_SDR_PAD_DRV_OFFSET) +#define A1X_SDR_PAD_PUL (A1X_PIO_VADDR+A1X_SDR_PAD_PUL_OFFSET) + +/* Register bit field definitions ***************************************************/ + +/* Port Configure Register 0, n=0-7 */ + +#define PIO_CFG0_SHIFT(n) ((n) << 2) +#define PIO_CFG0_MASK(n)) (7 << PIO_CFG0_SHIFT(n)) +# define PIO_CFG0(m,v) ((uint32_t)(v) << PIO_CFG0_SHIFT(n)) + +/* Port Configure Register 1, n=8-15 */ + +#define PIO_CFG1_SHIFT(n) (((n) - 8) << 2) +#define PIO_CFG1_MASK(n)) (7 << PIO_CFG1_SHIFT(n)) +# define PIO_CFG1(m,v) ((uint32_t)(v) << PIO_CFG1_SHIFT(n)) + +/* Port Configure Register 2, n=16-23 */ + +#define PIO_CFG2_SHIFT(n) (((n) - 16) << 2) +#define PIO_CFG2_MASK(n)) (7 << PIO_CFG2_SHIFT(n)) +# define PIO_CFG2(m,v) ((uint32_t)(v) << PIO_CFG2_SHIFT(n)) + +/* Port Configure Register 3, n=24-31 */ + +#define PIO_CFG3_SHIFT(n) (((n) - 24) << 2) +#define PIO_CFG3_MASK(n)) (7 << PIO_CFG3_SHIFT(n)) +# define PIO_CFG3(m,v) ((uint32_t)(v) << PIO_CFG3_SHIFT(n)) + +/* Then bring-in CPU-specific PIO CFG register definitions */ + +#if defined(CONFIG_ARCH_CHIP_A10) +# include "chip/a10_piocfg.h" +#else +# error Unrecognized A1X architecture +#endif + +/* Port n Data Register, n=0-9 */ + +#define PIO_DAT(n) (1 << (n)) /* PA data, n=0-31 */ + +/* Port n Multi-Driving Register 0, n=0-9 */ + +#define PIO_DRV0_SHIFT(n) ((n) << 1) /* PA DRV0, n=0-15 */ +#define PIO_DRV0_MASK(n) (3 << PIO_DRV0_SHIFT(n)) +# define PIO_DRV0_MASK(n,v) ((uint32_t)(v) << PIO_DRV0_SHIFT(n)) + +/* Port n Multi-Driving Register 1, n=0-9 */ + +#define PIO_DRV1_SHIFT(n) (((n) - 16) << 1) /* PA DRV1, n=16-31 */ +#define PIO_DRV1_MASK(n) (3 << PIO_DRV1_SHIFT(n)) +# define PIO_DRV1_MASK(n,v) ((uint32_t)(v) << PIO_DRV1_SHIFT(n)) + +/* Port n Pull Register 0, n=0-9 */ + +#define PIO_PUL0_SHIFT(n) ((n) << 1) /* PA PUL0, n=0-15 */ +#define PIO_PUL0_MASK(n) (3 << PIO_PUL0_SHIFT(n)) +# define PIO_PUL0_MASK(n,v) ((uint32_t)(v) << PIO_PUL0_SHIFT(n)) + +/* Port n Pull Register 1, n=0-9 */ + +#define PIO_PUL1_SHIFT(n) (((n) - 16) << 1) /* PA PUL1, n=16-31 */ +#define PIO_PUL1_MASK(n) (3 << PIO_PUL1_SHIFT(n)) +# define PIO_PUL1_MASK(n,v) ((uint32_t)(v) << PIO_PUL1_SHIFT(n)) + +/* PIO Interrupt Configure Register 0 */ + +#define PIO_INT_CFG0_SHIFT(n) ((n) << 2) +#define PIO_INT_CFG0_MASK(n)) (15 << PIO_INT_CFG0_SHIFT(n)) +# define PIO_INT_CFG0(m,v) ((uint32_t)(v) << PIO_INT_CFG0_SHIFT(n)) + +/* PIO Interrupt Configure Register 1 */ + +#define PIO_INT_CFG1_SHIFT(n) (((n) - 8) << 2) +#define PIO_INT_CFG1_MASK(n)) (15 << PIO_INT_CFG1_SHIFT(n)) +# define PIO_INT_CFG1(m,v) ((uint32_t)(v) << PIO_INT_CFG1_SHIFT(n)) + +/* PIO Interrupt Configure Register 2 */ + +#define PIO_INT_CFG2_SHIFT(n) (((n) - 16) << 2) +#define PIO_INT_CFG2_MASK(n)) (15 << PIO_INT_CFG2_SHIFT(n)) +# define PIO_INT_CFG2(m,v) ((uint32_t)(v) << PIO_INT_CFG2_SHIFT(n)) + +/* PIO Interrupt Configure Register 3 */ + +#define PIO_INT_CFG3_SHIFT(n) (((n) - 24) << 2) +#define PIO_INT_CFG3_MASK(n)) (15 << PIO_INT_CFG3_SHIFT(n)) +# define PIO_INT_CFG3(m,v) ((uint32_t)(v) << PIO_INT_CFG3_SHIFT(n)) + +/* PIO Interrupt Control Register */ + +#define PIO_INT_CTL(n) (1 << (n)) + +/* PIO Interrupt Status Register */ + +#define PIO_INT_STA(n) (1 << (n)) + +/* PIO Interrupt Debounce Register */ + +#define PIO_INT_DEB_CLKSEL (1 << 0) /* Bit 0: PIO Interrupt Clock Select */ +#define PIO_INT_DEB_CLKPRESC_SHIFT (4) /* Bit 4-6: Debounce Clock Pre-scale */ +#define PIO_INT_DEB_CLKPRESC_MASK (7 << PIO_INT_DEB_CLKPRESC_SHIFT) +# define PIO_INT_DEB_CLKPRESC(n) ((uint32_t)(n) << PIO_INT_DEB_CLKPRESC_SHIFT) + +/* SDRAM Pad Multi-Driving Register */ +/* REVISIT: Missing register bit definitions */ + +/* SDRAM Pad Pull Register */ +/* REVISIT: Missing register bit definitions */ + +#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H */ diff --git a/configs/sama5d3x-ek/src/sam_ov2640.c b/configs/sama5d3x-ek/src/sam_ov2640.c index 8d7b70bcc60..4ed787c5dd1 100644 --- a/configs/sama5d3x-ek/src/sam_ov2640.c +++ b/configs/sama5d3x-ek/src/sam_ov2640.c @@ -250,6 +250,10 @@ int ov2640_main(int argc, char *argv[]) return EXIT_FAILURE; } + /* Now if everything is set up properly, the camera output should be + * visible on the LCD. + */ + return EXIT_SUCCESS; }