diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index ad3346bd694..0dac1ddbfbc 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -65,6 +65,10 @@ config PIC32MZ_I2C bool default n +config PIC32MZ_TIMER + bool + default n + config PIC32MZ_T1 bool default y @@ -78,34 +82,42 @@ config PIC32MZ_WDT config PIC32MZ_T2 bool "Timer 2 (T2)" default n + select PIC32MZ_TIMER config PIC32MZ_T3 bool "Timer 3 (T3)" default n + select PIC32MZ_TIMER config PIC32MZ_T4 bool "Timer 4 (T4)" default n + select PIC32MZ_TIMER config PIC32MZ_T5 bool "Timer 5 (T5)" default n + select PIC32MZ_TIMER config PIC32MZ_T6 bool "Timer 6 (T6)" default n + select PIC32MZ_TIMER config PIC32MZ_T7 bool "Timer 7 (T7)" default n + select PIC32MZ_TIMER config PIC32MZ_T8 bool "Timer 8 (T8)" default n + select PIC32MZ_TIMER config PIC32MZ_T9 bool "Timer 9 (T9)" default n + select PIC32MZ_TIMER config PIC32MZ_IC1 bool "Input Capture 1 (IC1)" @@ -300,6 +312,579 @@ config PIC32MZ_CTMU endmenu # PIC32MZ Peripheral Support +menu "Timer Configuration" + +if PIC32MZ_TIMER + +config PIC32MZ_FREERUN + bool "Timer free-running wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config PIC32MZ_ONESHOT + bool "Timer one-shot wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config PIC32MZ_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + default 1 + range 1 8 + depends on PIC32MZ_ONESHOT + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +endif #PIC32MZ_TIMER + +if PIC32MZ_T2 + +menu "Timer 2 configuration" + +config PIC32MZ_T2_STOPINIDLE + bool "Stop Timer 2 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T2_GATED + bool "Enable Timer 2 Gated Time Accumulation" + depends on !PIC32MZ_T2_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation +choice + prompt "Timer 2 Input clock prescale value" + default PIC32MZ_T2_PRESCALE_1 + +config PIC32MZ_T2_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T2_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T2_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T2_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T2_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T2_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T2_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T2_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T2_PRESCALE + int + default 7 if PIC32MZ_T2_PRESCALE_256 + default 6 if PIC32MZ_T2_PRESCALE_64 + default 5 if PIC32MZ_T2_PRESCALE_32 + default 4 if PIC32MZ_T2_PRESCALE_16 + default 3 if PIC32MZ_T2_PRESCALE_8 + default 2 if PIC32MZ_T2_PRESCALE_4 + default 1 if PIC32MZ_T2_PRESCALE_2 + default 0 if PIC32MZ_T2_PRESCALE_1 + +config PIC32MZ_T2_MODE32 + bool "Timer 2 Enable 32bits mode" + select PIC32MZ_T3 + ---help--- + Enable 32bits mode + +config PIC32MZ_T2_EXTERNALCLOCK + bool "Timer 2 external clock source" + default 0 + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T2 + +if PIC32MZ_T3 + +menu "Timer 3 Configuration" + depends on !PIC32MZ_T2_MODE32 + +config PIC32MZ_T3_STOPINIDLE + bool "Stop Timer 3 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T3_GATED + bool "Enable Timer 3 Gated Time Accumulation" + depends on !PIC32MZ_T3_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 3 Input clock prescale value" + default PIC32MZ_T3_PRESCALE_1 + +config PIC32MZ_T3_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T3_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T3_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T3_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T3_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T3_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T3_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T3_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T3_PRESCALE + int + default 7 if PIC32MZ_T3_PRESCALE_256 + default 6 if PIC32MZ_T3_PRESCALE_64 + default 5 if PIC32MZ_T3_PRESCALE_32 + default 4 if PIC32MZ_T3_PRESCALE_16 + default 3 if PIC32MZ_T3_PRESCALE_8 + default 2 if PIC32MZ_T3_PRESCALE_4 + default 1 if PIC32MZ_T3_PRESCALE_2 + default 0 if PIC32MZ_T3_PRESCALE_1 + +config PIC32MZ_T3_EXTERNALCLOCK + bool "Timer 3 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T3 + +if PIC32MZ_T4 + +menu "Timer 4 Configuration" + +config PIC32MZ_T4_STOPINIDLE + bool "Stop Timer 4 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T4_GATED + bool "Enable Timer 4 Gated Time Accumulation" + depends on !PIC32MZ_T4_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 4 Input clock prescale value" + default PIC32MZ_T4_PRESCALE_1 + +config PIC32MZ_T4_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T4_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T4_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T4_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T4_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T4_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T4_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T4_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T4_PRESCALE + int + default 7 if PIC32MZ_T4_PRESCALE_256 + default 6 if PIC32MZ_T4_PRESCALE_64 + default 5 if PIC32MZ_T4_PRESCALE_32 + default 4 if PIC32MZ_T4_PRESCALE_16 + default 3 if PIC32MZ_T4_PRESCALE_8 + default 2 if PIC32MZ_T4_PRESCALE_4 + default 1 if PIC32MZ_T4_PRESCALE_2 + default 0 if PIC32MZ_T4_PRESCALE_1 + +config PIC32MZ_T4_MODE32 + bool "Timer 4 Enable 32bits mode" + select PIC32MZ_T5 + ---help--- + Enable 32bits mode + +config PIC32MZ_T4_EXTERNALCLOCK + bool "Timer 4 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T4 + +if PIC32MZ_T5 + +menu "Timer 5 Configuration" + depends on !PIC32MZ_T4_MODE32 + +config PIC32MZ_T5_STOPINIDLE + bool "Stop Timer 5 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T5_GATED + bool "Enable Timer 5 Gated Time Accumulation" + depends on !PIC32MZ_T5_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 5 Input clock prescale value" + default PIC32MZ_T5_PRESCALE_1 + +config PIC32MZ_T5_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T5_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T5_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T5_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T5_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T5_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T5_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T5_PRESCALE_1 + bool "1:1 prescale" +endchoice + +config PIC32MZ_T5_PRESCALE + int + default 7 if PIC32MZ_T5_PRESCALE_256 + default 6 if PIC32MZ_T5_PRESCALE_64 + default 5 if PIC32MZ_T5_PRESCALE_32 + default 4 if PIC32MZ_T5_PRESCALE_16 + default 3 if PIC32MZ_T5_PRESCALE_8 + default 2 if PIC32MZ_T5_PRESCALE_4 + default 1 if PIC32MZ_T5_PRESCALE_2 + default 0 if PIC32MZ_T5_PRESCALE_1 + +config PIC32MZ_T5_EXTERNALCLOCK + bool "Timer 5 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T5 + +if PIC32MZ_T6 + +menu "Timer 6 Configuration" + +config PIC32MZ_T6_STOPINIDLE + bool "Stop Timer 6 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T6_GATED + bool "Enable Timer 6 Gated Time Accumulation" + depends on !PIC32MZ_T6_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 6 Input clock prescale value" + default PIC32MZ_T6_PRESCALE_1 + +config PIC32MZ_T6_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T6_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T6_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T6_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T6_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T6_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T6_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T6_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T6_PRESCALE + int + default 7 if PIC32MZ_T6_PRESCALE_256 + default 6 if PIC32MZ_T6_PRESCALE_64 + default 5 if PIC32MZ_T6_PRESCALE_32 + default 4 if PIC32MZ_T6_PRESCALE_16 + default 3 if PIC32MZ_T6_PRESCALE_8 + default 2 if PIC32MZ_T6_PRESCALE_4 + default 1 if PIC32MZ_T6_PRESCALE_2 + default 0 if PIC32MZ_T6_PRESCALE_1 + +config PIC32MZ_T6_MODE32 + bool "Timer 6 Enable 32bits mode" + select PIC32MZ_T7 + ---help--- + Enable 32bits mode + +config PIC32MZ_T6_EXTERNALCLOCK + bool "Timer 6 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T6 + +if PIC32MZ_T7 + +menu "Timer 7 Configuration" + depends on !PIC32MZ_T6_MODE32 + +config PIC32MZ_T7_STOPINIDLE + bool "Stop Timer 7 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T7_GATED + bool "Enable Timer 7 Gated Time Accumulation" + depends on !PIC32MZ_T7_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 7 Input clock prescale value" + default PIC32MZ_T7_PRESCALE_1 + +config PIC32MZ_T7_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T7_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T7_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T7_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T7_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T7_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T7_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T7_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T7_PRESCALE + int + default 7 if PIC32MZ_T7_PRESCALE_256 + default 6 if PIC32MZ_T7_PRESCALE_64 + default 5 if PIC32MZ_T7_PRESCALE_32 + default 4 if PIC32MZ_T7_PRESCALE_16 + default 3 if PIC32MZ_T7_PRESCALE_8 + default 2 if PIC32MZ_T7_PRESCALE_4 + default 1 if PIC32MZ_T7_PRESCALE_2 + default 0 if PIC32MZ_T7_PRESCALE_1 + +config PIC32MZ_T7_EXTERNALCLOCK + bool "Timer 7 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T7 + +if PIC32MZ_T8 + +menu "Timer 8 Configuration" + +config PIC32MZ_T8_STOPINIDLE + bool "Stop Timer 8 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T8_GATED + bool "Enable Timer 8 Gated Time Accumulation" + depends on !PIC32MZ_T8_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 8 Input clock prescale value" + default PIC32MZ_T8_PRESCALE_1 + +config PIC32MZ_T8_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T8_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T8_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T8_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T8_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T8_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T8_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T8_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T8_PRESCALE + int + default 7 if PIC32MZ_T8_PRESCALE_256 + default 6 if PIC32MZ_T8_PRESCALE_64 + default 5 if PIC32MZ_T8_PRESCALE_32 + default 4 if PIC32MZ_T8_PRESCALE_16 + default 3 if PIC32MZ_T8_PRESCALE_8 + default 2 if PIC32MZ_T8_PRESCALE_4 + default 1 if PIC32MZ_T8_PRESCALE_2 + default 0 if PIC32MZ_T8_PRESCALE_1 + +config PIC32MZ_T8_MODE32 + bool "Timer 8 Enable 32bits mode" + select PIC32MZ_T9 + ---help--- + Enable 32bits mode + +config PIC32MZ_T8_EXTERNALCLOCK + bool "Timer 8 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T8 + +if PIC32MZ_T9 + +menu "Timer 9 Configuration" + depends on !PIC32MZ_T8_MODE32 + +config PIC32MZ_T9_STOPINIDLE + bool "Stop Timer 9 in idle" + ---help--- + Stop Timer in idle + +config PIC32MZ_T9_GATED + bool "Enable Timer 9 Gated Time Accumulation" + depends on !PIC32MZ_T9_EXTERNALCLOCK + ---help--- + Enable Gated Time Accumulation + +choice + prompt "Timer 9 Input clock prescale value" + default PIC32MZ_T9_PRESCALE_1 + +config PIC32MZ_T9_PRESCALE_256 + bool "1:256 prescale" + +config PIC32MZ_T9_PRESCALE_64 + bool "1:64 prescale" + +config PIC32MZ_T9_PRESCALE_32 + bool "1:32 prescale" + +config PIC32MZ_T9_PRESCALE_16 + bool "1:16 prescale" + +config PIC32MZ_T9_PRESCALE_8 + bool "1:8 prescale" + +config PIC32MZ_T9_PRESCALE_4 + bool "1:4 prescale" + +config PIC32MZ_T9_PRESCALE_2 + bool "1:2 prescale" + +config PIC32MZ_T9_PRESCALE_1 + bool "1:1 prescale" + +endchoice + +config PIC32MZ_T9_PRESCALE + int + default 7 if PIC32MZ_T9_PRESCALE_256 + default 6 if PIC32MZ_T9_PRESCALE_64 + default 5 if PIC32MZ_T9_PRESCALE_32 + default 4 if PIC32MZ_T9_PRESCALE_16 + default 3 if PIC32MZ_T9_PRESCALE_8 + default 2 if PIC32MZ_T9_PRESCALE_4 + default 1 if PIC32MZ_T9_PRESCALE_2 + default 0 if PIC32MZ_T9_PRESCALE_1 + +config PIC32MZ_T9_EXTERNALCLOCK + bool "Timer 9 external clock source" + ---help--- + Enable Timer External clock + +endmenu +endif # PIC32MZ_T9 + + +endmenu # Timer Configuration + menuconfig PIC32MZ_GPIOIRQ bool "GPIO Interrupt Support" default n diff --git a/arch/mips/src/pic32mz/Make.defs b/arch/mips/src/pic32mz/Make.defs index 5577d868a65..c12fb925551 100644 --- a/arch/mips/src/pic32mz/Make.defs +++ b/arch/mips/src/pic32mz/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # arch/mips/src/pic32mz/Make.defs # -# Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved. +# Copyright (C) 2015, 2018, 2019 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -90,6 +90,24 @@ ifeq ($(CONFIG_PIC32MZ_I2C),y) CHIP_CSRCS += pic32mz-i2c.c endif +ifeq ($(CONFIG_PIC32MZ_TIMER),y) +CHIP_CSRCS += pic32mz-timer.c +endif + +ifeq ($(CONFIG_TIMER),y) +CHIP_CSRCS += pic32mz-timer-lowerhalf.c +else ifeq ($(CONFIG_PIC32MZ_ONESHOT),y) +CHIP_CSRCS += pic32mz-timer-lowerhalf.c +endif + +ifeq ($(CONFIG_PIC32MZ_FREERUN),y) +CHIP_CSRCS += pic32mz-freerun.c +endif + +ifeq ($(CONFIG_PIC32MZ_ONESHOT),y) +CHIP_CSRCS += pic32mz-oneshot.c +endif + ifeq ($(CONFIG_PIC32MZ_ETHERNET),y) CHIP_CSRCS += pic32mz-ethernet.c endif diff --git a/arch/mips/src/pic32mz/chip/pic32mz-timer.h b/arch/mips/src/pic32mz/chip/pic32mz-timer.h index 4cc12eacf0f..da54777ba9b 100644 --- a/arch/mips/src/pic32mz/chip/pic32mz-timer.h +++ b/arch/mips/src/pic32mz/chip/pic32mz-timer.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H -#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H +#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_TIMER_H +#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_TIMER_H /************************************************************************************ * Included Files @@ -308,4 +308,4 @@ extern "C" #endif /* __ASSEMBLY__ */ #endif /* CHIP_NTIMERS > 0 */ -#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H */ +#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_TIMER_H */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h index c027d6a346c..d8b3a12eed8 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mzec-pps.h @@ -1,7 +1,7 @@ /******************************************************************************************** * arch/mips/src/pic32mz/pic32mzec-pps.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,6 +45,7 @@ /******************************************************************************************** * Pre-processor Definitions ********************************************************************************************/ + /* PPS Register Offsets *********************************************************************/ /* Peripheral pin select input register map */ diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-pps.h b/arch/mips/src/pic32mz/chip/pic32mzef-pps.h index 8e65d3f3e91..89bc403f2bc 100644 --- a/arch/mips/src/pic32mz/chip/pic32mzef-pps.h +++ b/arch/mips/src/pic32mz/chip/pic32mzef-pps.h @@ -55,14 +55,14 @@ # define PIC32MZ_INT3R_OFFSET 0x140c # define PIC32MZ_INT4R_OFFSET 0x1410 #define PIC32MZ_TnCKR_OFFSET(n) (0x1410 + ((n << 2)) /* n=2..9 */ -# define PIC32MZ_I2TKR_OFFSET 0x1418 -# define PIC32MZ_I3TKR_OFFSET 0x141c -# define PIC32MZ_I4TKR_OFFSET 0x1420 -# define PIC32MZ_I5TKR_OFFSET 0x1424 -# define PIC32MZ_I6TKR_OFFSET 0x1428 -# define PIC32MZ_I7TKR_OFFSET 0x142c -# define PIC32MZ_I8TKR_OFFSET 0x1430 -# define PIC32MZ_I9TKR_OFFSET 0x1434 +# define PIC32MZ_T2CKR_OFFSET 0x1418 +# define PIC32MZ_T3CKR_OFFSET 0x141c +# define PIC32MZ_T4CKR_OFFSET 0x1420 +# define PIC32MZ_T5CKR_OFFSET 0x1424 +# define PIC32MZ_T6CKR_OFFSET 0x1428 +# define PIC32MZ_T7CKR_OFFSET 0x142c +# define PIC32MZ_T8CKR_OFFSET 0x1430 +# define PIC32MZ_T9CKR_OFFSET 0x1434 #define PIC32MZ_ICnR_OFFSET(n) (0x1434 + ((n << 2)) /* n=1..9 */ # define PIC32MZ_IC1R_OFFSET 0x1438 # define PIC32MZ_IC2R_OFFSET 0x143c @@ -189,14 +189,14 @@ # define PIC32MZ_INT3R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT3R_OFFSET) # define PIC32MZ_INT4R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT4R_OFFSET) #define PIC32MZ_TnCKR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_TnCKR_OFFSET(n)) -# define PIC32MZ_I2TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I2TKR_OFFSET) -# define PIC32MZ_I3TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I3TKR_OFFSET) -# define PIC32MZ_I4TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I4TKR_OFFSET) -# define PIC32MZ_I5TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I5TKR_OFFSET) -# define PIC32MZ_I6TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I6TKR_OFFSET) -# define PIC32MZ_I7TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I7TKR_OFFSET) -# define PIC32MZ_I8TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I8TKR_OFFSET) -# define PIC32MZ_I9TKR (PIC32MZ_SFR_K1BASE+PIC32MZ_I9TKR_OFFSET) +# define PIC32MZ_T2CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T2CKR_OFFSET) +# define PIC32MZ_T3CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T3CKR_OFFSET) +# define PIC32MZ_T4CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T4CKR_OFFSET) +# define PIC32MZ_T5CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T5CKR_OFFSET) +# define PIC32MZ_T6CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T6CKR_OFFSET) +# define PIC32MZ_T7CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T7CKR_OFFSET) +# define PIC32MZ_T8CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T8CKR_OFFSET) +# define PIC32MZ_T9CKR (PIC32MZ_SFR_K1BASE+PIC32MZ_T9CKR_OFFSET) #define PIC32MZ_ICnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_ICnR_OFFSET(n)) # define PIC32MZ_IC1R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC1R_OFFSET) # define PIC32MZ_IC2R (PIC32MZ_SFR_K1BASE+PIC32MZ_IC2R_OFFSET) diff --git a/arch/mips/src/pic32mz/pic32mz-freerun.c b/arch/mips/src/pic32mz/pic32mz-freerun.c new file mode 100644 index 00000000000..f92d9e84298 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-freerun.c @@ -0,0 +1,335 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-freerun.c + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "pic32mz-freerun.h" + +#ifdef CONFIG_PIC32MZ_FREERUN + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING +static int pic32mz_freerun_handler(int irq, void *context, void *arg); +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_freerun_handler + * + * Description: + * Timer interrupt callback. When the freerun timer counter overflows, + * this interrupt will occur. We will just increment an overflow count. + * + * Input Parameters: + * irq Number of the IRQ that generated the interrupt + * context Interrupt register state save info (architecture-specific) + * arg An opaque argument provided when the interrupt was registered + * + * Returned Value: + * OK on success + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING +static int pic32mz_freerun_handler(int irq, void *context, void *arg) +{ + struct pic32mz_freerun_s *freerun = (struct pic32mz_freerun_s *) arg; + + DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); + freerun->overflow++; + + PIC32MZ_TIMER_ACKINT(freerun->timer); + + return OK; +} +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_freerun_initialize(struct pic32mz_freerun_s *freerun, int chan, + uint16_t resolution) +{ + uint32_t freq; + + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); + DEBUGASSERT(freerun != NULL && resolution > 0); + + freerun->timer = pic32mz_timer_init(chan); + if (!freerun->timer) + { + tmrerr("ERROR: Failed to allocate timer%d\n", chan); + return -EBUSY; + } + + /* Get the timer's frequency that corresponds to the requested resolution */ + + freq = USEC_PER_SEC / (uint32_t)resolution; + + tmrinfo("Setting frequency=%luHz\n", freq); + + if (!PIC32MZ_TIMER_SETFREQ(freerun->timer, freq)) + { + tmrerr("Cannot set frequency=%luHz\n", freq); + return -EAGAIN; + } + + /* Initialize the remaining fields in the state structure. + * + * The timer's frequency might not be the same as requested, + * due to the lack of prescale values. Get it from the driver. + */ + + freerun->freq = PIC32MZ_TIMER_GETFREQ(freerun->timer); + freerun->width = PIC32MZ_TIMER_GETWIDTH(freerun->timer); + freerun->chan = chan; + freerun->running = false; + +#ifdef CONFIG_CLOCK_TIMEKEEPING + if (freerun->width == 32) + { + freerun->counter_mask = 0xffffffffull; + } + else + { + freerun->counter_mask = 0x0000ffffull; + } +#endif + +#ifndef CONFIG_CLOCK_TIMEKEEPING + freerun->overflow = 0; + + /* Set up to receive the callback when the counter overflow occurs */ + + PIC32MZ_TIMER_ACKINT(freerun->timer); + PIC32MZ_TIMER_SETISR(freerun->timer, pic32mz_freerun_handler, freerun); +#endif + + /* Set the period */ + + PIC32MZ_TIMER_SETPERIOD(freerun->timer, + (uint32_t)((1ull << freerun->width) - 1ul)); + + /* Start the timer */ + + PIC32MZ_TIMER_START(freerun->timer); + freerun->running = true; + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * pic32mz_freerun_initialize(); + * ts The location in which to return the time from the free-running + * timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING + +int pic32mz_freerun_counter(struct pic32mz_freerun_s *freerun, + struct timespec *ts) +{ + uint64_t usec; + uint32_t counter; + uint32_t verify; + uint32_t overflow; + uint32_t sec; + bool pending; + irqstate_t flags; + + DEBUGASSERT(freerun && freerun->timer && ts); + + /* Temporarily disable the overflow counter. */ + + flags = enter_critical_section(); + + overflow = freerun->overflow; + counter = PIC32MZ_TIMER_GETCOUNTER(freerun->timer); + pending = PIC32MZ_TIMER_CHECKINT(freerun->timer); + verify = PIC32MZ_TIMER_GETCOUNTER(freerun->timer); + + /* If an interrupt was pending before we re-enabled interrupts, + * then the overflow needs to be incremented. + */ + + if (pending) + { + PIC32MZ_TIMER_ACKINT(freerun->timer); + + /* Increment the overflow count and use the value of the + * guaranteed to be AFTER the overflow occurred. + */ + + overflow++; + counter = verify; + + /* Update freerun overflow counter. */ + + freerun->overflow = overflow; + } + + leave_critical_section(flags); + + tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n", + (unsigned long)counter, (unsigned long)verify, + (unsigned long)overflow, pending); + tmrinfo("frequency=%u\n", freerun->freq); + + /* Convert the whole thing to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = ((((uint64_t)overflow << freerun->width) + + (uint64_t)counter) * USEC_PER_SEC) / freerun->freq; + + /* And return the value of the timer */ + + sec = (uint32_t)(usec / USEC_PER_SEC); + ts->tv_sec = sec; + ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + tmrinfo("usec=%llu ts=(%u, %lu)\n", + usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + + return OK; +} + +#else /* CONFIG_CLOCK_TIMEKEEPING */ + +int pic32mz_freerun_counter(struct pic32mz_freerun_s *freerun, + uint64_t *counter) +{ + *counter = (uint64_t)PIC32MZ_TIMER_GETCOUNTER(freerun->timer) & + freerun->counter_mask; + return OK; +} + +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Name: pic32mz_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * pic32mz_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_freerun_uninitialize(struct pic32mz_freerun_s *freerun) +{ + DEBUGASSERT(freerun && freerun->timer); + + /* Now we can disable the timer interrupt */ + + PIC32MZ_TIMER_SETISR(freerun->timer, NULL, NULL); + + /* Free the timer, this will stop the timer as well */ + + pic32mz_timer_deinit(freerun->timer); + + freerun->running = false; + freerun->timer = NULL; + + return OK; +} + +#endif /* CONFIG_PIC32MZ_FREERUN */ diff --git a/arch/mips/src/pic32mz/pic32mz-freerun.h b/arch/mips/src/pic32mz/pic32mz-freerun.h new file mode 100644 index 00000000000..65c1345d282 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-freerun.h @@ -0,0 +1,179 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-freerun.h + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_FREERUN_H +#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_FREERUN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "pic32mz-timer.h" + +#ifdef CONFIG_PIC32MZ_FREERUN + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The freerun client must allocate an instance of this structure and call + * pic32mz_freerun_initialize() before using the freerun facilities. + * The client should not access the contents of this structure directly + * since the contents are subject to change. + */ + +struct pic32mz_freerun_s +{ + uint8_t chan; /* The timer in use */ + uint8_t width; /* Width of timer (16- or 32) */ + bool running; /* True: the timer is running */ + FAR struct pic32mz_timer_dev_s *timer; /* PIC32MZ timer driver */ + uint32_t freq; /* Timer's frequency (Hz) */ + +#ifndef CONFIG_CLOCK_TIMEKEEPING + uint32_t overflow; /* Timer's counter overflow */ +#endif + +#ifdef CONFIG_CLOCK_TIMEKEEPING + uint64_t counter_mask; /* Timer's count register mask */ +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure + * chan Timer channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_freerun_initialize(struct pic32mz_freerun_s *freerun, int chan, + uint16_t resolution); + +/**************************************************************************** + * Name: pic32mz_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * pic32mz_freerun_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#ifndef CONFIG_CLOCK_TIMEKEEPING + +int pic32mz_freerun_counter(struct pic32mz_freerun_s *freerun, + struct timespec *ts); + +#else /* CONFIG_CLOCK_TIMEKEEPING */ + +int pic32mz_freerun_counter(struct pic32mz_freerun_s *freerun, + uint64_t *counter); + +#endif /* CONFIG_CLOCK_TIMEKEEPING */ + +/**************************************************************************** + * Name: pic32mz_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * pic32mz_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_freerun_uninitialize(struct pic32mz_freerun_s *freerun); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_PIC32MZ_FREERUN */ +#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_FREERUN_H */ diff --git a/arch/mips/src/pic32mz/pic32mz-oneshot-lowerhalf.c b/arch/mips/src/pic32mz/pic32mz-oneshot-lowerhalf.c new file mode 100644 index 00000000000..5f79c40d2ef --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-oneshot-lowerhalf.c @@ -0,0 +1,353 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-oneshot-lowerhalf.c + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "pic32mz-oneshot.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of the oneshot lower-half driver */ + +struct pic32mz_oneshot_lowerhalf_s +{ + /* This is the part of the lower half driver that is visible to the upper- + * half client of the driver. This must be the first thing in this + * structure so that pointers to struct oneshot_lowerhalf_s are cast + * compatible to struct pic32mz_oneshot_lowerhalf_s and vice versa. + */ + + struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ + + /* Private lower half data follows */ + + struct pic32mz_oneshot_s oneshot; /* PIC32MZ-specific oneshot state */ + oneshot_callback_t callback; /* Handler that receives callback */ + FAR void *arg; /* Argument passed to the handler */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void pic32mz_oneshot_handler(void *arg); + +static int pic32mz_max_delay(FAR struct oneshot_lowerhalf_s *lower, + FAR struct timespec *ts); +static int pic32mz_start(FAR struct oneshot_lowerhalf_s *lower, + oneshot_callback_t callback, FAR void *arg, + FAR const struct timespec *ts); +static int pic32mz_cancel(FAR struct oneshot_lowerhalf_s *lower, + FAR struct timespec *ts); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Lower half operations */ + +static const struct oneshot_operations_s g_oneshot_ops = +{ + .max_delay = pic32mz_max_delay, + .start = pic32mz_start, + .cancel = pic32mz_cancel, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_oneshot_handler + * + * Description: + * Timer expiration handler + * + * Input Parameters: + * arg Should be the same argument provided when pic32mz_oneshot_start() + * was called. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pic32mz_oneshot_handler(void *arg) +{ + FAR struct pic32mz_oneshot_lowerhalf_s *priv = + (FAR struct pic32mz_oneshot_lowerhalf_s *)arg; + oneshot_callback_t callback; + FAR void *cbarg; + + DEBUGASSERT(priv != NULL); + + /* Perhaps the callback was nullified in a race condition with + * pic32mz_cancel? + */ + + if (priv->callback) + { + /* Sample and nullify BEFORE executing callback (in case the callback + * restarts the oneshot). + */ + + callback = priv->callback; + cbarg = priv->arg; + priv->callback = NULL; + priv->arg = NULL; + + /* Then perform the callback */ + + callback(&priv->lh, cbarg); + } +} + +/**************************************************************************** + * Name: pic32mz_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the maxumum delay. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int pic32mz_max_delay(FAR struct oneshot_lowerhalf_s *lower, + FAR struct timespec *ts) +{ + FAR struct pic32mz_oneshot_lowerhalf_s *priv = + (FAR struct pic32mz_oneshot_lowerhalf_s *)lower; + uint64_t usecs; + int ret; + + DEBUGASSERT(priv != NULL && ts != NULL); + + ret = pic32mz_oneshot_max_delay(&priv->oneshot, &usecs); + tmrinfo("max delay %lu\n", usecs); + + if (ret >= 0) + { + uint64_t sec = usecs / 1000000; + usecs -= 1000000 * sec; + + ts->tv_sec = (time_t)sec; + ts->tv_nsec = (long)(usecs * 1000); + } + + return ret; +} + +/**************************************************************************** + * Name: pic32mz_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int pic32mz_start(FAR struct oneshot_lowerhalf_s *lower, + oneshot_callback_t callback, FAR void *arg, + FAR const struct timespec *ts) +{ + FAR struct pic32mz_oneshot_lowerhalf_s *priv = + (FAR struct pic32mz_oneshot_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL); + + /* Save the callback information and start the timer */ + + flags = enter_critical_section(); + priv->callback = callback; + priv->arg = arg; + ret = pic32mz_oneshot_start(&priv->oneshot, + pic32mz_oneshot_handler, + priv, ts); + leave_critical_section(flags); + + if (ret < 0) + { + tmrerr("ERROR: pic32mz_oneshot_start failed: %d\n", flags); + } + + return ret; +} + +/**************************************************************************** + * Name: pic32mz_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * lower Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +static int pic32mz_cancel(FAR struct oneshot_lowerhalf_s *lower, + FAR struct timespec *ts) +{ + FAR struct pic32mz_oneshot_lowerhalf_s *priv = + (FAR struct pic32mz_oneshot_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + DEBUGASSERT(priv != NULL); + + /* Cancel the timer */ + + flags = enter_critical_section(); + ret = pic32mz_oneshot_cancel(&priv->oneshot, ts); + priv->callback = NULL; + priv->arg = NULL; + leave_critical_section(flags); + + if (ret < 0) + { + tmrerr("ERROR: pic32mz_oneshot_cancel failed: %d\n", flags); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: oneshot_initialize + * + * Description: + * Initialize the oneshot timer and return a oneshot lower half driver + * instance. + * + * Input Parameters: + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * On success, a non-NULL instance of the oneshot lower-half driver is + * returned. NULL is return on any failure. + * + ****************************************************************************/ + +FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan, + uint16_t resolution) +{ + FAR struct pic32mz_oneshot_lowerhalf_s *priv; + int ret; + + /* Allocate an instance of the lower half driver */ + + priv = (FAR struct pic32mz_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct pic32mz_oneshot_lowerhalf_s)); + + if (priv == NULL) + { + tmrerr("ERROR: Failed to initialized state structure\n"); + return NULL; + } + + /* Initialize the lower-half driver structure */ + + priv->lh.ops = &g_oneshot_ops; + + /* Initialize the contained PIC32MZ oneshot timer */ + + ret = pic32mz_oneshot_initialize(&priv->oneshot, chan, resolution); + if (ret < 0) + { + tmrerr("ERROR: pic32mz_oneshot_initialize failed: %d\n", ret); + kmm_free(priv); + return NULL; + } + + return &priv->lh; +} diff --git a/arch/mips/src/pic32mz/pic32mz-oneshot.c b/arch/mips/src/pic32mz/pic32mz-oneshot.c new file mode 100644 index 00000000000..bd0b30f39b5 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-oneshot.c @@ -0,0 +1,464 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-oneshot.c + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "pic32mz-oneshot.h" + +#ifdef CONFIG_PIC32MZ_ONESHOT + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int pic32mz_oneshot_handler(int irg_num, void * context, void *arg); +static inline int pic32mz_allocate_handler(struct pic32mz_oneshot_s *oneshot); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct pic32mz_oneshot_s *g_oneshot[CONFIG_PIC32MZ_ONESHOT_MAXTIMERS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_oneshot_handler + * + * Description: + * Common timer interrupt callback. When any oneshot timer interrupt + * expires, this function will be called. It will forward the call to + * the next level up. + * + * Input Parameters: + * oneshot The state associated with the expired timer + * + * Returned Value: + * Always returns OK + * + ****************************************************************************/ + +static int pic32mz_oneshot_handler(int irg_num, void * context, void *arg) +{ + struct pic32mz_oneshot_s * oneshot = (struct pic32mz_oneshot_s *) arg; + oneshot_handler_t oneshot_handler; + void *oneshot_arg; + + tmrinfo("Expired...\n"); + DEBUGASSERT(oneshot != NULL && oneshot->handler); + + /* Stop the timer and disable any further interrupts */ + + PIC32MZ_TIMER_ACKINT(oneshot->timer); + PIC32MZ_TIMER_SETISR(oneshot->timer, NULL, NULL); + PIC32MZ_TIMER_STOP(oneshot->timer); + + /* The timer is no longer running */ + + oneshot->running = false; + + /* Forward the event, clearing out any vestiges */ + + oneshot_handler = (oneshot_handler_t)oneshot->handler; + oneshot->handler = NULL; + oneshot_arg = (void *)oneshot->arg; + oneshot->arg = NULL; + + oneshot_handler(oneshot_arg); + return OK; +} + +/**************************************************************************** + * Name: pic32mz_allocate_handler + * + * Description: + * Allocate a timer callback handler for the oneshot instance. + * + * Input Parameters: + * oneshot The state instance the new oneshot timer + * + * Returned Value: + * Returns zero (OK) on success. This can only fail if the number of + * timers exceeds CONFIG_PIC32MZ_ONESHOT_MAXTIMERS. + * + ****************************************************************************/ + +static inline int pic32mz_allocate_handler(struct pic32mz_oneshot_s *oneshot) +{ +#if CONFIG_PIC32MZ_ONESHOT_MAXTIMERS > 1 + int ret = -EBUSY; + int i; + + /* Search for an unused handler */ + + sched_lock(); + for (i = 0; i < CONFIG_PIC32MZ_ONESHOT_MAXTIMERS; i++) + { + /* Is this handler available? */ + + if (g_oneshot[i] == NULL) + { + /* Yes... assign it to this oneshot */ + + g_oneshot[i] = oneshot; + oneshot->cbndx = i; + ret = OK; + break; + } + } + + sched_unlock(); + return ret; + +#else + if (g_oneshot[0] == NULL) + { + g_oneshot[0] = oneshot; + return OK; + } + + return -EBUSY; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_oneshot_initialize(struct pic32mz_oneshot_s *oneshot, int chan, + uint16_t resolution) +{ + uint32_t freq; + + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); + DEBUGASSERT(oneshot && resolution > 0); + + oneshot->timer = pic32mz_timer_init(chan); + if (!oneshot->timer) + { + tmrerr("ERROR: Failed to allocate timer%d\n", chan); + return -EBUSY; + } + + /* Get the timer's frequency that corresponds to the requested resolution */ + + freq = USEC_PER_SEC / (uint32_t)resolution; + tmrinfo("Setting frequency=%luHz\n", freq); + + if (!PIC32MZ_TIMER_SETFREQ(oneshot->timer, freq)) + { + tmrerr("Cannot set frequency=%luHz\n", freq); + return -EAGAIN; + } + + /* Initialize the remaining fields in the state structure. + * + * The timer's frequency might not be the same as requested, + * due to the lack of prescale values. Get it from the driver. + */ + + oneshot->freq = PIC32MZ_TIMER_GETFREQ(oneshot->timer); + oneshot->width = PIC32MZ_TIMER_GETWIDTH(oneshot->timer); + oneshot->chan = chan; + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + + /* Assign a callback handler to the oneshot */ + + return pic32mz_allocate_handler(oneshot); +} + +/**************************************************************************** + * Name: pic32mz_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int pic32mz_oneshot_max_delay(struct pic32mz_oneshot_s *oneshot, + uint64_t *usec) +{ + uint32_t maxticks; + + maxticks = (1ull << oneshot->width) - 1ul; + + DEBUGASSERT(oneshot != NULL && usec != NULL); + tmrinfo("width=%u freq=%lu max ticks=%lu\n", + oneshot->width, oneshot->freq, maxticks); + + *usec = (maxticks / oneshot->freq) * USEC_PER_SEC; + + tmrinfo("max delay %lu\n", *usec); + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. + * This structure must have been previously initialized via + * a call to pic32mz_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_oneshot_start(struct pic32mz_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts) +{ + uint64_t usec; + uint64_t period; + irqstate_t flags; + + tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", + handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + DEBUGASSERT(oneshot && handler && ts); + DEBUGASSERT(oneshot->timer); + + flags = enter_critical_section(); + + /* Was the oneshot already running? */ + + if (oneshot->running) + { + /* Yes.. then cancel it */ + + tmrinfo("Already running... cancelling\n"); + (void)pic32mz_oneshot_cancel(oneshot, NULL); + } + + /* Save the new handler and its argument */ + + oneshot->handler = handler; + oneshot->arg = arg; + + /* Express the delay in microseconds */ + + usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + + period = (usec * (uint64_t)oneshot->freq) / USEC_PER_SEC; + + tmrinfo("usec=%llu period=%08llx\n", usec, period); + DEBUGASSERT(period <= ((1ull << oneshot->width) - 1ul)); + + /* Set timer period */ + + oneshot->period = (uint32_t)period; + PIC32MZ_TIMER_SETPERIOD(oneshot->timer, (uint32_t)period); + + /* Set up to receive the callback and start the timer */ + + PIC32MZ_TIMER_ACKINT(oneshot->timer); + PIC32MZ_TIMER_SETISR(oneshot->timer, pic32mz_oneshot_handler, oneshot); + PIC32MZ_TIMER_START(oneshot->timer); + + oneshot->running = true; + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * pic32mz_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. ts may be zero in which case the time remaining + * is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int pic32mz_oneshot_cancel(struct pic32mz_oneshot_s *oneshot, + struct timespec *ts) +{ + irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint32_t count; + uint32_t period; + + flags = enter_critical_section(); + + /* Was the timer running? */ + + if (!oneshot->running) + { + /* No.. Just return zero timer remaining and successful cancellation. + * This function may execute at a high rate with no timer running + * (as when pre-emption is enabled and disabled). + */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + leave_critical_section(flags); + + return OK; + } + + /* Yes.. Get the timer counter and period registers and stop the counter. */ + + tmrinfo("Cancelling...\n"); + + count = PIC32MZ_TIMER_GETCOUNTER(oneshot->timer); + period = oneshot->period; + + PIC32MZ_TIMER_SETISR(oneshot->timer, NULL, NULL); + PIC32MZ_TIMER_STOP(oneshot->timer); + + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + leave_critical_section(flags); + + /* Did the caller provide us with a location to return the time + * remaining? + */ + + if (ts) + { + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ + + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + + if (count >= period) + { + /* No time remaining (?) */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + /* The total time remaining is the difference. Convert the that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + oneshot->freq; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = (time_t)sec; + ts->tv_nsec = (unsigned long)nsec; + } + + tmrinfo("remaining (%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + } + + return OK; +} + +#endif /* CONFIG_PIC32MZ_ONESHOT */ diff --git a/arch/mips/src/pic32mz/pic32mz-oneshot.h b/arch/mips/src/pic32mz/pic32mz-oneshot.h new file mode 100644 index 00000000000..15a61ddd413 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-oneshot.h @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-oneshort.h + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_ONESHOT_H +#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "pic32mz-timer.h" + +#ifdef CONFIG_PIC32MZ_ONESHOT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_PIC32MZ_ONESHOT_MAXTIMERS) || \ + CONFIG_PIC32MZ_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_PIC32MZ_ONESHOT_MAXTIMERS +# define CONFIG_PIC32MZ_ONESHOT_MAXTIMERS 1 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This describes the callback function that will be invoked when the oneshot + * timer expires. When the oneshot fires, the client will receive: + * + * arg - The opaque argument provided when the interrupt was registered + */ + +typedef void (*oneshot_handler_t)(void *arg); + +/* The oneshot client must allocate an instance of this structure and called + * pic32mz_oneshot_initialize() before using the oneshot facilities. + * The client should not access the contents of this structure directly + * since the contents are subject to change. + */ + +struct pic32mz_oneshot_s +{ + uint8_t chan; /* The timer/counter in use */ +#if CONFIG_PIC32MZ_ONESHOT_MAXTIMERS > 1 + uint8_t cbndx; /* Timer callback handler index */ +#endif + volatile bool running; /* True: the timer is running */ + FAR struct pic32mz_timer_dev_s *timer; /* PIC32MZ timer driver */ + volatile oneshot_handler_t handler; /* Oneshot expiration callback */ + volatile void *arg; /* Callback's argument */ + uint32_t freq; /* Timer's frequency */ + uint32_t period; /* Timer's period */ + uint8_t width; /* Timer's width */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_oneshot_initialize(struct pic32mz_oneshot_s *oneshot, int chan, + uint16_t resolution); + +/**************************************************************************** + * Name: pic32mz_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int pic32mz_oneshot_max_delay(struct pic32mz_oneshot_s *oneshot, + uint64_t *usec); + +/**************************************************************************** + * Name: pic32mz_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * pic32mz_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int pic32mz_oneshot_start(struct pic32mz_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); + +/**************************************************************************** + * Name: pic32mz_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * pic32mz_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int pic32mz_oneshot_cancel(struct pic32mz_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_PIC32MZ_ONESHOT */ +#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_ONESHOT_H */ diff --git a/arch/mips/src/pic32mz/pic32mz-timer-lowerhalf.c b/arch/mips/src/pic32mz/pic32mz-timer-lowerhalf.c new file mode 100644 index 00000000000..6eea1c40b57 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-timer-lowerhalf.c @@ -0,0 +1,714 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-timer-lowerhalf.c + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "pic32mz-timer.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* One of the type B timers should be defined. */ + +#if defined(CONFIG_TIMER) && defined(CONFIG_PIC32MZ_TIMER) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * timer_lowerhalf_s structure. + */ + +struct pic32mz_lowerhalf_s +{ + FAR const struct timer_ops_s *ops; /* Lower half operations */ + FAR struct pic32mz_timer_dev_s *timer; /* pic32mz timer driver */ + tccb_t callback; /* Current user interrupt cb */ + FAR void *arg; /* Argument to upper half cb */ + uint32_t timeout; /* Current timeout value (us) */ + uint32_t ticks; /* Timeout converted in ticks */ + uint32_t freq; /* Timer's frequency (Hz) */ + uint8_t width; /* Timer's width */ + uint32_t maxticks; /* Maximum ticks for this timer */ + bool started; /* True: Timer has been started */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helper functions *********************************************************/ + +static uint32_t pic32mz_usec2ticks(struct pic32mz_lowerhalf_s *priv, + uint32_t usecs); +static uint32_t pic32mz_ticks2usec(struct pic32mz_lowerhalf_s *priv, + uint32_t ticks); + +/* Interrupt handling *******************************************************/ + +static int pic32mz_timer_handler(int irq, void * context, void * arg); + +/* "Lower half" driver methods **********************************************/ + +static int pic32mz_start(FAR struct timer_lowerhalf_s *lower); +static int pic32mz_stop(FAR struct timer_lowerhalf_s *lower); +static int pic32mz_getstatus(struct timer_lowerhalf_s *lower, + struct timer_status_s *status); +static int pic32mz_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout); +static void pic32mz_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg); +static int pic32mz_ioctl(struct timer_lowerhalf_s *lower, int cmd, + unsigned long arg); +static int pic32mz_maxtimeout(FAR struct timer_lowerhalf_s *lower, + FAR uint32_t *maxtimeout); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct timer_ops_s g_timer_ops = +{ + .start = pic32mz_start, + .stop = pic32mz_stop, + .getstatus = pic32mz_getstatus, + .settimeout = pic32mz_settimeout, + .setcallback = pic32mz_setcallback, + .ioctl = pic32mz_ioctl, + .maxtimeout = pic32mz_maxtimeout, +}; + +#ifdef CONFIG_PIC32MZ_T2 +static struct pic32mz_lowerhalf_s g_t2_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T3 +static struct pic32mz_lowerhalf_s g_t3_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T4 +static struct pic32mz_lowerhalf_s g_t4_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T5 +static struct pic32mz_lowerhalf_s g_t5_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T6 +static struct pic32mz_lowerhalf_s g_t6_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T7 +static struct pic32mz_lowerhalf_s g_t7_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T8 +static struct pic32mz_lowerhalf_s g_t8_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T9 +static struct pic32mz_lowerhalf_s g_t9_lowerhalf = +{ + .ops = &g_timer_ops, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_usec2ticks + * + * Description: + * Convert microseconds to timer clock ticks. + * + * Input Parameters: + * priv A pointer to a private timer driver lower half instance + * usecs The number of usecs to convert + * + * Returned Value: + * The time converted to clock ticks. + * + ****************************************************************************/ + +static uint32_t pic32mz_usec2ticks(FAR struct pic32mz_lowerhalf_s *priv, + uint32_t usecs) +{ + uint64_t bigticks; + + bigticks = ((uint64_t)usecs * (uint64_t)priv->freq) / 1000000; + + if (bigticks > UINT32_MAX) + { + return UINT32_MAX; + } + + return (uint32_t)bigticks; +} + +/**************************************************************************** + * Name: pic32mz_ticks2usec + * + * Description: + * Convert timer clock ticks to microseconds. + * + * Input Parameters: + * priv A pointer to a private timer driver lower half instance + * usecs The number of ticks to convert + * + * Returned Value: + * The time converted to microseconds. + * + ****************************************************************************/ + +static uint32_t pic32mz_ticks2usec(FAR struct pic32mz_lowerhalf_s *priv, + uint32_t ticks) +{ + uint64_t bigusec; + + bigusec = (1000000ull * (uint64_t)ticks) / priv->freq; + if (bigusec > UINT32_MAX) + { + return UINT32_MAX; + } + + return (uint32_t)bigusec; +} + +/**************************************************************************** + * Name: pic32mz_timer_handler + * + * Description: + * timer interrupt handler + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int pic32mz_timer_handler(int irq, FAR void *context, FAR void *arg) +{ + FAR struct pic32mz_lowerhalf_s *lower = + (struct pic32mz_lowerhalf_s *) arg; + uint32_t next_interval_us = 0; + + PIC32MZ_TIMER_ACKINT(lower->timer); + + if (lower->callback && lower->callback(&next_interval_us, lower->arg)) + { + if (next_interval_us > 0) + { + /* Stop the timer before writing the new period, + * to prevent unintended period matches. + */ + + PIC32MZ_TIMER_STOP(lower->timer); + + PIC32MZ_TIMER_SETPERIOD(lower->timer, next_interval_us); + + PIC32MZ_TIMER_START(lower->timer); + } + } + else + { + pic32mz_stop((struct timer_lowerhalf_s *)lower); + } + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_start + * + * Description: + * Start the timer, resetting the time to the current timeout, + * + * Input Parameters: + * lower A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int pic32mz_start(FAR struct timer_lowerhalf_s *lower) +{ + FAR struct pic32mz_lowerhalf_s *priv = + (FAR struct pic32mz_lowerhalf_s *)lower; + + if (!priv->started) + { + if (priv->callback != NULL) + { + PIC32MZ_TIMER_SETISR(priv->timer, pic32mz_timer_handler, priv); + } + + PIC32MZ_TIMER_START(priv->timer); + + priv->started = true; + + return OK; + } + + /* Return EBUSY to indicate that the timer was already running */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: pic32mz_stop + * + * Description: + * Stop the timer + * + * Input Parameters: + * lower A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int pic32mz_stop(FAR struct timer_lowerhalf_s *lower) +{ + FAR struct pic32mz_lowerhalf_s *priv = + (FAR struct pic32mz_lowerhalf_s *)lower; + + if (priv->started) + { + PIC32MZ_TIMER_STOP(priv->timer); + PIC32MZ_TIMER_SETISR(priv->timer, NULL, NULL); + priv->started = false; + + return OK; + } + + /* Return ENODEV to indicate that the timer was not running */ + + return -ENODEV; +} + +/**************************************************************************** + * Name: pic32mz_getstatus + * + * Description: + * Get the current timer status + * + * Input Parameters: + * lower A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * status The location to return the status information. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int pic32mz_getstatus(FAR struct timer_lowerhalf_s *lower, + FAR struct timer_status_s *status) +{ + FAR struct pic32mz_lowerhalf_s *priv = + (FAR struct pic32mz_lowerhalf_s *)lower; + uint32_t remainingticks; + + DEBUGASSERT(priv); + + /* Return the status bit */ + + status->flags = 0; + if (priv->started) + { + status->flags |= TCFLAGS_ACTIVE; + } + + if (priv->callback) + { + status->flags |= TCFLAGS_HANDLER; + } + + /* Return the actual timeout in microseconds */ + + status->timeout = priv->timeout; + + /* Get the remaining ticks for the next overflow. */ + + remainingticks = priv->ticks - PIC32MZ_TIMER_GETCOUNTER(priv->timer); + + /* Convert the remaining ticks to microseconds. */ + + status->timeleft = pic32mz_ticks2usec(priv, remainingticks); + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_settimeout + * + * Description: + * Set a new timeout value (and reset the timer) + * + * Input Parameters: + * lower A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout The new timeout value in microseconds. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int pic32mz_settimeout(FAR struct timer_lowerhalf_s *lower, + uint32_t timeout) +{ + FAR struct pic32mz_lowerhalf_s *priv = + (FAR struct pic32mz_lowerhalf_s *)lower; + + DEBUGASSERT(priv); + + if (priv->started) + { + return -EPERM; + } + + tmrinfo("Entry: timeout = %d\n", timeout); + + priv->timeout = timeout; + + /* Convert the timeout to ticks. */ + + priv->ticks = pic32mz_usec2ticks(priv, timeout); + + tmrinfo("Timeout ticks = %ld\n", priv->ticks); + + if (priv->ticks == 0) + { + tmrerr("The timeout value can't be represented by " + "the current config! Try a different prescaler.\n"); + + /* REVISIT: This might be done by trying all the prescale values + * (there aren't that much) and find the first that can represent + * these ticks. + */ + + return -EAGAIN; + } + else if (priv->ticks > priv->maxticks) + { + tmrwarn("Timeout value truncated! Consider a different prescaler.\n"); + + /* REVISIT: Try a different prescale value first. */ + + PIC32MZ_TIMER_SETPERIOD(priv->timer, priv->maxticks); + } + else + { + PIC32MZ_TIMER_SETPERIOD(priv->timer, priv->ticks); + } + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_setcallback + * + * Description: + * Call this user provided timeout callback. + * + * Input Parameters: + * lower A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * callback The new timer expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored. + * arg Argument that will be provided in the callback. + * + * Returned Value: + * The previous timer expiration function pointer or NULL is there was + * no previous function pointer. + * + ****************************************************************************/ + +static void pic32mz_setcallback(FAR struct timer_lowerhalf_s *lower, + tccb_t callback, FAR void *arg) +{ + FAR struct pic32mz_lowerhalf_s *priv = + (FAR struct pic32mz_lowerhalf_s *)lower; + + irqstate_t flags = enter_critical_section(); + + DEBUGASSERT(priv); + + /* Save the new callback */ + + priv->callback = callback; + priv->arg = arg; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: pic32mz_ioctl + * + * Description: + * Any ioctl commands that are not recognized by the "upper-half" driver + * are forwarded to the lower half driver through this method. + * + * Input Parameters: + * lower A pointer the publicly visible representation of the "lower-half" + * driver state structure. + * cmd The ioctl command value + * arg The optional argument that accompanies the 'cmd'. The + * interpretation of this argument depends on the particular + * command. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int pic32mz_ioctl(FAR struct timer_lowerhalf_s *lower, int cmd, + unsigned long arg) +{ + int ret = -ENOTTY; + + DEBUGASSERT(lower); + tmrinfo("Entry: cmd=%d arg=%ld\n", cmd, arg); + + return ret; +} + +/**************************************************************************** + * Name: pic32mz_ioctl + * + * Description: + * Get the maximum supported timeout value + * + * Input Parameters: + * lower A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * maxtimeout The max value in microseconds will be written here. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int pic32mz_maxtimeout(FAR struct timer_lowerhalf_s *lower, + FAR uint32_t *maxtimeout) +{ + FAR struct pic32mz_lowerhalf_s *priv = + (FAR struct pic32mz_lowerhalf_s *)lower; + + DEBUGASSERT(priv); + + /* Convert ticks to microseconds */ + + *maxtimeout = pic32mz_ticks2usec(priv, priv->maxticks); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath The full path to the timer device. This should be of the + * form /dev/timer0 + * timer the timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int pic32mz_timer_initialize(FAR const char *devpath, int timer) +{ + FAR struct pic32mz_lowerhalf_s *lower; + FAR void *drvr; + + tmrinfo("Initializing %s - timer %d\n", devpath, timer); + + switch (timer) + { +#ifdef CONFIG_PIC32MZ_T2 + case 2: + lower = &g_t2_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T3 + case 3: + lower = &g_t3_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T4 + case 4: + lower = &g_t4_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T5 + case 5: + lower = &g_t5_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T6 + case 6: + lower = &g_t6_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T7 + case 7: + lower = &g_t7_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T8 + case 8: + lower = &g_t8_lowerhalf; + break; +#endif +#ifdef CONFIG_PIC32MZ_T9 + case 9: + lower = &g_t9_lowerhalf; + break; +#endif + default: + return -ENODEV; + } + + /* Initialize the elements of lower half state structure */ + + lower->started = false; + lower->callback = NULL; + lower->timer = pic32mz_timer_init(timer); + + if (lower->timer == NULL) + { + tmrerr("ERROR: Failed to init timer %d.\n", timer); + + return -EINVAL; + } + + lower->freq = PIC32MZ_TIMER_GETFREQ(lower->timer); + lower->width = PIC32MZ_TIMER_GETWIDTH(lower->timer); + lower->maxticks = ((1ull << lower->width) - 1ul); + + tmrinfo("Freq=%dHz / Width=%d-bit / Max ticks=%lu\n", + lower->freq, lower->width, lower->maxticks); + + /* Register the timer driver as /dev/timerX. The returned value from + * timer_register is a handle that could be used with timer_unregister(). + * REVISIT: The returned handle is discard here. + */ + + drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower); + + if (drvr == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the timer driver (such as if the + * 'devpath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + tmrerr("ERROR: Failed to register timer %s\n", devpath); + + return -EEXIST; + } + + tmrinfo("Timer registered successfuly\n"); + + return OK; +} + +#endif /* CONFIG_TIMER && CONFIG_PIC32MZ_TIMER */ diff --git a/arch/mips/src/pic32mz/pic32mz-timer.c b/arch/mips/src/pic32mz/pic32mz-timer.c new file mode 100644 index 00000000000..94dfc5b7fb0 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-timer.c @@ -0,0 +1,1254 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-timer.c + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip/pic32mz-timer.h" +#include "pic32mz-timer.h" +#include "pic32mz-gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This module is for the type B timers only. + * Type A (timer1) is used by the system. + */ + +#if defined(CONFIG_PIC32MZ_T2) || defined(CONFIG_PIC32MZ_T3) || \ + defined(CONFIG_PIC32MZ_T4) || defined(CONFIG_PIC32MZ_T5) || \ + defined(CONFIG_PIC32MZ_T6) || defined(CONFIG_PIC32MZ_T7) || \ + defined(CONFIG_PIC32MZ_T8) || defined(CONFIG_PIC32MZ_T9) + +/* Undef odd timers if mode32 is enabled in even timers. + * If mode32 is enabled the consecutive odd timers will be automatically + * enabled through menuconfig. + * This is an indication for the user that the odd timer is in use + * and to avoid a seperate, incorrect, utilization. + * Undef it here so its (useless in this case) structures won't be created + * later. + */ + +#ifdef CONFIG_PIC32MZ_T2_MODE32 +# undef CONFIG_PIC32MZ_T3 +#endif + +#ifdef CONFIG_PIC32MZ_T4_MODE32 +# undef CONFIG_PIC32MZ_T5 +#endif + +#ifdef CONFIG_PIC32MZ_T6_MODE32 +# undef CONFIG_PIC32MZ_T7 +#endif + +#ifdef CONFIG_PIC32MZ_T8_MODE32 +# undef CONFIG_PIC32MZ_T9 +#endif + +/* Prescale values */ + +#define PIC32MZ_TIMER_PRESCALE_1_1 0 +#define PIC32MZ_TIMER_PRESCALE_1_2 1 +#define PIC32MZ_TIMER_PRESCALE_1_4 2 +#define PIC32MZ_TIMER_PRESCALE_1_8 3 +#define PIC32MZ_TIMER_PRESCALE_1_16 4 +#define PIC32MZ_TIMER_PRESCALE_1_32 5 +#define PIC32MZ_TIMER_PRESCALE_1_64 6 +#define PIC32MZ_TIMER_PRESCALE_1_256 7 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Timer's hardware configuration */ + +struct pic32mz_timer_config_s +{ + uint32_t base; /* Timer's base address */ + uint32_t irq; /* Timer's event irq */ + bool stopinidle; /* True: stop in idle */ + bool gated; /* True: enable gated mode */ + uint8_t prescale; /* Timer's prescale value */ + bool mode32; /* True: enable mode 32bit */ + bool extclock; /* True: use external clock */ + uint32_t tckreg; /* Timer's clock PPS register */ + uint8_t tckpps; /* Timer's PPS value */ + uint32_t tckpin; /* GPIO config for the input */ +}; + +/* Timer's Device Structure */ + +struct pic32mz_timer_priv_s +{ + const struct pic32mz_timer_ops_s *ops; + struct pic32mz_timer_config_s *config; + bool inuse; +}; + +/**************************************************************************** + * Private Function prototypes + ****************************************************************************/ + +/* Helpers */ + +static inline uint32_t pic32mz_getreg(FAR struct pic32mz_timer_dev_s *dev, + uint16_t offset); +static inline void pic32mz_putreg(FAR struct pic32mz_timer_dev_s *dev, + uint16_t offset, uint32_t value); +static inline bool pic32mz_timer_mode32(FAR struct pic32mz_timer_dev_s *dev); +static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset); +static inline uint32_t pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev); + +static void pic32mz_timer_stopinidle(FAR struct pic32mz_timer_dev_s *dev, + bool stop); +static void pic32mz_timer_enablegate(FAR struct pic32mz_timer_dev_s *dev, + bool enable); +static void pic32mz_timer_setprescale(FAR struct pic32mz_timer_dev_s *dev, + uint8_t prescale); +static void pic32mz_timer_setmode32(FAR struct pic32mz_timer_dev_s *dev, + bool enable); +static void pic32mz_timer_extclocksource(FAR struct pic32mz_timer_dev_s *dev, + bool enable); +static void pic32mz_timer_inithardware(FAR struct pic32mz_timer_dev_s *dev); + +/* Timer's methods */ + +static void pic32mz_timer_start(FAR struct pic32mz_timer_dev_s *dev); +static void pic32mz_timer_stop(FAR struct pic32mz_timer_dev_s *dev); +static void pic32mz_timer_setperiod(FAR struct pic32mz_timer_dev_s *dev, + uint32_t period); +static uint32_t pic32mz_timer_getcounter(FAR struct pic32mz_timer_dev_s *dev); +static void pic32mz_timer_setcounter(FAR struct pic32mz_timer_dev_s *dev, + uint32_t count); +static uint32_t pic32mz_timer_getfreq(FAR struct pic32mz_timer_dev_s *dev); +static bool pic32mz_timer_setfreq(FAR struct pic32mz_timer_dev_s *dev, + uint32_t freq); +static uint8_t pic32mz_timer_getwidth(FAR struct pic32mz_timer_dev_s *dev); + +static int pic32mz_timer_setisr(FAR struct pic32mz_timer_dev_s *dev, + xcpt_t handler, void *arg); +static void pic32mz_timer_ackint(FAR struct pic32mz_timer_dev_s *dev); +static bool pic32mz_timer_checkint(FAR struct pic32mz_timer_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct pic32mz_timer_ops_s pic32mz_timer_ops = +{ + .start = pic32mz_timer_start, + .stop = pic32mz_timer_stop, + .setperiod = pic32mz_timer_setperiod, + .getcounter = pic32mz_timer_getcounter, + .setcounter = pic32mz_timer_setcounter, + .getfreq = pic32mz_timer_getfreq, + .setfreq = pic32mz_timer_setfreq, + .getwidth = pic32mz_timer_getwidth, + + .setisr = pic32mz_timer_setisr, + .ackint = pic32mz_timer_ackint, + .checkint = pic32mz_timer_checkint, +}; + +#ifdef CONFIG_PIC32MZ_T2 +static struct pic32mz_timer_config_s pic32mz_timer_t2_config = +{ + .base = PIC32MZ_TIMER2_K1BASE, + .irq = PIC32MZ_IRQ_T2, +#ifdef CONFIG_PIC32MZ_T2_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T2_GATED + .gated = true, + .tckreg = PIC32MZ_T2CKR, + .tckpps = BOARD_T2CK_PPS, + .tckpin = GPIO_T2CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T2_PRESCALE, +#ifdef CONFIG_PIC32MZ_T2_MODE32 + .mode32 = true, +#else + .mode32 = false, +#endif +#ifdef CONFIG_PIC32MZ_T2_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T2CKR, + .tckpps = BOARD_T2CK_PPS, + .tckpin = GPIO_T2CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t2_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t2_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T3 +static struct pic32mz_timer_config_s pic32mz_timer_t3_config = +{ + .base = PIC32MZ_TIMER3_K1BASE, + .irq = PIC32MZ_IRQ_T3, +#ifdef CONFIG_PIC32MZ_T3_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T3_GATED + .gated = true, + .tckreg = PIC32MZ_T3CKR, + .tckpps = BOARD_T3CK_PPS, + .tckpin = GPIO_T3CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T3_PRESCALE, + .mode32 = false, +#ifdef CONFIG_PIC32MZ_T3_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T3CKR, + .tckpps = BOARD_T3CK_PPS, + .tckpin = GPIO_T3CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t3_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t3_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T4 +static struct pic32mz_timer_config_s pic32mz_timer_t4_config = +{ + .base = PIC32MZ_TIMER4_K1BASE, + .irq = PIC32MZ_IRQ_T4, +#ifdef CONFIG_PIC32MZ_T4_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T4_GATED + .gated = true, + .tckreg = PIC32MZ_T4CKR, + .tckpps = BOARD_T4CK_PPS, + .tckpin = GPIO_T4CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T4_PRESCALE, +#ifdef CONFIG_PIC32MZ_T4_MODE32 + .mode32 = true, +#else + .mode32 = false, +#endif +#ifdef CONFIG_PIC32MZ_T4_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T4CKR, + .tckpps = BOARD_T4CK_PPS, + .tckpin = GPIO_T4CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t4_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t4_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T5 +static struct pic32mz_timer_config_s pic32mz_timer_t5_config = +{ + .base = PIC32MZ_TIMER5_K1BASE, + .irq = PIC32MZ_IRQ_T5, +#ifdef CONFIG_PIC32MZ_T5_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T5_GATED + .gated = true, + .tckreg = PIC32MZ_T5CKR, + .tckpps = BOARD_T5CK_PPS, + .tckpin = GPIO_T5CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T5_PRESCALE, + .mode32 = false, +#ifdef CONFIG_PIC32MZ_T5_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T5CKR, + .tckpps = BOARD_T5CK_PPS, + .tckpin = GPIO_T5CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t5_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t5_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T6 +static struct pic32mz_timer_config_s pic32mz_timer_t6_config = +{ + .base = PIC32MZ_TIMER6_K1BASE, + .irq = PIC32MZ_IRQ_T6, +#ifdef CONFIG_PIC32MZ_T6_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T6_GATED + .gated = true, + .tckreg = PIC32MZ_T6CKR, + .tckpps = BOARD_T6CK_PPS, + .tckpin = GPIO_T6CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T6_PRESCALE, +#ifdef CONFIG_PIC32MZ_T6_MODE32 + .mode32 = true, +#else + .mode32 = false, +#endif +#ifdef CONFIG_PIC32MZ_T6_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T6CKR, + .tckpps = BOARD_T6CK_PPS, + .tckpin = GPIO_T6CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t6_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t6_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T7 +static struct pic32mz_timer_config_s pic32mz_timer_t7_config = +{ + .base = PIC32MZ_TIMER7_K1BASE, + .irq = PIC32MZ_IRQ_T7, +#ifdef CONFIG_PIC32MZ_T7_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T7_GATED + .gated = true, + .tckreg = PIC32MZ_T7CKR, + .tckpps = BOARD_T7CK_PPS, + .tckpin = GPIO_T7CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T7_PRESCALE, + .mode32 = false, +#ifdef CONFIG_PIC32MZ_T7_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T7CKR, + .tckpps = BOARD_T7CK_PPS, + .tckpin = GPIO_T7CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t7_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t7_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T8 +static struct pic32mz_timer_config_s pic32mz_timer_t8_config = +{ + .base = PIC32MZ_TIMER8_K1BASE, + .irq = PIC32MZ_IRQ_T8, +#ifdef CONFIG_PIC32MZ_T8_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T8_GATED + .gated = true, + .tckreg = PIC32MZ_T8CKR, + .tckpps = BOARD_T8CK_PPS, + .tckpin = GPIO_T8CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T8_PRESCALE, +#ifdef CONFIG_PIC32MZ_T8_MODE32 + .mode32 = true, +#else + .mode32 = false, +#endif +#ifdef CONFIG_PIC32MZ_T8_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T8CKR, + .tckpps = BOARD_T8CK_PPS, + .tckpin = GPIO_T8CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t8_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t8_config, + .inuse = false, +}; +#endif + +#ifdef CONFIG_PIC32MZ_T9 +static struct pic32mz_timer_config_s pic32mz_timer_t9_config = +{ + .base = PIC32MZ_TIMER9_K1BASE, + .irq = PIC32MZ_IRQ_T9, +#ifdef CONFIG_PIC32MZ_T9_STOPINIDLE + .stopinidle = true, +#else + .stopinidle = false, +#endif +#ifdef CONFIG_PIC32MZ_T9_GATED + .gated = true, + .tckreg = PIC32MZ_T9CKR, + .tckpps = BOARD_T9CK_PPS, + .tckpin = GPIO_T9CK, +#else + .gated = false, +#endif + .prescale = CONFIG_PIC32MZ_T9_PRESCALE, + .mode32 = false, +#ifdef CONFIG_PIC32MZ_T9_EXTERNALCLOCK + .extclock = true, + .tckreg = PIC32MZ_T9CKR, + .tckpps = BOARD_T9CK_PPS, + .tckpin = GPIO_T9CK, +#else + .extclock = false, +#endif +}; + +static struct pic32mz_timer_priv_s pic32mz_t9_priv = +{ + .ops = &pic32mz_timer_ops, + .config = &pic32mz_timer_t9_config, + .inuse = false, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t pic32mz_getreg(FAR struct pic32mz_timer_dev_s *dev, + uint16_t offset) +{ + FAR struct pic32mz_timer_priv_s *priv = + (FAR struct pic32mz_timer_priv_s *)dev; + + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: pic32mz_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void pic32mz_putreg(FAR struct pic32mz_timer_dev_s *dev, + uint16_t offset, uint32_t value) +{ + FAR struct pic32mz_timer_priv_s *priv = + (FAR struct pic32mz_timer_priv_s *)dev; + + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: pic32mz_timer_mode32 + * + * Description: + * Returns true if the 32 mode is enabled + * + ****************************************************************************/ + +static inline bool pic32mz_timer_mode32(FAR struct pic32mz_timer_dev_s *dev) +{ + return ((FAR struct pic32mz_timer_priv_s *)dev)->config->mode32; +} + +/**************************************************************************** + * Name: pic32mz_timer_oddoffset + * + * Description: + * Returns the offset of the consecutive odd timer + * + ****************************************************************************/ + +static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset) +{ + /* To access the consecutive odd timer the base needs te be changed. + * PIC32MZ_TIMERn_OFFSET(1) represents the offset between timers' base. + * An even timer's base + PIC32MZ_TIMERn_OFFSET(1) gives the base of + * the next odd timer. + * This wil allow the access of the odd timer from the dev of its + * previous even timer. + */ + + return PIC32MZ_TIMERn_OFFSET(1) + evenoffset; +} + +/**************************************************************************** + * Name: pic32mz_timer_nextirq + * + * Description: + * Returns the irq of the consecutive odd numbered timer + * + ****************************************************************************/ + +static inline uint32_t pic32mz_timer_nextirq(FAR struct pic32mz_timer_dev_s *dev) +{ + uint32_t irq; + + irq = ((FAR struct pic32mz_timer_priv_s *)dev)->config->irq; + + /* The irq offsets between odd and even timers + * are not always the same. + */ + + if (irq == PIC32MZ_IRQ_T2 || irq == PIC32MZ_IRQ_T4) + { + return irq + 5; + } + else + { + return irq + 4; + } +} + +/**************************************************************************** + * Name: pic32mz_timer_start + * + * Description: + * Start the timer by setting its ON bit + * + ****************************************************************************/ + +static void pic32mz_timer_start(FAR struct pic32mz_timer_dev_s *dev) +{ + pic32mz_putreg(dev, PIC32MZ_TIMER_CONSET_OFFSET, TIMER_CON_ON); +} + +/**************************************************************************** + * Name: pic32mz_timer_stop + * + * Description: + * Stop the timer by clearing the ON bit + * + ****************************************************************************/ + +static void pic32mz_timer_stop(FAR struct pic32mz_timer_dev_s *dev) +{ + pic32mz_putreg(dev, PIC32MZ_TIMER_CONCLR_OFFSET, TIMER_CON_ON); +} + +/**************************************************************************** + * Name: pic32mz_timer_stopinidle + * + * Description: + * Stop the timer in idle mode + * + ****************************************************************************/ + +static void pic32mz_timer_stopinidle(FAR struct pic32mz_timer_dev_s *dev, + bool stop) +{ + if (stop) + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONSET_OFFSET, TIMER_CON_SIDL); + } + else + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONCLR_OFFSET, TIMER_CON_SIDL); + + /* In 32bit mode, this bit should be cleared + * for the odd timer as well. + */ + + if (pic32mz_timer_mode32(dev)) + { + pic32mz_putreg(dev, + pic32mz_timer_oddoffset(PIC32MZ_TIMER_CONCLR_OFFSET), + TIMER_CON_SIDL); + } + } + + ((FAR struct pic32mz_timer_priv_s *)dev)->config->stopinidle = stop; +} + +/**************************************************************************** + * Name: pic32mz_timer_enablegate + * + * Description: + * Enabled gated time accumulation. + * This has no effect when external clock source is enabled + * + ****************************************************************************/ + +static void pic32mz_timer_enablegate(FAR struct pic32mz_timer_dev_s *dev, + bool enable) +{ + FAR struct pic32mz_timer_priv_s *priv = + (FAR struct pic32mz_timer_priv_s *)dev; + + if (enable) + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONSET_OFFSET, TIMER_CON_TGATE); + + /* Configure the TxCK input pin */ + + putreg32(priv->config->tckpps, priv->config->tckreg); + pic32mz_configgpio(priv->config->tckpin); + } + else + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONCLR_OFFSET, TIMER_CON_TGATE); + } + + priv->config->gated = enable; +} + +/**************************************************************************** + * Name: pic32mz_timer_setprescale + * + * Description: + * Set the timer's prescaler. + * + ****************************************************************************/ + +static void pic32mz_timer_setprescale(FAR struct pic32mz_timer_dev_s *dev, + uint8_t prescale) +{ + pic32mz_putreg(dev, PIC32MZ_TIMER_CONSET_OFFSET, + (prescale << TIMER_CON_TCKPS_SHIFT)); + + ((FAR struct pic32mz_timer_priv_s *)dev)->config->prescale = prescale; +} + +/**************************************************************************** + * Name: pic32mz_timer_setmode32 + * + * Description: + * Set the timer's mode. + * Two 16-bit timers can form a 32-bit timer. + * + ****************************************************************************/ + +static void pic32mz_timer_setmode32(FAR struct pic32mz_timer_dev_s *dev, + bool enable) +{ + /* Only even timers have the TIMER_CON_T32 bit. */ + + if (enable) + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONSET_OFFSET, TIMER_CON_T32); + } + else + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONCLR_OFFSET, TIMER_CON_T32); + } + + ((FAR struct pic32mz_timer_priv_s *)dev)->config->mode32 = enable; +} + +/**************************************************************************** + * Name: pic32mz_timer_extclocksource + * + * Description: + * Set the timer's clock source + * + ****************************************************************************/ + +static void pic32mz_timer_extclocksource(FAR struct pic32mz_timer_dev_s *dev, + bool enable) +{ + FAR struct pic32mz_timer_priv_s *priv = + (FAR truct pic32mz_timer_priv_s *)dev; + + if (enable) + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONSET_OFFSET, TIMER_CON_TCS); + + /* Configure the TxCK input pin */ + + putreg32(priv->config->tckpps, priv->config->tckreg); + pic32mz_configgpio(priv->config->tckpin); + } + else + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CONCLR_OFFSET, TIMER_CON_TCS); + } + + priv->config->extclock = enable; +} + +/**************************************************************************** + * Name: pic32mz_timer_inithardware + * + * Description: + * Initializes the timer's hardware + * This function is only called when the timer is first initialized. + * It uses the provided configuration. + * + ****************************************************************************/ + +static void pic32mz_timer_inithardware(FAR struct pic32mz_timer_dev_s *dev) +{ + FAR struct pic32mz_timer_priv_s *priv = + (FAR struct pic32mz_timer_priv_s *)dev; + + /* Initialize the hardware using the startup configuration. + * + * Set idle mode operations. + */ + + pic32mz_timer_stopinidle(dev, priv->config->stopinidle); + + /* Enable gated time accumulation if chosen. + * This operation is ignored if an external clock is used. + */ + + pic32mz_timer_enablegate(dev, priv->config->gated); + + /* Set the input clock prescale + */ + + pic32mz_timer_setprescale(dev, priv->config->prescale); + + /* Set the timer's mode (16 or 32bits) + * This bit only exists for type B even numbered timers (Timer 2, 4, 6, 8) + */ + + pic32mz_timer_setmode32(dev, priv->config->mode32); + + /* Set the clock source. + * If an external clock source is used, the timer is driven from TxCK pin. + */ + + pic32mz_timer_extclocksource(dev, priv->config->extclock); +} + +/**************************************************************************** + * Name: pic32mz_timer_setperiod + * + * Description: + * Set the PRx register + * + ****************************************************************************/ + +static void pic32mz_timer_setperiod(FAR struct pic32mz_timer_dev_s *dev, + uint32_t period) +{ + /* In 32bit mode: + * - even timers represent the least significant half words. + * - odd timers represent the most significant half words. + */ + + if (pic32mz_timer_mode32(dev)) + { + pic32mz_putreg(dev, PIC32MZ_TIMER_PR_OFFSET, period & 0x00000FFFF); + + pic32mz_putreg(dev, pic32mz_timer_oddoffset(PIC32MZ_TIMER_PR_OFFSET), + (period >> 16) & 0x00000FFFF); + } + else + { + pic32mz_putreg(dev, PIC32MZ_TIMER_PR_OFFSET, period); + } +} + +/**************************************************************************** + * Name: pic32mz_timer_getcounter + * + * Description: + * Return the TMRx register + * + ****************************************************************************/ + +static uint32_t pic32mz_timer_getcounter(FAR struct pic32mz_timer_dev_s *dev) +{ + /* In 32bit mode: + * - even timers represent the least significant half words. + * - odd timers represent the most significant half words. + */ + + if (pic32mz_timer_mode32(dev)) + { + uint16_t lsw; + uint16_t msw; + + lsw = pic32mz_getreg(dev, PIC32MZ_TIMER_CNT_OFFSET); + + msw = pic32mz_getreg(dev, + pic32mz_timer_oddoffset(PIC32MZ_TIMER_CNT_OFFSET)); + + return lsw | (msw << 16); + } + else + { + return pic32mz_getreg(dev, PIC32MZ_TIMER_CNT_OFFSET); + } + +} + +/**************************************************************************** + * Name: pic32mz_timer_setcounter + * + * Description: + * Set the TMRx register + * + ****************************************************************************/ + +static void pic32mz_timer_setcounter(FAR struct pic32mz_timer_dev_s *dev, + uint32_t count) +{ + /* In 32bit mode: + * - even timers represent the least significant half words. + * - odd timers represent the most significant half words. + */ + + if (pic32mz_timer_mode32(dev)) + { + + pic32mz_putreg(dev, PIC32MZ_TIMER_CNT_OFFSET, count & 0x00000FFFF); + + pic32mz_putreg(dev, pic32mz_timer_oddoffset(PIC32MZ_TIMER_CNT_OFFSET), + (count >> 16) & 0x00000FFFF); + } + else + { + pic32mz_putreg(dev, PIC32MZ_TIMER_CNT_OFFSET, count); + } +} + +/**************************************************************************** + * Name: pic32mz_timer_getfreq + * + * Description: + * Returns the frequency of the timer in Hz + * + ****************************************************************************/ + +static uint32_t pic32mz_timer_getfreq(FAR struct pic32mz_timer_dev_s *dev) +{ + uint8_t prescale; + uint32_t freq; + + prescale = ((FAR structpic32mz_timer_priv_s *)dev)->config->prescale; + + /* The prescale values are not a continuous power of 2. + * There is a gap between 64 and 256 (the 128 is skipped). + */ + + if (prescale == PIC32MZ_TIMER_PRESCALE_1_256) + { + freq = BOARD_PBCLK3 / (1 << (prescale + 1)); + } + else + { + freq = BOARD_PBCLK3 / (1 << prescale); + } + + return freq; +} + +/**************************************************************************** + * Name: pic32mz_timer_setfreq + * + * Description: + * Sets the frequency of the timer in Hz + * + ****************************************************************************/ + +static bool pic32mz_timer_setfreq(FAR struct pic32mz_timer_dev_s *dev, + uint32_t freq) +{ + uint16_t prescale; + uint32_t tmrfreq; + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + tmrwarn("Frequency=%luHz not valid", freq); + pic32mz_timer_stop(dev); + + return 0; + } + + prescale = BOARD_PBCLK3 / freq; + + tmrinfo("Prescale value calculated %d\n", prescale); + + if (prescale >= 1 && prescale < 2) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_1); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_1))); + } + else if (prescale >= 2 && prescale < 4) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_2); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_2))); + } + else if (prescale >= 4 && prescale < 8) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_4); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_4))); + } + else if (prescale >= 8 && prescale < 16) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_8); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_8))); + } + else if (prescale >= 16 && prescale < 32) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_16); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_16))); + } + else if (prescale >= 32 && prescale < 64) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_32); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_32))); + } + else if (prescale >= 64 && prescale < 256) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_64); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_64))); + } + else if (prescale >= 256) + { + pic32mz_timer_setprescale(dev, PIC32MZ_TIMER_PRESCALE_1_256); + tmrinfo("Prescale value chosen %d\n", + (1 << (PIC32MZ_TIMER_PRESCALE_1_256 + 1))); + } + else + { + tmrerr("The frequency of %luHz cannot be set.\n", freq); + return false; + } + + tmrfreq = pic32mz_timer_getfreq(dev); + + tmrinfo("Timer's frequency set to %luHz\n", tmrfreq); + + return true; +} + +/**************************************************************************** + * Name: pic32mz_timer_getwidth + * + * Description: + * Returns the timer's width + * + ****************************************************************************/ + +static uint8_t pic32mz_timer_getwidth(FAR struct pic32mz_timer_dev_s *dev) +{ + return pic32mz_timer_mode32(dev) ? 32 : 16; +} + +/**************************************************************************** + * Name: pic32mz_timer_setisr + * + * Description: + * Set the timer's ISR + * + ****************************************************************************/ + +static int pic32mz_timer_setisr(FAR struct pic32mz_timer_dev_s *dev, + xcpt_t handler, FAR void *arg) +{ + FAR struct pic32mz_timer_priv_s *priv = + (FAR struct pic32mz_timer_priv_s *)dev; + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + if (pic32mz_timer_mode32(dev)) + { + /* In 32bit mode, the consecutive odd timer controls + * the interrupt. + */ + + up_disable_irq(pic32mz_timer_nextirq(dev)); + irq_detach(pic32mz_timer_nextirq(dev)); + } + else + { + up_disable_irq(priv->config->irq); + irq_detach(priv->config->irq); + } + } + + /* Otherwise set callback and enable interrupt */ + + else + { + if (pic32mz_timer_mode32(dev)) + { + /* In 32bit mode, the consecutive odd timer controls + * the interrupt. + */ + + irq_attach(pic32mz_timer_nextirq(dev), handler, arg); + up_enable_irq(pic32mz_timer_nextirq(dev)); + } + else + { + irq_attach(priv->config->irq, handler, arg); + up_enable_irq(priv->config->irq); + } + } + + return OK; +} + +/**************************************************************************** + * Name: pic32mz_timer_ackint + * + * Description: + * Acknowledge the timer's interrupt + * + ****************************************************************************/ + +static void pic32mz_timer_ackint(FAR struct pic32mz_timer_dev_s *dev) +{ + up_clrpend_irq(((FAR structpic32mz_timer_priv_s *)dev)->config->irq); + + if (pic32mz_timer_mode32(dev)) + { + /* In 32bit mode, the consecutive odd timer controls the interrupt. */ + + up_clrpend_irq(pic32mz_timer_nextirq(dev)); + } +} + +/**************************************************************************** + * Name: pic32mz_timer_checkint + * + * Description: + * Check if the timer's interrupt is pending + * + ****************************************************************************/ + +static bool pic32mz_timer_checkint(FAR struct pic32mz_timer_dev_s *dev) +{ + if (pic32mz_timer_mode32(dev)) + { + /* In 32bit mode, the consecutive odd timer controls the interrupt. */ + + return up_pending_irq(pic32mz_timer_nextirq(dev)); + } + else + { + return up_pending_irq(((FAR structpic32mz_timer_priv_s *)dev)->config->irq); + } +} + +/**************************************************************************** + * Pubic Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_timer_init + ****************************************************************************/ + +FAR struct pic32mz_timer_dev_s *pic32mz_timer_init(int timer) +{ + struct pic32mz_timer_dev_s *dev = NULL; + + switch (timer) + { +#ifdef CONFIG_PIC32MZ_T2 + case 2: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t2_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T3 + case 3: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t3_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T4 + case 4: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t4_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T5 + case 5: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t5_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T6 + case 6: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t6_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T7 + case 7: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t7_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T8 + case 8: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t8_priv; + break; +#endif +#ifdef CONFIG_PIC32MZ_T9 + case 9: + dev = (FAR structpic32mz_timer_dev_s *)&pic32mz_t9_priv; + break; +#endif + default: + return NULL; + } + + if (((FAR structpic32mz_timer_priv_s *)dev)->inuse) + { + return NULL; + } + else + { + /* Init the timer's hardware (prescale, clock source, ..) */ + + pic32mz_timer_inithardware(dev); + + ((FAR structpic32mz_timer_priv_s *)dev)->inuse = true; + + return dev; + } +} + +int pic32mz_timer_deinit(FAR struct pic32mz_timer_dev_s *dev) +{ + /* Stop the timer in case it was still running + * and mark it as unused. + */ + + pic32mz_timer_stop(dev); + ((FAR structpic32mz_timer_priv_s *)dev)->inuse = false; + + return OK; +} + +#endif /* defined(CONFIG_PIC32MZ_T2 || ... || T9) */ diff --git a/arch/mips/src/pic32mz/pic32mz-timer.h b/arch/mips/src/pic32mz/pic32mz-timer.h new file mode 100644 index 00000000000..ddb4604b959 --- /dev/null +++ b/arch/mips/src/pic32mz/pic32mz-timer.h @@ -0,0 +1,167 @@ +/**************************************************************************** + * arch/mips/src/pic32mz/chip/pic32mz-timer.h + * + * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. + * Author: Abdelatif Guettouche + * + * This file is a part of NuttX: + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H +#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define PIC32MZ_TIMER_START(d) ((d)->ops->start(d)) +#define PIC32MZ_TIMER_STOP(d) ((d)->ops->stop(d)) +#define PIC32MZ_TIMER_SETPERIOD(d,p) ((d)->ops->setperiod(d,p)) +#define PIC32MZ_TIMER_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define PIC32MZ_TIMER_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) +#define PIC32MZ_TIMER_GETFREQ(d) ((d)->ops->getfreq(d)) +#define PIC32MZ_TIMER_SETFREQ(d,f) ((d)->ops->setfreq(d,f)) +#define PIC32MZ_TIMER_GETWIDTH(d) ((d)->ops->getwidth(d)) + +#define PIC32MZ_TIMER_SETISR(d,hnd,arg) ((d)->ops->setisr(d,hnd,arg)) +#define PIC32MZ_TIMER_ACKINT(d) ((d)->ops->ackint(d)) +#define PIC32MZ_TIMER_CHECKINT(d) ((d)->ops->checkint(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Timer's Operations */ + +struct pic32mz_timer_dev_s; /* Forward reference */ +struct pic32mz_timer_ops_s +{ + /* Timer's methods */ + + void (*start)(FAR struct pic32mz_timer_dev_s *dev); + void (*stop)(FAR struct pic32mz_timer_dev_s *dev); + void (*setperiod)(FAR struct pic32mz_timer_dev_s *dev, uint32_t p); + uint32_t (*getcounter)(FAR struct pic32mz_timer_dev_s *dev); + void (*setcounter)(FAR struct pic32mz_timer_dev_s *dev, uint32_t c); + uint32_t (*getfreq)(FAR struct pic32mz_timer_dev_s *dev); + bool (*setfreq)(FAR struct pic32mz_timer_dev_s *dev, uint32_t freq); + uint8_t (*getwidth)(FAR struct pic32mz_timer_dev_s *dev); + + /* Timer's interrupts */ + + int (*setisr)(FAR struct pic32mz_timer_dev_s *dev, xcpt_t handler, + void * arg); + void (*ackint)(FAR struct pic32mz_timer_dev_s *dev); + bool (*checkint)(FAR struct pic32mz_timer_dev_s *dev); +}; + +/* Timer's Device Structure */ + +struct pic32mz_timer_dev_s +{ + FAR struct pic32mz_timer_ops_s *ops; +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pic32mz_timer_init + * + * Description: + * Power-up the timer and get its structure. + * + ****************************************************************************/ + +FAR struct pic32mz_timer_dev_s *pic32mz_timer_init(int timer); + +/**************************************************************************** + * Name: pic32mz_timer_deinit + * + * Description: + * Power-down the timer and mark it as unused. + * + ****************************************************************************/ + +int pic32mz_timer_deinit(FAR struct pic32mz_timer_dev_s *dev); + +/**************************************************************************** + * Name: pic32mz_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath The full path to the timer device. + * This should be of the form /dev/timer0 + * timer The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int pic32mz_timer_initialize(FAR const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_TIMER_H */