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SAM3X/Arduino Due: Fix typo in sam3x_periphclks.h; add SCLK definitions to board.h header file. From Fabien Comte

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This commit is contained in:
Gregory Nutt
2014-09-08 06:14:59 -06:00
parent 8b64dc003e
commit 068115e7d6
5 changed files with 8 additions and 8 deletions
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arch/arm/src/sam34/sam3x_periphclks.h
+2 -2
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@@ -52,8 +52,8 @@
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) #define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) #define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) #define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC) #define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC)
#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC) #define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC)
arch/arm/src/sam34/sam_rtt.c
+1 -1
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@@ -67,7 +67,7 @@
# define RTT_PRES 1 # define RTT_PRES 1
#endif #endif
#define RTT_FCLK (BOARD_SLCK_FREQUENCY/RTT_PRES) #define RTT_FCLK (BOARD_SCLK_FREQUENCY/RTT_PRES)
#define RTT_MAXTIMEOUT ((1000000ULL * (0x100000000ULL)) / RTT_FCLK) #define RTT_MAXTIMEOUT ((1000000ULL * (0x100000000ULL)) / RTT_FCLK)
/* Configuration ************************************************************/ /* Configuration ************************************************************/
arch/arm/src/sam34/sam_tc.c
+1 -1
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@@ -66,7 +66,7 @@
/* TODO: Allow selection of any of the input clocks */ /* TODO: Allow selection of any of the input clocks */
#define TC_FCLK (BOARD_SLCK_FREQUENCY) #define TC_FCLK (BOARD_SCLK_FREQUENCY)
#define TC_MAXTIMEOUT ((1000000ULL * (1ULL + TC_RVALUE_MASK)) / TC_FCLK) #define TC_MAXTIMEOUT ((1000000ULL * (1ULL + TC_RVALUE_MASK)) / TC_FCLK)
/* Configuration ************************************************************/ /* Configuration ************************************************************/
arch/arm/src/sam34/sam_wdt.c
+1 -1
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@@ -71,7 +71,7 @@
* 1000 * 64 / Fmin = 49.93 msec * 1000 * 64 / Fmin = 49.93 msec
*/ */
#define WDT_FCLK (BOARD_SLCK_FREQUENCY / 128) #define WDT_FCLK (BOARD_SCLK_FREQUENCY / 128)
#define WDT_MAXTIMEOUT ((1000 * (WDT_MR_WDV_MAX+1)) / WDT_FCLK) #define WDT_MAXTIMEOUT ((1000 * (WDT_MR_WDV_MAX+1)) / WDT_FCLK)
/* Configuration ************************************************************/ /* Configuration ************************************************************/
arch/arm/src/sama5/sam_wdt.c
+3 -3
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@@ -61,11 +61,11 @@
* 32768 kHz). * 32768 kHz).
*/ */
#ifndef BOARD_SLCK_FREQUENCY #ifndef BOARD_SCLK_FREQUENCY
# define BOARD_SLCK_FREQUENCY 32768 # define BOARD_SCLK_FREQUENCY 32768
#endif #endif
#define WDT_FREQUENCY (BOARD_SLCK_FREQUENCY / 128) #define WDT_FREQUENCY (BOARD_SCLK_FREQUENCY / 128)
/* At 32768Hz, the maximum timeout value will be: /* At 32768Hz, the maximum timeout value will be:
* *