xtensa/esp32s2: Add driver for I2C peripheral in Master mode

Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>

arch/xtensa/src/esp32s2/Kconfig

@@ -15,6 +15,7 @@ config ARCH_CHIP_ESP32S2WROVER
 	bool "ESP32-S2-WROVER"
 	select ESP32S2_FLASH_4M
 	select ESP32S2_PSRAM_2M
+	select ARCH_HAVE_I2CRESET
 	---help---
 		Generic module with an embedded ESP32-S2
 
@@ -232,6 +233,10 @@ config ESP32S2_UART
 	bool
 	default n
 
+config ESP32S2_I2C
+	bool
+	default n
+
 config ESP32S2_TIMER
 	bool
 	default n
@@ -320,6 +325,18 @@ config ESP32S2_UART1
 	select UART1_SERIALDRIVER
 	select ARCH_HAVE_SERIAL_TERMIOS
 
+config ESP32S2_I2C0
+	bool "I2C 0"
+	default n
+	select ESP32S2_I2C
+	select I2C
+
+config ESP32S2_I2C1
+	bool "I2C 1"
+	default n
+	select ESP32S2_I2C
+	select I2C
+
 config ESP32S2_RT_TIMER
 	bool "Real-time Timer"
 	select ESP32S2_TIMER
@@ -401,6 +418,47 @@ endif # ESP32S2_UART1
 
 endmenu # UART Configuration
 
+menu "I2C Configuration"
+	depends on ESP32S2_I2C
+
+if ESP32S2_I2C0
+
+config ESP32S2_I2C0_SCLPIN
+	int "I2C0 SCL Pin"
+	default 19
+	range 0 46
+
+config ESP32S2_I2C0_SDAPIN
+	int "I2C0 SDA Pin"
+	default 18
+	range 0 46
+
+endif # ESP32S2_I2C0
+
+if ESP32S2_I2C1
+
+config ESP32S2_I2C1_SCLPIN
+	int "I2C1 SCL Pin"
+	default 6
+	range 0 46
+
+config ESP32S2_I2C1_SDAPIN
+	int "I2C1 SDA Pin"
+	default 7
+	range 0 46
+
+endif # ESP32S2_I2C1
+
+config ESP32S2_I2CTIMEOSEC
+	int "Timeout seconds"
+	default 0
+
+config ESP32S2_I2CTIMEOMS
+	int "Timeout milliseconds"
+	default 500
+
+endmenu # I2C Configuration
+
 menu "SPI Flash Configuration"
 	depends on ESP32S2_SPIFLASH
 

arch/xtensa/src/esp32s2/Make.defs

@@ -84,6 +84,10 @@ ifeq ($(CONFIG_ESP32S2_RNG),y)
 CHIP_CSRCS += esp32s2_rng.c
 endif
 
+ifeq ($(CONFIG_ESP32S2_I2C),y)
+CHIP_CSRCS += esp32s2_i2c.c
+endif
+
 ifeq ($(CONFIG_ESP32S2_TIMER),y)
 CHIP_CSRCS += esp32s2_tim.c
 ifeq ($(CONFIG_TIMER),y)

arch/xtensa/src/esp32s2/esp32s2_i2c.h

@@ -0,0 +1,91 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s2/esp32s2_i2c.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_I2C_H
+#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_I2C_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/i2c/i2c_master.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ESP32S2_I2C0
+#  define ESP32S2_I2C0 0
+#endif
+
+#ifdef CONFIG_ESP32S2_I2C1
+#  define ESP32S2_I2C1 1
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s2_i2cbus_initialize
+ *
+ * Description:
+ *   Initialize the selected I2C port. And return a unique instance of struct
+ *   struct i2c_master_s.  This function may be called to obtain multiple
+ *   instances of the interface, each of which may be set up with a
+ *   different frequency and slave address.
+ *
+ * Input Parameters:
+ *   Port number (for hardware that has multiple I2C interfaces)
+ *
+ * Returned Value:
+ *   Valid I2C device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct i2c_master_s *esp32s2_i2cbus_initialize(int port);
+
+/****************************************************************************
+ * Name: esp32s2_i2cbus_uninitialize
+ *
+ * Description:
+ *   De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameters:
+ *   Device structure as returned by the esp32s2_i2cbus_initialize()
+ *
+ * Returned Value:
+ *   OK on success, ERROR when internal reference count mismatch or dev
+ *   points to invalid hardware device.
+ *
+ ****************************************************************************/
+
+int esp32s2_i2cbus_uninitialize(struct i2c_master_s *dev);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_I2C_H */

arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h

@@ -190,7 +190,7 @@
 
 /* Helper to place a value in a field */
 
-#define VALUE_TO_FIELD(_value, _field) ((_value << (_field##_S)) & (_field##_M))
+#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
 
 /* Periheral Clock */
 

arch/xtensa/src/esp32s2/hardware/esp32s2_system.h

@@ -80,9 +80,9 @@
  * This field is used to force on clock gate of internal SRAM.
  */
 
-#define SYSTEM_SRAM_FO    0x003FFFFF
+#define SYSTEM_SRAM_FO    0x003fffff
 #define SYSTEM_SRAM_FO_M  (SYSTEM_SRAM_FO_V << SYSTEM_SRAM_FO_S)
-#define SYSTEM_SRAM_FO_V  0x003FFFFF
+#define SYSTEM_SRAM_FO_V  0x003fffff
 #define SYSTEM_SRAM_FO_S  0
 
 /* SYSTEM_SRAM_CTRL_1_REG register
@@ -95,9 +95,9 @@
  * This field is used to power down internal SRAM.
  */
 
-#define SYSTEM_SRAM_FORCE_PD    0x003FFFFF
+#define SYSTEM_SRAM_FORCE_PD    0x003fffff
 #define SYSTEM_SRAM_FORCE_PD_M  (SYSTEM_SRAM_FORCE_PD_V << SYSTEM_SRAM_FORCE_PD_S)
-#define SYSTEM_SRAM_FORCE_PD_V  0x003FFFFF
+#define SYSTEM_SRAM_FORCE_PD_V  0x003fffff
 #define SYSTEM_SRAM_FORCE_PD_S  0
 
 /* SYSTEM_CPU_PERI_CLK_EN_REG register
@@ -135,16 +135,15 @@
  */
 
 #define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x18)
-#define DPORT_CPU_PER_CONF_REG  (DR_REG_SYSTEM_BASE + 0x018) /* old name */
 
 /* SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
  * Sets the number of delay cycles to enter CPU wait mode after a WAITI
  * instruction.
  */
 
-#define SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000F
+#define SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000f
 #define SYSTEM_CPU_WAITI_DELAY_NUM_M  (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S)
-#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000F
+#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000f
 #define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
 
 /* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
@@ -188,9 +187,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S  0
 
 /* SYSTEM_JTAG_CTRL_1_REG register
@@ -205,9 +204,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S  0
 
 /* SYSTEM_JTAG_CTRL_2_REG register
@@ -222,9 +221,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S  0
 
 /* SYSTEM_JTAG_CTRL_3_REG register
@@ -239,9 +238,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S  0
 
 /* SYSTEM_JTAG_CTRL_4_REG register
@@ -256,9 +255,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S  0
 
 /* SYSTEM_JTAG_CTRL_5_REG register
@@ -273,9 +272,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S  0
 
 /* SYSTEM_JTAG_CTRL_6_REG register
@@ -290,9 +289,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S  0
 
 /* SYSTEM_JTAG_CTRL_7_REG register
@@ -307,9 +306,9 @@
  * temporary disable of eFuse to JTAG.
  */
 
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7    0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7    0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M  (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)
-#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V  0xFFFFFFFF
+#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V  0xffffffff
 #define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S  0
 
 /* SYSTEM_MEM_PD_MASK_REG register
@@ -1043,12 +1042,12 @@
 #define SYSTEM_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x50)
 
 /* SYSTEM_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255;
- * This register is used to set the integer number of divider.
+ * This field is used to set the integer number of the divider value.
  */
 
-#define SYSTEM_LPCK_DIV_NUM    0x00000FFF
+#define SYSTEM_LPCK_DIV_NUM    0x00000fff
 #define SYSTEM_LPCK_DIV_NUM_M  (SYSTEM_LPCK_DIV_NUM_V << SYSTEM_LPCK_DIV_NUM_S)
-#define SYSTEM_LPCK_DIV_NUM_V  0x00000FFF
+#define SYSTEM_LPCK_DIV_NUM_V  0x00000fff
 #define SYSTEM_LPCK_DIV_NUM_S  0
 
 /* SYSTEM_BT_LPCK_DIV_FRAC_REG register
@@ -1313,18 +1312,18 @@
  * address.
  */
 
-#define SYSTEM_RTC_MEM_CRC_LEN    0x000007FF
+#define SYSTEM_RTC_MEM_CRC_LEN    0x000007ff
 #define SYSTEM_RTC_MEM_CRC_LEN_M  (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S)
-#define SYSTEM_RTC_MEM_CRC_LEN_V  0x000007FF
+#define SYSTEM_RTC_MEM_CRC_LEN_V  0x000007ff
 #define SYSTEM_RTC_MEM_CRC_LEN_S  20
 
 /* SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0;
  * This field is used to set address of RTC memory for CRC.
  */
 
-#define SYSTEM_RTC_MEM_CRC_ADDR    0x000007FF
+#define SYSTEM_RTC_MEM_CRC_ADDR    0x000007ff
 #define SYSTEM_RTC_MEM_CRC_ADDR_M  (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S)
-#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x000007FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x000007ff
 #define SYSTEM_RTC_MEM_CRC_ADDR_S  9
 
 /* SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0;
@@ -1346,9 +1345,9 @@
  * This field stores the CRC result of RTC memory.
  */
 
-#define SYSTEM_RTC_MEM_CRC_RES    0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES    0xffffffff
 #define SYSTEM_RTC_MEM_CRC_RES_M  (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S)
-#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_V  0xffffffff
 #define SYSTEM_RTC_MEM_CRC_RES_S  0
 
 /* SYSTEM_Redundant_ECO_Ctrl_REG register
@@ -1400,9 +1399,9 @@
  * This field is used to power up internal SRAM.
  */
 
-#define SYSTEM_SRAM_FORCE_PU    0x003FFFFF
+#define SYSTEM_SRAM_FORCE_PU    0x003fffff
 #define SYSTEM_SRAM_FORCE_PU_M  (SYSTEM_SRAM_FORCE_PU_V << SYSTEM_SRAM_FORCE_PU_S)
-#define SYSTEM_SRAM_FORCE_PU_V  0x003FFFFF
+#define SYSTEM_SRAM_FORCE_PU_V  0x003fffff
 #define SYSTEM_SRAM_FORCE_PU_S  0
 
 /* SYSTEM_SYSCLK_CONF_REG register
@@ -1424,9 +1423,9 @@
  * This field is used to read XTAL frequency in MHz.
  */
 
-#define SYSTEM_CLK_XTAL_FREQ    0x0000007F
+#define SYSTEM_CLK_XTAL_FREQ    0x0000007f
 #define SYSTEM_CLK_XTAL_FREQ_M  (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S)
-#define SYSTEM_CLK_XTAL_FREQ_V  0x0000007F
+#define SYSTEM_CLK_XTAL_FREQ_V  0x0000007f
 #define SYSTEM_CLK_XTAL_FREQ_S  12
 
 /* SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0;
@@ -1442,24 +1441,24 @@
  * This field is used to set the count of prescaler of XTAL\_CLK.
  */
 
-#define SYSTEM_PRE_DIV_CNT    0x000003FF
+#define SYSTEM_PRE_DIV_CNT    0x000003ff
 #define SYSTEM_PRE_DIV_CNT_M  (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S)
-#define SYSTEM_PRE_DIV_CNT_V  0x000003FF
+#define SYSTEM_PRE_DIV_CNT_V  0x000003ff
 #define SYSTEM_PRE_DIV_CNT_S  0
 
-/* SYSTEM_REG_DATE_REG register
+/* SYSTEM_DATE_REG register
  * Version control register
  */
 
-#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
+#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
 
-/* SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 26247200;
+/* SYSTEM_DATE : R/W; bitpos: [27:0]; default: 26247200;
- * This is the date version register.
+ * Version control register.
  */
 
-#define SYSTEM_SYSTEM_REG_DATE    0x0FFFFFFF
+#define SYSTEM_DATE    0x0fffffff
-#define SYSTEM_SYSTEM_REG_DATE_M  (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S)
+#define SYSTEM_DATE_M  (SYSTEM_DATE_V << SYSTEM_DATE_S)
-#define SYSTEM_SYSTEM_REG_DATE_V  0x0FFFFFFF
+#define SYSTEM_DATE_V  0x0fffffff
-#define SYSTEM_SYSTEM_REG_DATE_S  0
+#define SYSTEM_DATE_S  0
 
 #endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H */