diff --git a/arch/arm/src/max326xx/chip/max326_gcr.h b/arch/arm/src/max326xx/chip/max326_gcr.h new file mode 100644 index 00000000000..97b4e09520e --- /dev/null +++ b/arch/arm/src/max326xx/chip/max326_gcr.h @@ -0,0 +1,196 @@ +/************************************************************************************ + * arch/arm/src/max326xx/chip/max326_gcr.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_GCR_H +#define __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_GCR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/max326_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define MAX326_GCR_SCON_OFFSET 0x0000 /* System Control Register */ +#define MAX326_GCR_RST0_OFFSET 0x0004 /* Reset Register 0 */ +#define MAX326_GCR_CLKCTRL_OFFSET 0x0008 /* Clock Control Register */ +#define MAX326_GCR_PM_OFFSET 0x000c /* Power Management Register */ +#define MAX326_GCR_PCLKDIS0_OFFSET 0x0024 /* Peripheral Clocks Disable 0 */ +#define MAX326_GCR_MEMCTRL_OFFSET 0x0028 /* Memory Clock Control */ +#define MAX326_GCR_MEMZCTRL_OFFSET 0x002c /* Memory Zeroize Register */ +#define MAX326_GCR_SYSSTAT_OFFSET 0x0040 /* System Status Flags */ +#define MAX326_GCR_RST1_OFFSET 0x0044 /* Reset Register 1 */ +#define MAX326_GCR_PCLKDIS1_OFFSET 0x0048 /* Peripheral Clocks Disable 1 */ +#define MAX326_GCR_EVTEN_OFFSET 0x004c /* Event Enable Register */ +#define MAX326_GCR_REV_OFFSET 0x0050 /* Revision Register */ +#define MAX326_GCR_SYSIE_OFFSET 0x0054 /* System Status Interrupt Enable */ + +/* Register Addresses ***************************************************************/ + +#define MAX326_GCR_SCON (MAX326_GCR_BASE + MAX326_GCR_SCON_OFFSET) +#define MAX326_GCR_RST0 (MAX326_GCR_BASE + MAX326_GCR_RST0_OFFSET) +#define MAX326_GCR_CLKCTRL (MAX326_GCR_BASE + MAX326_GCR_CLKCTRL_OFFSET) +#define MAX326_GCR_PM (MAX326_GCR_BASE + MAX326_GCR_PM_OFFSET) +#define MAX326_GCR_PCLKDIS0 (MAX326_GCR_BASE + MAX326_GCR_PCLKDIS0_OFFSET) +#define MAX326_GCR_MEMCTRL (MAX326_GCR_BASE + MAX326_GCR_MEMCTRL_OFFSET) +#define MAX326_GCR_MEMZCTRL (MAX326_GCR_BASE + MAX326_GCR_MEMZCTRL_OFFSET) +#define MAX326_GCR_SYSSTAT (MAX326_GCR_BASE + MAX326_GCR_SYSSTAT_OFFSET) +#define MAX326_GCR_RST1 (MAX326_GCR_BASE + MAX326_GCR_RST1_OFFSET) +#define MAX326_GCR_PCLKDIS1 (MAX326_GCR_BASE + MAX326_GCR_PCLKDIS1_OFFSET) +#define MAX326_GCR_EVTEN (MAX326_GCR_BASE + MAX326_GCR_EVTEN_OFFSET) +#define MAX326_GCR_REV (MAX326_GCR_BASE + MAX326_GCR_REV_OFFSET) +#define MAX326_GCR_SYSIE (MAX326_GCR_BASE + MAX326_GCR_SYSIE_OFFSET) + +/* Register Bit-field Definitions ***************************************************/ + +/* System Control Register */ + +#define GCR_SCON_FLASH_PAGEFLIP (1 >> 4) /* Bit 4: Flash Page Flip Flag */ +#define GCR_SCON_FPUDIS (1 >> 5) /* Bit 5: Floating Point Unit (FPU) Disable */ +#define GCR_SCON_ICC0FLUSH (1 >> 6) /* Bit 6: Instruction Cache Controller Flush */ +#define GCR_SCON_SWDDIS (1 >> 14) /* Bit 14: Serial Wire Debug Disable */ + +/* Reset Register 0 */ + +#define GCR_RST0_DMA (1 << 0) /* Bit 0: Standard DMA Reset */ +#define GCR_RST0_WDT0 (1 << 1) /* Bit 1: Watchdog Timer 0 Reset */ +#define GCR_RST0_GPIO0 (1 << 2) /* Bit 2: GPIO0 Reset */ +#define GCR_RST0_TMR1 (1 << 6) /* Bit 6: Timer1 Reset */ +#define GCR_RST0_TMR2 (1 << 7) /* Bit 7: Timer2 Reset */ +#define GCR_RST0_UART0 (1 << 11) /* Bit 11: UART0 Reset */ +#define GCR_RST0_UART1 (1 << 12) /* Bit 12: UART1 Reset */ +#define GCR_RST0_SPI0 (1 << 13) /* Bit 13: SPI0 Reset */ +#define GCR_RST0_SPI1 (1 << 14) /* Bit 14: SPIMSS (SPI1/I2S) Reset */ +#define GCR_RST0_I2C0 (1 << 16) /* Bit 16: I2C0 Reset */ +#define GCR_RST0_RTC (1 << 17) /* Bit 17: RTC Reset */ +#define GCR_RST0_SOFT (1 << 29) /* Bit 29: Soft Reset */ +#define GCR_RST0_PERIPH (1 << 30) /* Bit 30: System Peripheral Reset */ +#define GCR_RST0_SYSTEM (1 << 31) /* Bit 31: System Reset */ + +/* Clock Control Register */ + +#define GCR_CLKCTRL_PSC_SHIFT (6) /* Bits 6-8: System Oscillator Prescaler */ +#define GCR_CLKCTRL_PSC_MASK (7 << GCR_CLKCTRL_PSC_SHIFT) +# define GCR_CLKCTRL_PSC(n) ((uint32_t)(n) << GCR_CLKCTRL_PSC_SHIFT) +#define GCR_CLKCTRL_CLKSEL_SHIFT (9) /* Bits 9-11: System Oscillator Source Select */ +#define GCR_CLKCTRL_CLKSEL_MASK (7 << GCR_CLKCTRL_CLKSEL_SHIFT) +# define GCR_CLKCTRL_CLKSEL_HIRC (0 << GCR_CLKCTRL_CLKSEL_SHIFT) /* High-Frequency Internal Oscillator (HFIO) */ +# define GCR_CLKCTRL_CLKSEL_LIRC8K (3 << GCR_CLKCTRL_CLKSEL_SHIFT) /* 8kHz Low-Frequency Internal Oscillator */ +# define GCR_CLKCTRL_CLKSEL_X32K (6 << GCR_CLKCTRL_CLKSEL_SHIFT) /* 32.768kHz External Oscillator */ +#define GCR_CLKCTRL_CLKRDY (1 << 13) /* Bit 13: System Oscillator Clock Source Ready */ +#define GCR_CLKCTRL_X32KEN (1 << 17) /* Bit 17: 32.768kHz External Oscillator Enable */ +#define GCR_CLKCTRL_HIRCEN (1 << 18) /* Bit 18: High-Frequency Internal Oscillator (HFIO) Enable */ +#define GCR_CLKCTRL_X32KRDY (1 << 25) /* Bit 25: 32.768kHz External Oscillator Ready Status */ +#define GCR_CLKCTRL_LIRC8KRDY (1 << 29) /* Bit 29: 8kHz Internal Oscillator Ready Status */ + +/* Power Management Register */ + +#define GCR_PM_MODE_SHIFT (0) /* Bits 0-2: Operating Mode */ +#define GCR_PM_MODE_MASK (7 << GCR_PM_MODE_SHIFT) +# define GCR_PM_MODE_ACTIVE (0 << GCR_PM_MODE_SHIFT) /* Active mode */ +# define GCR_PM_MODE_BACKUP (4 << GCR_PM_MODE_SHIFT) /* Backup Low Power Mode */ +# define GCR_PM_MODE_SHUTDOWN (6 << GCR_PM_MODE_SHIFT) /* Shutdown Mode */ +#define GCR_PM_GPIOWKEN (1 << 4) /* Bit 4: GPIO Wakeup Enable */ +#define GCR_PM_RTCWKEN (1 << 5) /* Bit 5: RTC Alarm Wakeup Enable */ +#define GCR_PM_HFIOPD (1 << 15) /* Bit 15: HFIO DEEPSLEEP Auto Off */ + +/* Peripheral Clocks Disable 0 */ + +#define GCR_PCLKDIS0_GPIO0D (1 << 0) /* Bit 0: GPIO0 Port and Pad Logic Clock Disable */ +#define GCR_PCLKDIS0_DMAD (1 << 5) /* Bit 5: Standard DMA Clock Disable */ +#define GCR_PCLKDIS0_SPI0D (1 << 6) /* Bit 6: SPI0 Clock Disable */ +#define GCR_PCLKDIS0_SPI1D (1 << 7) /* Bit 7: SPI1 Clock Disable */ +#define GCR_PCLKDIS0_UART0D (1 << 9) /* Bit 9: UART0 Clock Disable */ +#define GCR_PCLKDIS0_UART1D (1 << 10) /* Bit 10: UART1 Clock Disable */ +#define GCR_PCLKDIS0_I2C0D (1 << 13) /* Bit 14: I2C0 Clock Disable */ +#define GCR_PCLKDIS0_TMR0D (1 << 15) /* Bit 15: Timer0 Clock Disable */ +#define GCR_PCLKDIS0_TMR1D (1 << 16) /* Bit 16: Timer1 Clock Disable */ +#define GCR_PCLKDIS0_TMR2D (1 << 17) /* Bit 17: Timer2 Clock Disable */ +#define GCR_PCLKDIS0_I2C1D (1 << 28) /* Bit 28: I2C1 Clock Disable */ + +/* Memory Clock Control */ + +#define GCR_MEMCTRL_FWS_SHIFT (0) /* Bits 0-2: Flash Wait States */ +#define GCR_MEMCTRL_RAM0LS (1 << 8) /* Bit 8: System RAM 0 Light Sleep Enable */ +#define GCR_MEMCTRL_RAM1LS (1 << 9) /* Bit 9: System RAM 1 Light Sleep Enable */ +#define GCR_MEMCTRL_RAM2LS (1 << 10) /* Bit 10: System RAM 2 Light Sleep Enable */ +#define GCR_MEMCTRL_RAM3LS (1 << 11) /* Bit 11: System RAM 3 Light Sleep Enable */ +#define GCR_MEMCTRL_ICACHERET (1 << 12) /* Bit 12: ICC0 Cache RAM Light Sleep Enable */ + +/* Memory Zeroize Register */ + +#define GCR_MEMZCTRL_SRAM_ZERO (1 << 0) /* Bit 0: System Data RAM Zeroization */ +#define GCR_MEMZCTRL_ICACHE_ZERO (1 << 1) /* Bit 1: Internal Cache Data and Tag RAM Zeroization */ + +/* System Status Flags */ + +#define GCR_SYSSTAT_ICELOCK (1 << 0) /* Bit 0: Arm Cortex-M4 with FPU ICE Lock Status Flag */ + +/* Reset Register 1 */ + +#define GCR_RST1_I2C1 (1 << 0) /* Bit 0: I2C1 Reset */ + +/* Peripheral Clocks Disable 1 */ + +#define GCR_PCLKDIS1_FLCD (1 << 3) /* Bit 3: Flash Controller Disable */ +#define GCR_PCLKDIS1_ICCD (1 << 11) /* Bit 11: ICC Clock Disable */ + +/* Event Enable Register */ + +#define GCR_EVTEN_DMAEVENT (1 << 0) /* Bit 0: DMA CTZ Event Wake-Up Enable */ +#define GCR_EVTEN_RXEVT (1 << 1) /* Bit 1: RX Event Enabled */ + +/* Revision Register */ + +#define GCR_REV_MASK (0xffff) /* Bits 0-15: Maxim Integrated Chip Revision */ + +/* System Status Interrupt Enable */ + +#define GCR_SYSIE_ICEULIE (1 << 0) /* Bit 0: Arm ICE Unlocked Interrupt Enable */ + +#endif /* __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_GCR_H */ diff --git a/arch/arm/src/max326xx/max32620_30/max32620_30_clockconfig.h b/arch/arm/src/max326xx/max32620_30/max32620_30_clockconfig.h new file mode 100644 index 00000000000..deed274bf72 --- /dev/null +++ b/arch/arm/src/max326xx/max32620_30/max32620_30_clockconfig.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/arm/src/max326xx/max32620_30/max32620_30_clockconfig.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MAX326XX_MAX_32620_30_MAX32620_30_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_MAX326XX_MAX_32620_30_MAX32620_30_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Clock sources */ + +enum clock_source_e +{ + CLKSRC_HFIO = 0, /* Internal 96MHz Relaxation Oscillator */ + CLKSRC_4KHZ, /* Internal 4MHz RC Oscillator */ + CLKSRC_44KHZ, /* Internal 44MHz Relaxation Oscillator (Crypto Oscillator) */ + CLKSRC_32KHZ /* RTC 32768Hz Crystal Oscillator */ +}; + +/* This structure can be used to define a clock configuration. */ + +struct clock_setup_s +{ + uint8_t clksrc; /* See enum clock_source_e */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_MAX326XX_MAX_32620_30_MAX32620_30_CLOCKCONFIG_H */ diff --git a/arch/arm/src/max326xx/max32660/max32660_clockconfig.h b/arch/arm/src/max326xx/max32660/max32660_clockconfig.h new file mode 100644 index 00000000000..f482112d21d --- /dev/null +++ b/arch/arm/src/max326xx/max32660/max32660_clockconfig.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/max326xx/max32660/max32660_clockconfig.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MAX326XX_MAX_32660_MAX32660_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_MAX326XX_MAX_32660_MAX32660_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Clock sources. Values match the CLKSEL field of the GCR_CLK_CTRL + * register + */ + +enum clock_source_e +{ + CLKSRC_HFIO = 0, /* High frequency internal oscillator */ + CLKSRC_8KHZ = 3, /* 8kHz Internal Ultra-Low Power Nano-Ring Oscillator */ + CLKSRC_32KHZ = 6 /* 32.768kHz External Crystal Oscillator */ +}; + +/* This structure can be used to define a clock configuration. + * + * Fhfio Determined by Output Voltage Range. + * Fsysoc Determined by source clock selection. + * Fsysclk = Fsysclk / (2^psc) + * Fpclk = Fsysclk / 2 + */ + +struct clock_setup_s +{ + uint8_t ovr; /* Output voltage range for internal regulator */ + uint8_t clksrc; /* See enum clock_source_e. Determines Fsysosc */ + uint8_t psc; /* System Oscillator Prescaler. Derives Fsysclk */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_MAX326XX_MAX_32660_MAX32660_CLOCKCONFIG_H */ diff --git a/arch/arm/src/max326xx/max326_clockconfig.h b/arch/arm/src/max326xx/max326_clockconfig.h index 95480606182..e235c0f92d8 100644 --- a/arch/arm/src/max326xx/max326_clockconfig.h +++ b/arch/arm/src/max326xx/max326_clockconfig.h @@ -46,11 +46,16 @@ * Public Types ****************************************************************************/ -/* This structure can be used to define a clock configuration. */ +/* Include the MCU-specific structure can be used to define a clock + * configuration. */ -struct clock_setup_s -{ -}; +#if defined(CONFIG_ARCH_FAMILY_MAX32620) || defined(CONFIG_ARCH_FAMILY_MAX32630) +# include "max32620_30/max32620_30_clockconfig.h" +#if defined(CONFIG_ARCH_FAMILY_MAX32660) +# include "max32660/max32660_clockconfig.h" +#else +# error "Unsupported MAX326XX family" +#endif /**************************************************************************** * Inline Functions @@ -88,6 +93,16 @@ extern "C" void max326_clockconfig(FAR const struct clock_setup_s *clocksetup); +/**************************************************************************** + * Name: max326_hfio_frequency + * + * Description: + * Return the High-Frequency Internal Oscillator (HFIO) frequency. + * + *****************************************************************************/ + +uint32_t max326_hfio_frequency(void); + /**************************************************************************** * Name: max326_cpu_frequency *