diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/stm32/hardware/stm32_tim.h index 414d71aee63..458357adc78 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/stm32/hardware/stm32_tim.h @@ -129,13 +129,6 @@ #define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */ -/* TIM16, and 17 only. - * Only available in the STM32 F1 Value Line and the STM32 F3 family. - */ - -#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ - /* Advanced Timers - TIM1 and TIM8 */ #define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ @@ -1242,48 +1235,6 @@ # define GTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ #endif -/* Repitition counter (TIM15-17 only) */ - -#define GTIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define GTIM_RCR_REP_MASK (0xff << GTIM_RCR_REP_SHIFT) - -#define GTIM_RCR_REP_MAX 128 - -/* Break and dead-time register (TIM15-17 only) */ - -#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT) -#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT) -# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ -#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define GTIM_BDTR_BKF_MASK (15 << GTIM_BDTR_BKF_SHIFT) -# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ - /* DMA control register */ #define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 5031aec1d56..9d9a1abbe67 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -111,9 +111,9 @@ #define TIMTYPE_TIM12 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM13 TIMTYPE_COUNTUP16 #define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 -#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N -#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N -#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N +#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ /* Timer clock source, RCC EN offset, enable bit, * RCC RST offset, reset bit to use @@ -674,7 +674,7 @@ static struct stm32_pwmchan_s g_pwm1channels[] = .pincfg = 0, /* No available externaly */ } #endif - } + }, #endif #ifdef CONFIG_STM32_TIM1_CHANNEL6 { @@ -1234,7 +1234,7 @@ static struct stm32_pwmchan_s g_pwm8channels[] = .pincfg = 0, /* No available externaly */ } #endif - } + }, #endif #ifdef CONFIG_STM32_TIM8_CHANNEL6 { @@ -3200,7 +3200,7 @@ static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv) /* Configure lock */ - bdtr |= priv->lock << GTIM_BDTR_LOCK_SHIFT; + bdtr |= priv->lock << ATIM_BDTR_LOCK_SHIFT; /* Write BDTR register at once */ @@ -3885,7 +3885,7 @@ static uint8_t pwm_pulsecount(uint32_t count) * just return the count. */ - if (count <= GTIM_RCR_REP_MAX) + if (count <= ATIM_RCR_REP_MAX) { return (uint8_t)count; } @@ -3897,16 +3897,16 @@ static uint8_t pwm_pulsecount(uint32_t count) * and 128. */ - else if (count < (3 * GTIM_RCR_REP_MAX / 2)) + else if (count < (3 * ATIM_RCR_REP_MAX / 2)) { - return (uint8_t)((GTIM_RCR_REP_MAX + 1) >> 1); + return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); } /* Otherwise, return the maximum. The final count will be 64 or more */ else { - return (uint8_t)GTIM_RCR_REP_MAX; + return (uint8_t)ATIM_RCR_REP_MAX; } } #endif /* HAVE_PWM_INTERRUPT */ diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 1e572c9d6c1..9f19ece93ff 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -134,6 +134,10 @@ config STM32H7_TIM bool default n +config STM32H7_PWM + bool + default n + config STM32H7_USART bool default n @@ -948,11 +952,18 @@ config STM32H7_CUSTOM_CLOCKCONFIG menu "Timer Configuration" +config STM32H7_PWM_LL_OPS + bool "PWM low-level operations" + default n + ---help--- + Enable low-level PWM ops. + config STM32H7_TIM1_PWM bool "TIM1 PWM" default n depends on STM32H7_TIM1 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 1 for use by PWM @@ -970,6 +981,27 @@ config STM32H7_TIM1_MODE ---help--- Specifies the timer mode. +config STM32H7_TIM1_LOCK + int "TIM1 Lock Level Configuration" + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32H7_TIM1_TDTS + int "TIM1 t_DTS Division" + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32H7_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + if STM32H7_PWM_MULTICHAN config STM32H7_TIM1_CHANNEL1 @@ -982,10 +1014,10 @@ if STM32H7_TIM1_CHANNEL1 config STM32H7_TIM1_CH1MODE int "TIM1 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM1_CH1OUT bool "TIM1 Channel 1 Output" @@ -993,6 +1025,12 @@ config STM32H7_TIM1_CH1OUT ---help--- Enables channel 1 output. +config STM32H7_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + default n + ---help--- + Enables channel 1 Complementary Output. + endif # STM32H7_TIM1_CHANNEL1 config STM32H7_TIM1_CHANNEL2 @@ -1005,10 +1043,10 @@ if STM32H7_TIM1_CHANNEL2 config STM32H7_TIM1_CH2MODE int "TIM1 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM1_CH2OUT bool "TIM1 Channel 2 Output" @@ -1016,6 +1054,12 @@ config STM32H7_TIM1_CH2OUT ---help--- Enables channel 2 output. +config STM32H7_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + default n + ---help--- + Enables channel 2 Complementary Output. + endif # STM32H7_TIM1_CHANNEL2 config STM32H7_TIM1_CHANNEL3 @@ -1028,10 +1072,10 @@ if STM32H7_TIM1_CHANNEL3 config STM32H7_TIM1_CH3MODE int "TIM1 Channel 3 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM1_CH3OUT bool "TIM1 Channel 3 Output" @@ -1039,6 +1083,12 @@ config STM32H7_TIM1_CH3OUT ---help--- Enables channel 3 output. +config STM32H7_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + default n + ---help--- + Enables channel 3 Complementary Output. + endif # STM32H7_TIM1_CHANNEL3 config STM32H7_TIM1_CHANNEL4 @@ -1051,10 +1101,10 @@ if STM32H7_TIM1_CHANNEL4 config STM32H7_TIM1_CH4MODE int "TIM1 Channel 4 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM1_CH4OUT bool "TIM1 Channel 4 Output" @@ -1065,19 +1115,19 @@ config STM32H7_TIM1_CH4OUT endif # STM32H7_TIM1_CHANNEL4 config STM32H7_TIM1_CHANNEL5 - bool "TIM1 Channel 5" + bool "TIM1 Channel 5 (internal)" default n ---help--- - Enables channel 5. + Enables channel 5 (no available externaly) if STM32H7_TIM1_CHANNEL5 config STM32H7_TIM1_CH5MODE int "TIM1 Channel 5 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM1_CH5OUT bool "TIM1 Channel 5 Output" @@ -1088,19 +1138,19 @@ config STM32H7_TIM1_CH5OUT endif # STM32H7_TIM1_CHANNEL5 config STM32H7_TIM1_CHANNEL6 - bool "TIM1 Channel 6" + bool "TIM1 Channel 6 (internal)" default n ---help--- - Enables channel 6. + Enables channel 6 (no available externaly) if STM32H7_TIM1_CHANNEL6 config STM32H7_TIM1_CH6MODE int "TIM1 Channel 6 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM1_CH6OUT bool "TIM1 Channel 6 Output" @@ -1122,12 +1172,70 @@ config STM32H7_TIM1_CHANNEL If TIM1 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +if STM32H7_TIM1_CHANNEL = 1 + +config STM32H7_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H7_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + default n + ---help--- + Enables channel 1 Complementary Output. + +endif # STM32H7_TIM1_CHANNEL = 1 + +if STM32H7_TIM1_CHANNEL = 2 + +config STM32H7_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +config STM32H7_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + default n + ---help--- + Enables channel 2 Complementary Output. + +endif # STM32H7_TIM1_CHANNEL = 2 + +if STM32H7_TIM1_CHANNEL = 3 + +config STM32H7_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +config STM32H7_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + default n + ---help--- + Enables channel 3 Complementary Output. + +endif # STM32H7_TIM1_CHANNEL = 3 + +if STM32H7_TIM1_CHANNEL = 4 + +config STM32H7_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H7_TIM1_CHANNEL = 4 + config STM32H7_TIM1_CHMODE int "TIM1 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1138,6 +1246,7 @@ config STM32H7_TIM2_PWM default n depends on STM32H7_TIM2 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 2 for use by PWM @@ -1167,10 +1276,10 @@ if STM32H7_TIM2_CHANNEL1 config STM32H7_TIM2_CH1MODE int "TIM2 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM2_CH1OUT bool "TIM2 Channel 1 Output" @@ -1190,10 +1299,10 @@ if STM32H7_TIM2_CHANNEL2 config STM32H7_TIM2_CH2MODE int "TIM2 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM2_CH2OUT bool "TIM2 Channel 2 Output" @@ -1213,10 +1322,10 @@ if STM32H7_TIM2_CHANNEL3 config STM32H7_TIM2_CH3MODE int "TIM2 Channel 3 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM2_CH3OUT bool "TIM2 Channel 3 Output" @@ -1236,10 +1345,10 @@ if STM32H7_TIM2_CHANNEL4 config STM32H7_TIM2_CH4MODE int "TIM2 Channel 4 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM2_CH4OUT bool "TIM2 Channel 4 Output" @@ -1261,12 +1370,52 @@ config STM32H7_TIM2_CHANNEL If TIM2 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +if STM32H7_TIM2_CHANNEL = 1 + +config STM32H7_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM2_CHANNEL = 1 + +if STM32H7_TIM2_CHANNEL = 2 + +config STM32H7_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H7_TIM2_CHANNEL = 2 + +if STM32H7_TIM2_CHANNEL = 3 + +config STM32H7_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H7_TIM2_CHANNEL = 3 + +if STM32H7_TIM2_CHANNEL = 4 + +config STM32H7_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H7_TIM2_CHANNEL = 4 + config STM32H7_TIM2_CHMODE int "TIM2 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1277,6 +1426,7 @@ config STM32H7_TIM3_PWM default n depends on STM32H7_TIM3 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 3 for use by PWM @@ -1306,10 +1456,10 @@ if STM32H7_TIM3_CHANNEL1 config STM32H7_TIM3_CH1MODE int "TIM3 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM3_CH1OUT bool "TIM3 Channel 1 Output" @@ -1329,10 +1479,10 @@ if STM32H7_TIM3_CHANNEL2 config STM32H7_TIM3_CH2MODE int "TIM3 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM3_CH2OUT bool "TIM3 Channel 2 Output" @@ -1352,10 +1502,10 @@ if STM32H7_TIM3_CHANNEL3 config STM32H7_TIM3_CH3MODE int "TIM3 Channel 3 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM3_CH3OUT bool "TIM3 Channel 3 Output" @@ -1375,10 +1525,10 @@ if STM32H7_TIM3_CHANNEL4 config STM32H7_TIM3_CH4MODE int "TIM3 Channel 4 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM3_CH4OUT bool "TIM3 Channel 4 Output" @@ -1400,12 +1550,52 @@ config STM32H7_TIM3_CHANNEL If TIM3 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +if STM32H7_TIM3_CHANNEL = 1 + +config STM32H7_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM3_CHANNEL = 1 + +if STM32H7_TIM3_CHANNEL = 2 + +config STM32H7_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H7_TIM3_CHANNEL = 2 + +if STM32H7_TIM3_CHANNEL = 3 + +config STM32H7_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H7_TIM3_CHANNEL = 3 + +if STM32H7_TIM3_CHANNEL = 4 + +config STM32H7_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H7_TIM3_CHANNEL = 4 + config STM32H7_TIM3_CHMODE int "TIM3 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1416,6 +1606,7 @@ config STM32H7_TIM4_PWM default n depends on STM32H7_TIM4 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 4 for use by PWM @@ -1445,10 +1636,10 @@ if STM32H7_TIM4_CHANNEL1 config STM32H7_TIM4_CH1MODE int "TIM4 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM4_CH1OUT bool "TIM4 Channel 1 Output" @@ -1468,10 +1659,10 @@ if STM32H7_TIM4_CHANNEL2 config STM32H7_TIM4_CH2MODE int "TIM4 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM4_CH2OUT bool "TIM4 Channel 2 Output" @@ -1491,10 +1682,10 @@ if STM32H7_TIM4_CHANNEL3 config STM32H7_TIM4_CH3MODE int "TIM4 Channel 3 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM4_CH3OUT bool "TIM4 Channel 3 Output" @@ -1514,10 +1705,10 @@ if STM32H7_TIM4_CHANNEL4 config STM32H7_TIM4_CH4MODE int "TIM4 Channel 4 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM4_CH4OUT bool "TIM4 Channel 4 Output" @@ -1539,12 +1730,52 @@ config STM32H7_TIM4_CHANNEL If TIM4 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +if STM32H7_TIM4_CHANNEL = 1 + +config STM32H7_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM4_CHANNEL = 1 + +if STM32H7_TIM4_CHANNEL = 2 + +config STM32H7_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H7_TIM4_CHANNEL = 2 + +if STM32H7_TIM4_CHANNEL = 3 + +config STM32H7_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H7_TIM4_CHANNEL = 3 + +if STM32H7_TIM4_CHANNEL = 4 + +config STM32H7_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H7_TIM4_CHANNEL = 4 + config STM32H7_TIM4_CHMODE int "TIM4 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1555,6 +1786,7 @@ config STM32H7_TIM5_PWM default n depends on STM32H7_TIM5 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 5 for use by PWM @@ -1584,10 +1816,10 @@ if STM32H7_TIM5_CHANNEL1 config STM32H7_TIM5_CH1MODE int "TIM5 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM5_CH1OUT bool "TIM5 Channel 1 Output" @@ -1607,10 +1839,10 @@ if STM32H7_TIM5_CHANNEL2 config STM32H7_TIM5_CH2MODE int "TIM5 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM5_CH2OUT bool "TIM5 Channel 2 Output" @@ -1630,10 +1862,10 @@ if STM32H7_TIM5_CHANNEL3 config STM32H7_TIM5_CH3MODE int "TIM5 Channel 3 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM5_CH3OUT bool "TIM5 Channel 3 Output" @@ -1653,10 +1885,10 @@ if STM32H7_TIM5_CHANNEL4 config STM32H7_TIM5_CH4MODE int "TIM5 Channel 4 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM5_CH4OUT bool "TIM5 Channel 4 Output" @@ -1678,12 +1910,52 @@ config STM32H7_TIM5_CHANNEL If TIM5 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +if STM32H7_TIM5_CHANNEL = 1 + +config STM32H7_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM5_CHANNEL = 1 + +if STM32H7_TIM5_CHANNEL = 2 + +config STM32H7_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H7_TIM5_CHANNEL = 2 + +if STM32H7_TIM5_CHANNEL = 3 + +config STM32H7_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # STM32H7_TIM5_CHANNEL = 3 + +if STM32H7_TIM5_CHANNEL = 4 + +config STM32H7_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H7_TIM5_CHANNEL = 4 + config STM32H7_TIM5_CHMODE int "TIM5 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1694,6 +1966,7 @@ config STM32H7_TIM8_PWM default n depends on STM32H7_TIM8 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 8 for use by PWM @@ -1711,6 +1984,27 @@ config STM32H7_TIM8_MODE ---help--- Specifies the timer mode. +config STM32H7_TIM8_LOCK + int "TIM8 Lock Level Configuration" + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32H7_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32H7_TIM8_TDTS + int "TIM8 t_DTS Division" + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + if STM32H7_PWM_MULTICHAN config STM32H7_TIM8_CHANNEL1 @@ -1723,16 +2017,22 @@ if STM32H7_TIM8_CHANNEL1 config STM32H7_TIM8_CH1MODE int "TIM8 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" + bool "TIM8 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H7_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" default n ---help--- - Enables channel 1 output. + Enables channel 1 Complementary Output. endif # STM32H7_TIM8_CHANNEL1 @@ -1746,10 +2046,10 @@ if STM32H7_TIM8_CHANNEL2 config STM32H7_TIM8_CH2MODE int "TIM8 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM8_CH2OUT bool "TIM8 Channel 2 Output" @@ -1757,6 +2057,12 @@ config STM32H7_TIM8_CH2OUT ---help--- Enables channel 2 output. +config STM32H7_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + default n + ---help--- + Enables channel 2 Complementary Output. + endif # STM32H7_TIM8_CHANNEL2 config STM32H7_TIM8_CHANNEL3 @@ -1769,10 +2075,10 @@ if STM32H7_TIM8_CHANNEL3 config STM32H7_TIM8_CH3MODE int "TIM8 Channel 3 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM8_CH3OUT bool "TIM8 Channel 3 Output" @@ -1780,6 +2086,12 @@ config STM32H7_TIM8_CH3OUT ---help--- Enables channel 3 output. +config STM32H7_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + default n + ---help--- + Enables channel 3 Complementary Output. + endif # STM32H7_TIM8_CHANNEL3 config STM32H7_TIM8_CHANNEL4 @@ -1792,10 +2104,10 @@ if STM32H7_TIM8_CHANNEL4 config STM32H7_TIM8_CH4MODE int "TIM8 Channel 4 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM8_CH4OUT bool "TIM8 Channel 4 Output" @@ -1806,19 +2118,19 @@ config STM32H7_TIM8_CH4OUT endif # STM32H7_TIM8_CHANNEL4 config STM32H7_TIM8_CHANNEL5 - bool "TIM8 Channel 5" + bool "TIM8 Channel 5 (internal)" default n ---help--- - Enables channel 5. + Enables channel 5 (no available externaly) if STM32H7_TIM8_CHANNEL5 config STM32H7_TIM8_CH5MODE int "TIM8 Channel 5 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM8_CH5OUT bool "TIM8 Channel 5 Output" @@ -1829,19 +2141,19 @@ config STM32H7_TIM8_CH5OUT endif # STM32H7_TIM8_CHANNEL5 config STM32H7_TIM8_CHANNEL6 - bool "TIM8 Channel 6" + bool "TIM8 Channel 6 (internal)" default n ---help--- - Enables channel 4. + Enables channel 6 (no available externaly) if STM32H7_TIM8_CHANNEL6 config STM32H7_TIM8_CH6MODE int "TIM8 Channel 6 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM8_CH6OUT bool "TIM8 Channel 6 Output" @@ -1849,7 +2161,7 @@ config STM32H7_TIM8_CH6OUT ---help--- Enables channel 6 output. -endif # STM32H7_TIM8_CHANNEL4 +endif # STM32H7_TIM8_CHANNEL6 endif # STM32H7_PWM_MULTICHAN @@ -1863,12 +2175,70 @@ config STM32H7_TIM8_CHANNEL If TIM8 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} +if STM32H7_TIM8_CHANNEL = 1 + +config STM32H7_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config STM32H7_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + default n + ---help--- + Enables channel 1 Complementary Output. + +endif # STM32H7_TIM8_CHANNEL = 1 + +if STM32H7_TIM8_CHANNEL = 2 + +config STM32H7_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +config STM32H7_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + default n + ---help--- + Enables channel 2 Complementary Output. + +endif # STM32H7_TIM8_CHANNEL = 2 + +if STM32H7_TIM8_CHANNEL = 3 + +config STM32H7_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +config STM32H7_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + default n + ---help--- + Enables channel 3 Complementary Output. + +endif # STM32H7_TIM8_CHANNEL = 3 + +if STM32H7_TIM8_CHANNEL = 4 + +config STM32H7_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + default n + ---help--- + Enables channel 4 output. + +endif # STM32H7_TIM8_CHANNEL = 4 + config STM32H7_TIM8_CHMODE int "TIM8 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1879,6 +2249,7 @@ config STM32H7_TIM12_PWM default n depends on STM32H7_TIM12 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 12 for use by PWM @@ -1901,10 +2272,10 @@ if STM32H7_TIM12_CHANNEL1 config STM32H7_TIM12_CH1MODE int "TIM12 Channel 1 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM12_CH1OUT bool "TIM12 Channel 1 Output" @@ -1924,10 +2295,10 @@ if STM32H7_TIM12_CHANNEL2 config STM32H7_TIM12_CH2MODE int "TIM12 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM12_CH2OUT bool "TIM12 Channel 2 Output" @@ -1949,12 +2320,32 @@ config STM32H7_TIM12_CHANNEL If TIM12 is enabled for PWM usage, you also need specifies the timer output channel {1,2} +if STM32H7_TIM12_CHANNEL = 1 + +config STM32H7_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM12_CHANNEL = 1 + +if STM32H7_TIM12_CHANNEL = 2 + +config STM32H7_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +endif # STM32H7_TIM12_CHANNEL = 2 + config STM32H7_TIM12_CHMODE int "TIM12 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -1965,6 +2356,7 @@ config STM32H7_TIM13_PWM default n depends on STM32H7_TIM13 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 13 for use by PWM @@ -1975,6 +2367,33 @@ config STM32H7_TIM13_PWM if STM32H7_TIM13_PWM +if STM32H7_PWM_MULTICHAN + +config STM32H7_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H7_TIM13_CHANNEL1 + +config STM32H7_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32H7_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM13_CHANNEL1 + +endif # STM32H7_PWM_MULTICHAN + if !STM32H7_PWM_MULTICHAN config STM32H7_TIM13_CHANNEL @@ -1985,12 +2404,22 @@ config STM32H7_TIM13_CHANNEL If TIM13 is enabled for PWM usage, you also need specifies the timer output channel {1} +if STM32H7_TIM13_CHANNEL = 1 + +config STM32H7_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM13_CHANNEL = 1 + config STM32H7_TIM13_CHMODE int "TIM13 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -2001,6 +2430,7 @@ config STM32H7_TIM14_PWM default n depends on STM32H7_TIM14 select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 14 for use by PWM @@ -2011,9 +2441,36 @@ config STM32H7_TIM14_PWM if STM32H7_TIM14_PWM +if STM32H7_PWM_MULTICHAN + +config STM32H7_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H7_TIM14_CHANNEL1 + +config STM32H7_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32H7_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM14_CHANNEL1 + +endif # STM32H7_PWM_MULTICHAN + if !STM32H7_PWM_MULTICHAN -config STM32_TIM14_CHANNEL +config STM32H7_TIM14_CHANNEL int "TIM14 PWM Output Channel" default 1 range 1 1 @@ -2021,12 +2478,22 @@ config STM32_TIM14_CHANNEL If TIM14 is enabled for PWM usage, you also need specifies the timer output channel {1} +if STM32H7_TIM14_CHANNEL = 1 + +config STM32H7_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM14_CHANNEL = 1 + config STM32H7_TIM14_CHMODE int "TIM14 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 11 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -2036,7 +2503,7 @@ config STM32H7_TIM15_PWM bool "TIM15 PWM" default n depends on STM32H7_TIM15 - select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 15 for use by PWM @@ -2047,6 +2514,27 @@ config STM32H7_TIM15_PWM if STM32H7_TIM15_PWM +config STM32H7_TIM15_LOCK + int "TIM15 Lock Level Configuration" + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32H7_TIM15_TDTS + int "TIM15 t_DTS Division" + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32H7_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + if STM32H7_PWM_MULTICHAN config STM32H7_TIM15_CHANNEL1 @@ -2058,18 +2546,24 @@ config STM32H7_TIM15_CHANNEL1 if STM32H7_TIM15_CHANNEL1 config STM32H7_TIM15_CH1MODE - int "TIM12 Channel 1 Mode" - default 0 - range 0 5 + int "TIM15 Channel 1 Mode" + default 6 + range 0 9 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM15_CH1OUT - bool "TIM12 Channel 1 Output" + bool "TIM15 Channel 1 Output" default n ---help--- Enables channel 1 output. +config STM32H7_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + default n + ---help--- + Enables channel 1 Complementary Output. + endif # STM32H7_TIM15_CHANNEL1 config STM32H7_TIM15_CHANNEL2 @@ -2082,10 +2576,10 @@ if STM32H7_TIM15_CHANNEL2 config STM32H7_TIM15_CH2MODE int "TIM15 Channel 2 Mode" - default 0 - range 0 5 + default 6 + range 0 9 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. config STM32H7_TIM15_CH2OUT bool "TIM15 Channel 2 Output" @@ -2104,15 +2598,47 @@ config STM32H7_TIM15_CHANNEL default 1 range 1 2 ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output + If TIM15 is enabled for PWM usage, you also need specifies the timer output channel {1,2} -config STM32H7_TIM15_CHMODE - int "TIM12 Channel Mode" - default 0 - range 0 5 +if STM32H7_TIM15_CHANNEL = 1 + +config STM32H7_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + default n ---help--- - Specifies the channel mode. + Enables channel 1 output. + +config STM32H7_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + default n + ---help--- + Enables channel 1 Complementary Output. + +endif # STM32H7_TIM15_CHANNEL = 1 + +if STM32H7_TIM15_CHANNEL = 2 + +config STM32H7_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +config STM32H7_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + default n + ---help--- + Enables channel 2 Complementary Output. + +endif # STM32H7_TIM15_CHANNEL = 2 + +config STM32H7_TIM15_CHMODE + int "TIM15 Channel Mode" + default 6 + range 0 9 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -2122,7 +2648,7 @@ config STM32H7_TIM16_PWM bool "TIM16 PWM" default n depends on STM32H7_TIM16 - select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 16 for use by PWM @@ -2133,9 +2659,57 @@ config STM32H7_TIM16_PWM if STM32H7_TIM16_PWM +config STM32H7_TIM16_LOCK + int "TIM16 Lock Level Configuration" + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32H7_TIM16_TDTS + int "TIM16 t_DTS division" + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32H7_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +if STM32H7_PWM_MULTICHAN + +config STM32H7_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H7_TIM16_CHANNEL1 + +config STM32H7_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + default 6 + range 0 7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32H7_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM16_CHANNEL1 + +endif # STM32H7_PWM_MULTICHAN + if !STM32H7_PWM_MULTICHAN -config STM32_TIM16_CHANNEL +config STM32H7_TIM16_CHANNEL int "TIM16 PWM Output Channel" default 1 range 1 1 @@ -2143,12 +2717,22 @@ config STM32_TIM16_CHANNEL If TIM16 is enabled for PWM usage, you also need specifies the timer output channel {1} +if STM32H7_TIM16_CHANNEL = 1 + +config STM32H7_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM16_CHANNEL = 1 + config STM32H7_TIM16_CHMODE int "TIM16 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 7 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -2158,7 +2742,7 @@ config STM32H7_TIM17_PWM bool "TIM17 PWM" default n depends on STM32H7_TIM17 - select ARCH_HAVE_PWM_PULSECOUNT + select STM32H7_PWM ---help--- Reserve timer 17 for use by PWM @@ -2169,9 +2753,57 @@ config STM32H7_TIM17_PWM if STM32H7_TIM17_PWM +config STM32H7_TIM17_LOCK + int "TIM17 Lock Level Configuration" + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32H7_TIM17_TDTS + int "TIM17 t_DTS Division" + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32H7_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +if STM32H7_PWM_MULTICHAN + +config STM32H7_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + default n + ---help--- + Enables channel 1. + +if STM32H7_TIM17_CHANNEL1 + +config STM32H7_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + default 6 + range 0 7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32H7_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM17_CHANNEL1 + +endif # STM32H7_PWM_MULTICHAN + if !STM32H7_PWM_MULTICHAN -config STM32_TIM17_CHANNEL +config STM32H7_TIM17_CHANNEL int "TIM17 PWM Output Channel" default 1 range 1 1 @@ -2179,12 +2811,22 @@ config STM32_TIM17_CHANNEL If TIM17 is enabled for PWM usage, you also need specifies the timer output channel {1} +if STM32H7_TIM17_CHANNEL = 1 + +config STM32H7_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +endif # STM32H7_TIM17_CHANNEL = 1 + config STM32H7_TIM17_CHMODE int "TIM17 Channel Mode" - default 0 - range 0 5 + default 6 + range 0 7 ---help--- - Specifies the channel mode. + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. endif # !STM32H7_PWM_MULTICHAN @@ -2319,6 +2961,715 @@ config STM32H7_TIM17_CAP Timer devices may be used for different purposes. One special purpose is to capture input. + +menu "STM32 TIMx Outputs Configuration" + +config STM32H7_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH1OUT + ---help--- + TIM1 Channel 1 output polarity + +config STM32H7_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH1OUT + ---help--- + TIM1 Channel 1 output IDLE + +config STM32H7_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH1NOUT + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32H7_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH1NOUT + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32H7_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH2OUT + ---help--- + TIM1 Channel 2 output polarity + +config STM32H7_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH2OUT + ---help--- + TIM1 Channel 2 output IDLE + +config STM32H7_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH2NOUT + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32H7_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH2NOUT + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32H7_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH3OUT + ---help--- + TIM1 Channel 3 output polarity + +config STM32H7_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH3OUT + ---help--- + TIM1 Channel 3 output IDLE + +config STM32H7_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH3NOUT + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32H7_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH3NOUT + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32H7_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH4OUT + ---help--- + TIM1 Channel 4 output polarity + +config STM32H7_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH4OUT + ---help--- + TIM1 Channel 4 output IDLE + +config STM32H7_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH5OUT + ---help--- + TIM1 Channel 5 output polarity + +config STM32H7_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH5OUT + ---help--- + TIM1 Channel 5 output IDLE + +config STM32H7_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH6OUT + ---help--- + TIM1 Channel 6 output polarity + +config STM32H7_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM1_CH6OUT + ---help--- + TIM1 Channel 6 output IDLE + +config STM32H7_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH1OUT + ---help--- + TIM2 Channel 1 output polarity + +config STM32H7_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH1OUT + ---help--- + TIM2 Channel 1 output IDLE + +config STM32H7_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH2OUT + ---help--- + TIM2 Channel 2 output polarity + +config STM32H7_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH2OUT + ---help--- + TIM2 Channel 2 output IDLE + +config STM32H7_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH3OUT + ---help--- + TIM2 Channel 3 output polarity + +config STM32H7_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH3OUT + ---help--- + TIM2 Channel 3 output IDLE + +config STM32H7_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH4OUT + ---help--- + TIM2 Channel 4 output polarity + +config STM32H7_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM2_CH4OUT + ---help--- + TIM2 Channel 4 output IDLE + +config STM32H7_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH1OUT + ---help--- + TIM3 Channel 1 output polarity + +config STM32H7_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH1OUT + ---help--- + TIM3 Channel 1 output IDLE + +config STM32H7_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH2OUT + ---help--- + TIM3 Channel 2 output polarity + +config STM32H7_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH2OUT + ---help--- + TIM3 Channel 2 output IDLE + +config STM32H7_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH3OUT + ---help--- + TIM3 Channel 3 output polarity + +config STM32H7_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH3OUT + ---help--- + TIM3 Channel 3 output IDLE + +config STM32H7_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH4OUT + ---help--- + TIM3 Channel 4 output polarity + +config STM32H7_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM3_CH4OUT + ---help--- + TIM3 Channel 4 output IDLE + +config STM32H7_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH1OUT + ---help--- + TIM4 Channel 1 output polarity + +config STM32H7_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH1OUT + ---help--- + TIM4 Channel 1 output IDLE + +config STM32H7_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH2OUT + ---help--- + TIM4 Channel 2 output polarity + +config STM32H7_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH2OUT + ---help--- + TIM4 Channel 2 output IDLE + +config STM32H7_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH3OUT + ---help--- + TIM4 Channel 3 output polarity + +config STM32H7_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH3OUT + ---help--- + TIM4 Channel 3 output IDLE + +config STM32H7_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH4OUT + ---help--- + TIM4 Channel 4 output polarity + +config STM32H7_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM4_CH4OUT + ---help--- + TIM4 Channel 4 output IDLE + +config STM32H7_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH1OUT + ---help--- + TIM5 Channel 1 output polarity + +config STM32H7_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH1OUT + ---help--- + TIM5 Channel 1 output IDLE + +config STM32H7_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH2OUT + ---help--- + TIM5 Channel 2 output polarity + +config STM32H7_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH2OUT + ---help--- + TIM5 Channel 2 output IDLE + +config STM32H7_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH3OUT + ---help--- + TIM5 Channel 3 output polarity + +config STM32H7_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH3OUT + ---help--- + TIM5 Channel 3 output IDLE + +config STM32H7_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH4OUT + ---help--- + TIM5 Channel 4 output polarity + +config STM32H7_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM5_CH4OUT + ---help--- + TIM5 Channel 4 output IDLE + +config STM32H7_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH1OUT + ---help--- + TIM8 Channel 1 output polarity + +config STM32H7_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH1OUT + ---help--- + TIM8 Channel 1 output IDLE + +config STM32H7_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH1NOUT + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32H7_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH1NOUT + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32H7_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH2OUT + ---help--- + TIM8 Channel 2 output polarity + +config STM32H7_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH2OUT + ---help--- + TIM8 Channel 2 output IDLE + +config STM32H7_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH2NOUT + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32H7_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH2NOUT + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32H7_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH3OUT + ---help--- + TIM8 Channel 3 output polarity + +config STM32H7_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH3OUT + ---help--- + TIM8 Channel 3 output IDLE + +config STM32H7_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH3NOUT + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32H7_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH3NOUT + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32H7_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH4OUT + ---help--- + TIM8 Channel 4 output polarity + +config STM32H7_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH4OUT + ---help--- + TIM8 Channel 4 output IDLE + +config STM32H7_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH5OUT + ---help--- + TIM8 Channel 5 output polarity + +config STM32H7_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH5OUT + ---help--- + TIM8 Channel 5 output IDLE + +config STM32H7_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH6OUT + ---help--- + TIM8 Channel 6 output polarity + +config STM32H7_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM8_CH6OUT + ---help--- + TIM8 Channel 6 output IDLE + +config STM32H7_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM12_CH1OUT + ---help--- + TIM12 Channel 1 output polarity + +config STM32H7_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM12_CH1OUT + ---help--- + TIM12 Channel 1 output IDLE + +config STM32H7_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM12_CH2OUT + ---help--- + TIM12 Channel 2 output polarity + +config STM32H7_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM12_CH2OUT + ---help--- + TIM12 Channel 2 output IDLE + +config STM32H7_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM13_CH1OUT + ---help--- + TIM13 Channel 1 output polarity + +config STM32H7_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM13_CH1OUT + ---help--- + TIM13 Channel 1 output IDLE + +config STM32H7_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM14_CH1OUT + ---help--- + TIM14 Channel 1 output polarity + +config STM32H7_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM14_CH1OUT + ---help--- + TIM14 Channel 1 output IDLE + +config STM32H7_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH1OUT + ---help--- + TIM15 Channel 1 output polarity + +config STM32H7_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH1OUT + ---help--- + TIM15 Channel 1 output IDLE + +config STM32H7_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH1NOUT + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32H7_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH1NOUT + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32H7_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH2OUT + ---help--- + TIM15 Channel 2 output polarity + +config STM32H7_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH2OUT + ---help--- + TIM15 Channel 2 output IDLE + +config STM32H7_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH2NOUT + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32H7_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM15_CH2NOUT + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32H7_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM16_CH1OUT + ---help--- + TIM16 Channel 1 output polarity + +config STM32H7_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM16_CH1OUT + ---help--- + TIM16 Channel 1 output IDLE + +config STM32H7_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + default 0 + range 0 1 + depends on STM32H7_TIM17_CH1OUT + ---help--- + TIM17 Channel 1 output polarity + +config STM32H7_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + default 0 + range 0 1 + depends on STM32H7_TIM17_CH1OUT + ---help--- + TIM17 Channel 1 output IDLE + +endmenu #STM32 TIMx Outputs Configuration + endmenu # Timer Configuration menu "Ethernet MAC configuration" diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index cad59ce82e6..6047e2a8e83 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -130,6 +130,10 @@ ifeq ($(CONFIG_STM32H7_TIM),y) CHIP_CSRCS += stm32_tim.c endif +ifeq ($(CONFIG_STM32H7_PWM),y) +CHIP_CSRCS += stm32_pwm.c +endif + ifeq ($(CONFIG_STM32H7_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32_tim.h index bed1c75eb83..2ca0e169f5c 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h7/hardware/stm32_tim.h @@ -44,10 +44,1115 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X3XX) -# include "hardware/stm32h7x3xx_tim.h" -#else -# error "Unsupported STM32 H7 sub family" -#endif +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* The STM32H7 family uses STM32 TIMER IP version 2 */ + +#define HAVE_IP_TIMERS_V2 1 + +/* Register Offsets *********************************************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ + +/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 + * timers are 16-bit except for TIM2 and 5 are 32-bit + * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 + */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2, 5 only) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ + +/* Advanced Timers - TIM1 and TIM8 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32 -bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit cnt in lower 16 bit ) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (16-bit) */ +#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (16-bit) */ +#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (16-bit) */ +#define STM32_ATIM_TISEL_OFFSET 0x0068 /* Timer input selection register (32-bit) */ + +/* Register Addresses *******************************************************************************/ + +/* Advanced Timers - TIM1 and TIM8 */ + +# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM1_AF1 (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) +# define STM32_TIM1_TISEL (STM32_TIM1_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM8_AF1 (STM32_TIM8_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM8_AF2 (STM32_TIM8_BASE+STM32_ATIM_AF2_OFFSET) +# define STM32_TIM8_TISEL (STM32_TIM8_BASE+STM32_ATIM_TISEL_OFFSET) + +/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. + * All timers are 16-bit except for TIM2 and 5 are 32-bit + */ + +# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM2_AF1 (STM32_TIM2_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM2_AF2 (STM32_TIM2_BASE+STM32_ATIM_AF2_OFFSET) +# define STM32_TIM2_TISEL (STM32_TIM2_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM3_AF1 (STM32_TIM3_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM3_AF2 (STM32_TIM3_BASE+STM32_ATIM_AF2_OFFSET) +# define STM32_TIM3_TISEL (STM32_TIM3_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM4_AF1 (STM32_TIM4_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM4_AF2 (STM32_TIM4_BASE+STM32_ATIM_AF2_OFFSET) +# define STM32_TIM4_TISEL (STM32_TIM4_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM5_AF1 (STM32_TIM5_BASE+STM32_ATIM_AF1_OFFSET) +# define STM32_TIM5_AF2 (STM32_TIM5_BASE+STM32_ATIM_AF2_OFFSET) +# define STM32_TIM5_TISEL (STM32_TIM5_BASE+STM32_ATIM_TISEL_OFFSET) + +/* 16-bit General Timers - TIM12-14 without dma */ + +# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM12_CR2 (STM32_TIM12_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM12_SMCR (STM32_TIM12_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM12_TISEL (STM32_TIM12_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM13_TISEL (STM32_TIM13_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM14_TISEL (STM32_TIM14_BASE+STM32_ATIM_TISEL_OFFSET) + +/* 16-bit General Timers - TIM15-17 */ + +# define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +# define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM15_AF1 (STM32_TIM15_BASE+STM32_GTIM_AF1_OFFSET) +# define STM32_TIM15_TISEL (STM32_TIM15_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +# define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +# define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM16_AF1 (STM32_TIM16_BASE+STM32_GTIM_AF1_OFFSET) +# define STM32_TIM16_TISEL (STM32_TIM16_BASE+STM32_ATIM_TISEL_OFFSET) + +# define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +# define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +# define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) +# define STM32_TIM17_AF1 (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET) +# define STM32_TIM17_TISEL (STM32_TIM17_BASE+STM32_ATIM_TISEL_OFFSET) + +/* Basic Timers - TIM6 and TIM7 */ + +# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) + +# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) + +/* Register Bitfield Definitions ********************************************************************/ + +/* Control register 1 */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ +#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ +# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ +# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ + +/* Slave mode control register */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ + +/* Status register */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ +#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ +#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ + +/* Event generation register */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ + +/* Capture/compare mode register 1 -- Output compare mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0) /* 0000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (1) /* 0001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (2) /* 0010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (4) /* 0100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (5) /* 0101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (6) /* 0110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (7) /* 0111: PWM mode 2 */ +#define ATIM_CCMR_MODE_OPM1 (8) /* 1000: Retrigerrable OPM mode 1 */ +#define ATIM_CCMR_MODE_OPM2 (9) /* 1001: Retrigerrable OPM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ + +/* Capture/compare mode register 1 -- Input capture mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* Capture/compare mode register 2 - Input Capture Mode */ + + /* Bits 1-0:(same as output compare mode) */ +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + +/* Capture/compare mode register 3 -- Output compare mode */ + +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ +#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ +#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ + +/* Capture/compare enable register */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ +#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ +#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ +#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ +#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ + +/* 16-bit counter register */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* Repetition counter register */ + +#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ +#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) + +#define ATIM_RCR_REP_MAX 65536 + +/* Capture/compare registers (CCR) */ + +#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ +#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ +#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ + +#define ATIM_CCR_MASK (0xffff) + +/* Alternate function option register 1 (TIMx_AF1) */ + +#define ATIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ +#define ATIM_AF1_BKDFBKE (1 << 8) /* Bit 8: BRK DFSDM_BREAK[0] enable */ +#define ATIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ + +/* Alternate function option register 2 (TIMx_AF2) */ + +#define ATIM_AF1_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ +#define ATIM_AF1_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */ +#define ATIM_AF1_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ + +/* Break and dead-time register */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ + +/* DMA control register */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Control register 1 (TIM2-5 and TIM9-14) */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ +#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ +# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ +#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ +# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ +# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ +#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ + +/* Control register 2 (TIM2-5, TIM9-12) */ + +#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ +#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ +#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ +# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ +# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ +#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ +#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ +#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ + +/* Slave mode control register (TIM2-5) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ +#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ +#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ +# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ +# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ +# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ +# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ +#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ +#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ +#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ + +/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ +#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ + +/* Status register */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ +#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ + +/* Event generation register (TIM2-5 and TIM9-14) */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ +#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ +#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ + +/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ + +/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ +#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ + +/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ + + /* Bits 1-0 (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ +#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ +#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ + +/* 16-bit counter register */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) + +/* DMA control register */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) + +/* Timer 2/5 option register */ + +#define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ +#define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) +# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ + +#define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) +# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ +# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ +# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ +# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ + +#define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +#define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) +# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ +# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ + +/* Control register 1 */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ + +/* Control register 2 */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* DMA/Interrupt enable register */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* Status register */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ + +/* Event generation register */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h index 223a90bccef..1367baba5e9 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h @@ -1143,30 +1143,30 @@ #define GPIO_TIM1_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) #define GPIO_TIM1_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9) #define GPIO_TIM1_CH1OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1) -#define GPIO_TIM1_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) -#define GPIO_TIM1_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) -#define GPIO_TIM1_CH1N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) -#define GPIO_TIM1_CH1N_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTK|GPIO_PIN0) +#define GPIO_TIM1_CH1NOUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM1_CH1NOUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13) +#define GPIO_TIM1_CH1NOUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8) +#define GPIO_TIM1_CH1NOUT_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTK|GPIO_PIN0) #define GPIO_TIM1_CH2IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9) #define GPIO_TIM1_CH2IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11) #define GPIO_TIM1_CH2IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTJ|GPIO_PIN11) #define GPIO_TIM1_CH2OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9) #define GPIO_TIM1_CH2OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11) #define GPIO_TIM1_CH2OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11) -#define GPIO_TIM1_CH2N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0) -#define GPIO_TIM1_CH2N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14) -#define GPIO_TIM1_CH2N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) -#define GPIO_TIM1_CH2N_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN10) +#define GPIO_TIM1_CH2NOUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM1_CH2NOUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM1_CH2NOUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10) +#define GPIO_TIM1_CH2NOUT_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN10) #define GPIO_TIM1_CH3IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10) #define GPIO_TIM1_CH3IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13) #define GPIO_TIM1_CH3IN_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTJ|GPIO_PIN9) #define GPIO_TIM1_CH3OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10) #define GPIO_TIM1_CH3OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13) #define GPIO_TIM1_CH3OUT_3 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9) -#define GPIO_TIM1_CH3N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1) -#define GPIO_TIM1_CH3N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15) -#define GPIO_TIM1_CH3N_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) -#define GPIO_TIM1_CH3N_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN8) +#define GPIO_TIM1_CH3NOUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM1_CH3NOUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM1_CH3NOUT_3 (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12) +#define GPIO_TIM1_CH3NOUT_4 (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN8) #define GPIO_TIM1_CH4IN_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11) #define GPIO_TIM1_CH4IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14) #define GPIO_TIM1_CH4OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) @@ -1276,10 +1276,10 @@ #define GPIO_TIM8_CH1OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) #define GPIO_TIM8_CH1OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5) #define GPIO_TIM8_CH1OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8) -#define GPIO_TIM8_CH1N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) -#define GPIO_TIM8_CH1N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) -#define GPIO_TIM8_CH1N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13) -#define GPIO_TIM8_CH1N_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN9) +#define GPIO_TIM8_CH1NOUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5) +#define GPIO_TIM8_CH1NOUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7) +#define GPIO_TIM8_CH1NOUT_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13) +#define GPIO_TIM8_CH1NOUT_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN9) #define GPIO_TIM8_CH2IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7) #define GPIO_TIM8_CH2IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6) #define GPIO_TIM8_CH2IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTJ|GPIO_PIN10) @@ -1288,21 +1288,21 @@ #define GPIO_TIM8_CH2OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6) #define GPIO_TIM8_CH2OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10) #define GPIO_TIM8_CH2OUT_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN6) -#define GPIO_TIM8_CH2N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) -#define GPIO_TIM8_CH2N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) -#define GPIO_TIM8_CH2N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14) -#define GPIO_TIM8_CH2N_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN11) -#define GPIO_TIM8_CH2N_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN7) +#define GPIO_TIM8_CH2NOUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0) +#define GPIO_TIM8_CH2NOUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14) +#define GPIO_TIM8_CH2NOUT_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14) +#define GPIO_TIM8_CH2NOUT_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN11) +#define GPIO_TIM8_CH2NOUT_5 (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN7) #define GPIO_TIM8_CH3IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8) #define GPIO_TIM8_CH3IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7) #define GPIO_TIM8_CH3IN_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTK|GPIO_PIN0) #define GPIO_TIM8_CH3OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8) #define GPIO_TIM8_CH3OUT_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7) #define GPIO_TIM8_CH3OUT_3 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0) -#define GPIO_TIM8_CH3N_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) -#define GPIO_TIM8_CH3N_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15) -#define GPIO_TIM8_CH3N_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15) -#define GPIO_TIM8_CH3N_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTK|GPIO_PIN1) +#define GPIO_TIM8_CH3NOUT_1 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1) +#define GPIO_TIM8_CH3NOUT_2 (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15) +#define GPIO_TIM8_CH3NOUT_3 (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15) +#define GPIO_TIM8_CH3NOUT_4 (GPIO_ALT|GPIO_AF3|GPIO_PORTK|GPIO_PIN1) #define GPIO_TIM8_CH4IN_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9) #define GPIO_TIM8_CH4IN_2 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2) #define GPIO_TIM8_CH4OUT_1 (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9) @@ -1337,8 +1337,8 @@ #define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2) #define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5) -#define GPIO_TIM15_CH1N_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1) -#define GPIO_TIM15_CH1N_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTE|GPIO_PIN4) +#define GPIO_TIM15_CH1NOUT_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1) +#define GPIO_TIM15_CH1NOUT_2 (GPIO_ALT|GPIO_AF4|GPIO_PORTE|GPIO_PIN4) #define GPIO_TIM15_CH2IN_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3) #define GPIO_TIM15_CH2IN_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6) #define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN3) @@ -1350,8 +1350,8 @@ #define GPIO_TIM16_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6) #define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) #define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6) -#define GPIO_TIM16_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6) -#define GPIO_TIM16_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN8) +#define GPIO_TIM16_CH1NOUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6) +#define GPIO_TIM16_CH1NOUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN8) #define GPIO_TIM17_BKIN_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN5) #define GPIO_TIM17_BKIN_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN6) @@ -1359,8 +1359,8 @@ #define GPIO_TIM17_CH1IN_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7) #define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9) #define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7) -#define GPIO_TIM17_CH1N_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7) -#define GPIO_TIM17_CH1N_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9) +#define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7) +#define GPIO_TIM17_CH1NOUT_2 (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9) /* Trace */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_tim.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_tim.h deleted file mode 100644 index 8804d1d3dba..00000000000 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_tim.h +++ /dev/null @@ -1,1148 +0,0 @@ -/**************************************************************************************************** - * arch/arm/src/stm32h7/hardware/stm32h7x3xx_tim.h - * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Authors: Gregory Nutt - * David Sidrane - * Jukka Laitinen - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_TIM_H -#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_TIM_H - -/**************************************************************************************************** - * Pre-processor Definitions - ****************************************************************************************************/ - -/* Register Offsets *********************************************************************************/ - -/* Basic Timers - TIM6 and TIM7 */ - -#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ - -/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 - * timers are 16-bit except for TIM2 and 5 are 32-bit - * timers TIM9 and 12 are different then TIM10, TIM11, TIM13, and TIM14 - */ - -#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2, 5 only) */ -#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */ -#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */ -#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16 bit and 32-bit on TIM2, 5 only) */ -#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */ -#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */ -#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */ -#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ -#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */ -#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ -#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ - -/* Advanced Timers - TIM1 and TIM8 */ - -#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit*) */ -#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32 -bit) */ -#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit*) */ -#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit*) */ -#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit*) */ -#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit*) */ -#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit cnt in lower 16 bit ) */ -#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit*) */ -#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ -#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (16-bit) */ -#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (16-bit) */ -#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (16-bit) */ -#define STM32_ATIM_TISEL_OFFSET 0x0068 /* Timer input selection register (32-bit) */ - -/* Register Addresses *******************************************************************************/ - -/* Advanced Timers - TIM1 and TIM8 */ - -# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) -# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) -# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) -# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) -# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) -# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) -# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) -# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) -# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) -# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) -# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) -# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) -# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) -# define STM32_TIM1_AF1 (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET) -# define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) -# define STM32_TIM1_TISEL (STM32_TIM1_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) -# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) -# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) -# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) -# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) -# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) -# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) -# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) -# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) -# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) -# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) -# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) -# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) -# define STM32_TIM8_AF1 (STM32_TIM8_BASE+STM32_ATIM_AF1_OFFSET) -# define STM32_TIM8_AF2 (STM32_TIM8_BASE+STM32_ATIM_AF2_OFFSET) -# define STM32_TIM8_TISEL (STM32_TIM8_BASE+STM32_ATIM_TISEL_OFFSET) - -/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. - * All timers are 16-bit except for TIM2 and 5 are 32-bit - */ - -# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM2_AF1 (STM32_TIM2_BASE+STM32_ATIM_AF1_OFFSET) -# define STM32_TIM2_AF2 (STM32_TIM2_BASE+STM32_ATIM_AF2_OFFSET) -# define STM32_TIM2_TISEL (STM32_TIM2_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM3_AF1 (STM32_TIM3_BASE+STM32_ATIM_AF1_OFFSET) -# define STM32_TIM3_AF2 (STM32_TIM3_BASE+STM32_ATIM_AF2_OFFSET) -# define STM32_TIM3_TISEL (STM32_TIM3_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM4_AF1 (STM32_TIM4_BASE+STM32_ATIM_AF1_OFFSET) -# define STM32_TIM4_AF2 (STM32_TIM4_BASE+STM32_ATIM_AF2_OFFSET) -# define STM32_TIM4_TISEL (STM32_TIM4_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM5_AF1 (STM32_TIM5_BASE+STM32_ATIM_AF1_OFFSET) -# define STM32_TIM5_AF2 (STM32_TIM5_BASE+STM32_ATIM_AF2_OFFSET) -# define STM32_TIM5_TISEL (STM32_TIM5_BASE+STM32_ATIM_TISEL_OFFSET) - -/* 16-bit General Timers - TIM12-14 without dma */ - -# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM12_CR2 (STM32_TIM12_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM12_SMCR (STM32_TIM12_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM12_TISEL (STM32_TIM12_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM13_TISEL (STM32_TIM13_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM14_TISEL (STM32_TIM14_BASE+STM32_ATIM_TISEL_OFFSET) - -/* 16-bit General Timers - TIM15-17 */ - -# define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) -# define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM15_AF1 (STM32_TIM15_BASE+STM32_GTIM_AF1_OFFSET) -# define STM32_TIM15_TISEL (STM32_TIM15_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) -# define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) -# define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM16_AF1 (STM32_TIM16_BASE+STM32_GTIM_AF1_OFFSET) -# define STM32_TIM16_TISEL (STM32_TIM16_BASE+STM32_ATIM_TISEL_OFFSET) - -# define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) -# define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) -# define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) -# define STM32_TIM17_AF1 (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET) -# define STM32_TIM17_TISEL (STM32_TIM17_BASE+STM32_ATIM_TISEL_OFFSET) - -/* Basic Timers - TIM6 and TIM7 */ - -# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) -# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) -# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) -# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) -# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) -# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) -# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) -# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) - -# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) -# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) -# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) -# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) -# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) -# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) -# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) -# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) - -/* Register Bitfield Definitions ********************************************************************/ - -/* Control register 1 */ - -#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ -#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ -#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ -#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) -# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ -#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) -# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ -#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ - -/* Control register 2 */ - -#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ -#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ -#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) -# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ -#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */ -#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ -#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ -#define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) -# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ -# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ -# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ -# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ -# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ - -/* Slave mode control register */ - -#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ -#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) -# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ -#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) -# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ -# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ -# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ -# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ -# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ -#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) -# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ - -/* DMA/Interrupt enable register */ - -#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ - -/* Status register */ - -#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ -#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ -#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ - -/* Event generation register */ - -#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ -#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ - -/* Capture/compare mode register 1 -- Output compare mode */ - -#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define ATIM_CCMR_MODE_FRZN (0) /* 0000: Frozen */ -#define ATIM_CCMR_MODE_CHACT (1) /* 0001: Channel x active on match */ -#define ATIM_CCMR_MODE_CHINACT (2) /* 0010: Channel x inactive on match */ -#define ATIM_CCMR_MODE_OCREFTOG (3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define ATIM_CCMR_MODE_OCREFLO (4) /* 0100: OCxREF forced low */ -#define ATIM_CCMR_MODE_OCREFHI (5) /* 0101: OCxREF forced high */ -#define ATIM_CCMR_MODE_PWM1 (6) /* 0110: PWM mode 1 */ -#define ATIM_CCMR_MODE_PWM2 (7) /* 0111: PWM mode 2 */ -#define ATIM_CCMR_MODE_OPM1 (8) /* 1000: Retrigerrable OPM mode 1 */ -#define ATIM_CCMR_MODE_OPM2 (9) /* 1001: Retrigerrable OPM mode 2 */ -#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ -#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ -#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ -#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ - -/* Capture/compare mode register 1 -- Input capture mode */ - - /* Bits 1-0:(same as output compare mode) */ -#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ -#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode */ - -#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ -#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ - -/* Capture/compare mode register 2 - Input Capture Mode */ - - /* Bits 1-0:(same as output compare mode) */ -#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ -#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - -/* Capture/compare mode register 3 -- Output compare mode */ - -#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ -#define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ -#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ -#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ -#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ -#define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ -#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ -#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ - -/* Capture/compare enable register */ - -#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ -#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ -#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ -#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ -#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ -#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ -#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ -#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ -#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ -#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ -#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */ -#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ -#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ -#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ -#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ - -/* 16-bit counter register */ - -#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) - -/* Repetition counter register */ - -#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ -#define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) - -#define ATIM_RCR_REP_MAX 65536 - -/* Capture/compare registers (CCR) */ - -#define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ -#define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ -#define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ - -#define ATIM_CCR_MASK (0xffff) - -/* Alternate function option register 1 (TIMx_AF1) */ - -#define ATIM_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define ATIM_AF1_BKDFBKE (1 << 8) /* Bit 8: BRK DFSDM_BREAK[0] enable */ -#define ATIM_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ - -/* Alternate function option register 2 (TIMx_AF2) */ - -#define ATIM_AF1_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ -#define ATIM_AF1_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */ -#define ATIM_AF1_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ - -/* Break and dead-time register */ - -#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) -#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) -# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */ -#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define ATIM_BDTR_BKF_MASK (0xf << ATIM_BDTR_BKF_SHIFT) -# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ -#define ATIM_BDTR_BK2F_MASK (0xf << ATIM_BDTR_BK2F_SHIFT) -# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ -# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ - -/* DMA control register */ - -#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) -#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) -# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* Control register 1 (TIM2-5 and TIM9-14) */ - -#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ -#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ -#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ -#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) -# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ -# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ -#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ -#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) -# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ -# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ -# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ -#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ - -/* Control register 2 (TIM2-5, TIM9-12) */ - -#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ -#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ -#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ -#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ -#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) -# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ -# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ -# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ -# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ -#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ -#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ -#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ -#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ - -/* Slave mode control register (TIM2-5) */ - -#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ -#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) -# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ -#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) -# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ -# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ -# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ -# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ -# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ -#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ -#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ -#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) -# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ -#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) -# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ -#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ -#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ - -/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ - -#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ -#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ -#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ -#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ -#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ -#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ -#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ -#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ -#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ -#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ -#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ - -/* Status register */ - -#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ -#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ -#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ -#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ -#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ -#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ -#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ -#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ -#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ -#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ -#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ -#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ - -/* Event generation register (TIM2-5 and TIM9-14) */ - -#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ -#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ -#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ -#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ -#define GTIM_EGR_COMIG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ -#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ -#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ - -/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */ - -#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ -#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ - -/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */ - - /* Bits 1-0 (Same as Output Compare Mode) */ -#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ -#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ - -#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ - - /* Bits 1-0 (Same as Output Compare Mode) */ -#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ -#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */ - -#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define GTIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */ -#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ -#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ -#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ -#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ -#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ -#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ -#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ -#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ -#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ -#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ -#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ -#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */ - -/* 16-bit counter register */ - -#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) - -/* DMA control register */ - -#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) -#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) - -/* Timer 2/5 option register */ - -#define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ -#define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) -# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ -# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ -# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ -# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ - -#define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ -#define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) -# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ -# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ -# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ -# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ - -#define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ -#define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) -# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ -# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ - -/* Control register 1 */ - -#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ -#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ - -/* Control register 2 */ - -#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) -# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ - -/* DMA/Interrupt enable register */ - -#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ - -/* Status register */ - -#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ - -/* Event generation register */ - -#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ - -#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_TIM_H */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c new file mode 100644 index 00000000000..f74afda363f --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -0,0 +1,4397 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32_pwm.c + * + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience + * Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "stm32_pwm.h" +#include "stm32.h" + +/* This module then only compiles if there is at least one enabled timer + * intended for use with the PWM upper half driver. + * + * It implements support for both: + * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 + * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ + */ + +#ifdef CONFIG_STM32H7_PWM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PWM/Timer Definitions ****************************************************/ + +/* The following definitions are used to identify the various time types. */ + +#define TIMTYPE_BASIC 0 /* Basic timers (no outputs) */ +#define TIMTYPE_GENERAL16 1 /* General 16-bit timers (up, down, up/down)*/ +#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers */ +#define TIMTYPE_COUNTUP16_N 3 /* General 16-bit count-up timers with + * complementary outptus + */ +#define TIMTYPE_GENERAL32 4 /* General 32-bit timers (up, down, up/down)*/ +#define TIMTYPE_ADVANCED 5 /* Advanced timers */ + +#define TIMTYPE_TIM1 TIMTYPE_ADVANCED +#define TIMTYPE_TIM2 TIMTYPE_GENERAL32 +#define TIMTYPE_TIM3 TIMTYPE_GENERAL16 +#define TIMTYPE_TIM4 TIMTYPE_GENERAL16 +#define TIMTYPE_TIM5 TIMTYPE_GENERAL32 +#define TIMTYPE_TIM6 TIMTYPE_BASIC +#define TIMTYPE_TIM7 TIMTYPE_BASIC +#define TIMTYPE_TIM8 TIMTYPE_ADVANCED +/* No TIM9-11 */ +#define TIMTYPE_TIM12 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM13 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM14 TIMTYPE_COUNTUP16 +#define TIMTYPE_TIM15 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM16 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ +#define TIMTYPE_TIM17 TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */ + +/* Timer clock source, RCC EN offset, enable bit, + * RCC RST offset, reset bit to use + * + * TODO: simplify this and move somewhere else. + */ + +#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +#define TIMRCCEN_TIM1 STM32_RCC_APB2ENR +#define TIMEN_TIM1 RCC_APB2ENR_TIM1EN +#define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR +#define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST +#define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +#define TIMRCCEN_TIM2 STM32_RCC_APB1LENR +#define TIMEN_TIM2 RCC_APB1LENR_TIM2EN +#define TIMRCCRST_TIM2 STM32_RCC_APB1LRSTR +#define TIMRST_TIM2 RCC_APB1LRSTR_TIM2RST +#define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +#define TIMRCCEN_TIM3 STM32_RCC_APB1LENR +#define TIMEN_TIM3 RCC_APB1LENR_TIM3EN +#define TIMRCCRST_TIM3 STM32_RCC_APB1LRSTR +#define TIMRST_TIM3 RCC_APB1LRSTR_TIM3RST +#define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +#define TIMRCCEN_TIM4 STM32_RCC_APB1LENR +#define TIMEN_TIM4 RCC_APB1LENR_TIM4EN +#define TIMRCCRST_TIM4 STM32_RCC_APB1LRSTR +#define TIMRST_TIM4 RCC_APB1LRSTR_TIM4RST +#define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +#define TIMRCCEN_TIM5 STM32_RCC_APB1LENR +#define TIMEN_TIM5 RCC_APB1LENR_TIM5EN +#define TIMRCCRST_TIM5 STM32_RCC_APB1LRSTR +#define TIMRST_TIM5 RCC_APB1LRSTR_TIM5RST +#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +#define TIMRCCEN_TIM8 STM32_RCC_APB2ENR +#define TIMEN_TIM8 RCC_APB2ENR_TIM8EN +#define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR +#define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST +#define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +#define TIMRCCEN_TIM12 STM32_RCC_APB1LENR +#define TIMEN_TIM12 RCC_APB1LENR_TIM12EN +#define TIMRCCRST_TIM12 STM32_RCC_APB1LRSTR +#define TIMRST_TIM12 RCC_APB1LRSTR_TIM12RST +#define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +#define TIMRCCEN_TIM13 STM32_RCC_APB1LENR +#define TIMEN_TIM13 RCC_APB1LENR_TIM13EN +#define TIMRCCRST_TIM13 STM32_RCC_APB1LRSTR +#define TIMRST_TIM13 RCC_APB1LRSTR_TIM13RST +#define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +#define TIMRCCEN_TIM14 STM32_RCC_APB1LENR +#define TIMEN_TIM14 RCC_APB1LENR_TIM14EN +#define TIMRCCRST_TIM14 STM32_RCC_APB1LRSTR +#define TIMRST_TIM14 RCC_APB1LRSTR_TIM14RST +#define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN +#define TIMRCCEN_TIM15 STM32_RCC_APB2ENR +#define TIMEN_TIM15 RCC_APB2ENR_TIM15EN +#define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR +#define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST +#define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN +#define TIMRCCEN_TIM16 STM32_RCC_APB2ENR +#define TIMEN_TIM16 RCC_APB2ENR_TIM16EN +#define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR +#define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST +#define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN +#define TIMRCCEN_TIM17 STM32_RCC_APB2ENR +#define TIMEN_TIM17 RCC_APB2ENR_TIM71EN +#define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR +#define TIMRST_TIM17 RCC_APB2RSTR_TIM17RST + +/* Default GPIO pins state */ + +#define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) + +/* Advanced Timer support + * NOTE: TIM15-17 are not ADVTIM but they support most of the + * ADVTIM functionality. The main difference is the number of + * supported capture/compare. + */ + +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) +# define HAVE_ADVTIM +#else +# undef HAVE_ADVTIM +#endif + +/* Pulsecount support */ + +#ifdef CONFIG_PWM_PULSECOUNT +# ifndef HAVE_ADVTIM +# error "PWM_PULSECOUNT requires HAVE_ADVTIM" +# endif +# if defined(CONFIG_STM32H7_TIM1_PWM) || defined(CONFIG_STM32H7_TIM8_PWM) +# define HAVE_PWM_INTERRUPT +# endif +#endif + +/* Synchronisation support */ + +#ifdef CONFIG_STM32H7_PWM_TRGO +# define HAVE_TRGO +#endif + +/* Break support */ + +#if defined(CONFIG_STM32H7_TIM1_BREAK1) || defined(CONFIG_STM32H7_TIM1_BREAK2) || \ + defined(CONFIG_STM32H7_TIM8_BREAK1) || defined(CONFIG_STM32H7_TIM8_BREAK2) || \ + defined(CONFIG_STM32H7_TIM15_BREAK1) || defined(CONFIG_STM32H7_TIM16_BREAK1) || \ + defined(CONFIG_STM32H7_TIM17_BREAK1) +# defined HAVE_BREAK +#endif + +/* Debug ********************************************************************/ + +#ifdef CONFIG_DEBUG_PWM_INFO +# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) +#else +# define pwm_dumpgpio(p,m) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* PWM output configuration */ + +struct stm32_pwm_out_s +{ + uint8_t in_use:1; /* Output in use */ + uint8_t pol:1; /* Polarity. Default: positive */ + uint8_t idle:1; /* Idle state. Default: inactive */ + uint8_t _res:5; /* Reserved */ + uint32_t pincfg; /* Output pin configuration */ +}; + +/* PWM break configuration */ + +#ifdef HAVE_BREAK +struct stm32_pwm_break_s +{ + uint8_t en1:1; /* Break 1 enable */ + uint8_t pol1:1; /* Break 1 polarity */ + uint8_t _res:6; /* Reserved */ +#ifdef HAVE_IP_TIMERS_V2 + uint8_t en2:1; /* Break 2 enable */ + uint8_t pol2:1; /* Break 2 polarity */ + uint8_t flt2:6; /* Break 2 filter */ +#endif +}; +#endif + +/* PWM channel configuration */ + +struct stm32_pwmchan_s +{ + uint8_t channel:4; /* Timer output channel: {1,..4} */ + uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ + struct stm32_pwm_out_s out1; /* PWM output configuration */ +#ifdef HAVE_BREAK + struct stm32_pwm_break_s brk; /* PWM break configuration */ +#endif +#ifdef HAVE_PWM_COMPLEMENTARY + struct stm32_pwm_out_s out2; /* PWM complementary output configuration */ +#endif +}; + +/* This structure represents the state of one PWM timer */ + +struct stm32_pwmtimer_s +{ + FAR const struct pwm_ops_s *ops; /* PWM operations */ +#ifdef CONFIG_STM32H7_PWM_LL_OPS + FAR const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ +#endif + FAR struct stm32_pwmchan_s *channels; /* Channels configuration */ + uint8_t timid:5; /* Timer ID {1,...,17} */ + uint8_t chan_num:3; /* Number of configured channels */ + uint8_t timtype:3; /* See the TIMTYPE_* definitions */ + uint8_t mode:3; /* Timer mode (see stm32_pwm_tim_mode_e) */ + uint8_t lock:2; /* TODO: Lock configuration */ + uint8_t t_dts:3; /* Clock division for t_DTS */ + uint8_t _res:5; /* Reserved */ +#ifdef HAVE_PWM_COMPLEMENTARY + uint8_t deadtime; /* Dead-time value */ +#endif +#ifdef HAVE_TRGO + uint8_t trgo; /* TRGO configuration: + * 4 LSB = TRGO, 4 MSB = TRGO2 + */ +#endif +#ifdef CONFIG_PWM_PULSECOUNT + uint8_t irq; /* Timer update IRQ */ + uint8_t prev; /* The previous value of the RCR (pre-loaded) */ + uint8_t curr; /* The current value of the RCR (pre-loaded) */ + uint32_t count; /* Remaining pluse count */ +#else + uint32_t frequency; /* Current frequency setting */ +#endif + uint32_t base; /* The base address of the timer */ + uint32_t pclk; /* The frequency of the peripheral clock + * that drives the timer module. + */ +#ifdef CONFIG_PWM_PULSECOUNT + FAR void *handle; /* Handle used for upper-half callback */ +#endif +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* Register access */ + +static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, + uint32_t value); +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, + uint32_t clearbits, uint32_t setbits); + +#ifdef CONFIG_DEBUG_PWM_INFO +static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg); +#else +# define pwm_dumpregs(priv,msg) +#endif + +/* Timer management */ + +static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev, + uint32_t frequency); +static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, + uint8_t channel, uint32_t mode); +static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv); +static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv, + uint8_t channel); +static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, + uint16_t outputs, bool state); +static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev); +static int pwm_soft_break(FAR struct pwm_lowerhalf_s *dev, bool state); +static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index, + uint32_t ccr); +static int pwm_arr_update(FAR struct pwm_lowerhalf_s *dev, uint32_t arr); +static uint32_t pwm_arr_get(FAR struct pwm_lowerhalf_s *dev); +static int pwm_duty_update(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, + ub16_t duty); +static int pwm_timer_enable(FAR struct pwm_lowerhalf_s *dev, bool state); + +#ifdef HAVE_ADVTIM +static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv); +#endif +#ifdef HAVE_TRGO +static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv, + uint8_t trgo); +#endif +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +static int pwm_deadtime_update(FAR struct pwm_lowerhalf_s *dev, uint8_t dt); +#endif +#ifdef CONFIG_STM32H7_PWM_LL_OPS +static uint32_t pwm_ccr_get(FAR struct pwm_lowerhalf_s *dev, uint8_t index); +#endif + +#ifdef CONFIG_PWM_PULSECOUNT +static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev); +#else +static int pwm_configure(FAR struct pwm_lowerhalf_s *dev); +#endif +#ifdef CONFIG_PWM_PULSECOUNT +static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info); +#else +static int pwm_timer(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info); +#endif +#ifdef HAVE_PWM_INTERRUPT +static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev); +# ifdef CONFIG_STM32H7_TIM1_PWM +static int pwm_tim1interrupt(int irq, void *context, FAR void *arg); +# endif +# ifdef CONFIG_STM32H7_TIM8_PWM +static int pwm_tim8interrupt(int irq, void *context, FAR void *arg); +# endif +static uint8_t pwm_pulsecount(uint32_t count); +#endif + +/* PWM driver methods */ + +static int pwm_setup(FAR struct pwm_lowerhalf_s *dev); +static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev); + +#ifdef CONFIG_PWM_PULSECOUNT +static int pwm_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info, + FAR void *handle); +#else +static int pwm_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info); +#endif + +static int pwm_stop(FAR struct pwm_lowerhalf_s *dev); +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver. + */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, +}; + +#ifdef CONFIG_STM32H7_PWM_LL_OPS +static const struct stm32_pwm_ops_s g_llpwmops = +{ + .configure = pwm_configure, + .soft_break = pwm_soft_break, + .ccr_update = pwm_ccr_update, + .mode_update = pwm_mode_configure, + .ccr_get = pwm_ccr_get, + .arr_update = pwm_arr_update, + .arr_get = pwm_arr_get, + .outputs_enable = pwm_outputs_enable, + .soft_update = pwm_soft_update, + .freq_update = pwm_frequency_update, + .tim_enable = pwm_timer_enable, +# ifdef CONFIG_DEBUG_PWM_INFO + .dump_regs = pwm_dumpregs, +# endif +# ifdef HAVE_PWM_COMPLEMENTARY + .dt_update = pwm_deadtime_update, +# endif +}; +#endif + +#ifdef CONFIG_STM32H7_TIM1_PWM + +static struct stm32_pwmchan_s g_pwm1channels[] = +{ + /* TIM1 has 4 channels, 4 complementary */ + +#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM1_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32H7_TIM1_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32H7_TIM1_BRK1POL, +#endif +#ifdef CONFIG_STM32H7_TIM1_BREAK2 + .en2 = 1, + .pol2 = CONFIG_STM32H7_TIM1_BRK2POL, + .flt2 = CONFIG_STM32H7_TIM1_BRK2FLT, +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH1POL, + .idle = CONFIG_STM32H7_TIM1_CH1IDLE, + .pincfg = PWM_TIM1_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH1NPOL, + .idle = CONFIG_STM32H7_TIM1_CH1NIDLE, + .pincfg = PWM_TIM1_CH1NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM1_CH2MODE, +#ifdef CONFIG_STM32H7_TIM1_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH2POL, + .idle = CONFIG_STM32H7_TIM1_CH2IDLE, + .pincfg = PWM_TIM1_CH2CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CH2NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH2NPOL, + .idle = CONFIG_STM32H7_TIM1_CH2NIDLE, + .pincfg = PWM_TIM1_CH2NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32H7_TIM1_CH3MODE, +#ifdef CONFIG_STM32H7_TIM1_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH3POL, + .idle = CONFIG_STM32H7_TIM1_CH3IDLE, + .pincfg = PWM_TIM1_CH3CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CH3NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH3NPOL, + .idle = CONFIG_STM32H7_TIM1_CH3NIDLE, + .pincfg = PWM_TIM1_CH3NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32H7_TIM1_CH4MODE, +#ifdef CONFIG_STM32H7_TIM1_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH4POL, + .idle = CONFIG_STM32H7_TIM1_CH4IDLE, + .pincfg = PWM_TIM1_CH4CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 + { + .channel = 5, + .mode = CONFIG_STM32H7_TIM1_CH5MODE, +#ifdef CONFIG_STM32H7_TIM1_CH5OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH5POL, + .idle = CONFIG_STM32H7_TIM1_CH5IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 + { + .channel = 6, + .mode = CONFIG_STM32H7_TIM1_CH6MODE, +#ifdef CONFIG_STM32H7_TIM1_CH6OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM1_CH6POL, + .idle = CONFIG_STM32H7_TIM1_CH6IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm1dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 1, + .chan_num = PWM_TIM1_NCHANNELS, + .channels = g_pwm1channels, + .timtype = TIMTYPE_TIM1, + .mode = CONFIG_STM32H7_TIM1_MODE, + .lock = CONFIG_STM32H7_TIM1_LOCK, + .t_dts = CONFIG_STM32H7_TIM1_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32H7_TIM1_DEADTIME, +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) + .trgo = STM32_TIM1_TRGO, +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM1UP, +#endif + .base = STM32_TIM1_BASE, + .pclk = TIMCLK_TIM1, +}; +#endif /* CONFIG_STM32H7_TIM1_PWM */ + +#ifdef CONFIG_STM32H7_TIM2_PWM + +static struct stm32_pwmchan_s g_pwm2channels[] = +{ + /* TIM2 has 4 channels */ + +#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM2_CH1MODE, +#ifdef CONFIG_STM32H7_TIM2_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM2_CH1POL, + .idle = CONFIG_STM32H7_TIM2_CH1IDLE, + .pincfg = PWM_TIM2_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM2_CH2MODE, +#ifdef CONFIG_STM32H7_TIM2_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM2_CH2POL, + .idle = CONFIG_STM32H7_TIM2_CH2IDLE, + .pincfg = PWM_TIM2_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32H7_TIM2_CH3MODE, +#ifdef CONFIG_STM32H7_TIM2_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM2_CH3POL, + .idle = CONFIG_STM32H7_TIM2_CH3IDLE, + .pincfg = PWM_TIM2_CH3CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32H7_TIM2_CH4MODE, +#ifdef CONFIG_STM32H7_TIM2_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM2_CH4POL, + .idle = CONFIG_STM32H7_TIM2_CH4IDLE, + .pincfg = PWM_TIM2_CH4CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm2dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 2, + .chan_num = PWM_TIM2_NCHANNELS, + .channels = g_pwm2channels, + .timtype = TIMTYPE_TIM2, + .mode = CONFIG_STM32H7_TIM2_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) + .trgo = STM32_TIM2_TRGO, +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM2, +#endif + .base = STM32_TIM2_BASE, + .pclk = TIMCLK_TIM2, +}; +#endif /* CONFIG_STM32H7_TIM2_PWM */ + +#ifdef CONFIG_STM32H7_TIM3_PWM + +static struct stm32_pwmchan_s g_pwm3channels[] = +{ + /* TIM3 has 4 channels */ + +#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM3_CH1MODE, +#ifdef CONFIG_STM32H7_TIM3_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM3_CH1POL, + .idle = CONFIG_STM32H7_TIM3_CH1IDLE, + .pincfg = PWM_TIM3_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM3_CH2MODE, +#ifdef CONFIG_STM32H7_TIM3_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM3_CH2POL, + .idle = CONFIG_STM32H7_TIM3_CH2IDLE, + .pincfg = PWM_TIM3_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32H7_TIM3_CH3MODE, +#ifdef CONFIG_STM32H7_TIM3_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM3_CH3POL, + .idle = CONFIG_STM32H7_TIM3_CH3IDLE, + .pincfg = PWM_TIM3_CH3CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32H7_TIM3_CH4MODE, +#ifdef CONFIG_STM32H7_TIM3_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM3_CH4POL, + .idle = CONFIG_STM32H7_TIM3_CH4IDLE, + .pincfg = PWM_TIM3_CH4CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm3dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 3, + .chan_num = PWM_TIM3_NCHANNELS, + .channels = g_pwm3channels, + .timtype = TIMTYPE_TIM3, + .mode = CONFIG_STM32H7_TIM3_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) + .trgo = STM32_TIM3_TRGO, +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM3, +#endif + .base = STM32_TIM3_BASE, + .pclk = TIMCLK_TIM3, +}; +#endif /* CONFIG_STM32H7_TIM3_PWM */ + +#ifdef CONFIG_STM32H7_TIM4_PWM + +static struct stm32_pwmchan_s g_pwm4channels[] = +{ + /* TIM4 has 4 channels */ + +#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM4_CH1MODE, +#ifdef CONFIG_STM32H7_TIM4_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM4_CH1POL, + .idle = CONFIG_STM32H7_TIM4_CH1IDLE, + .pincfg = PWM_TIM4_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM4_CH2MODE, +#ifdef CONFIG_STM32H7_TIM4_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM4_CH2POL, + .idle = CONFIG_STM32H7_TIM4_CH2IDLE, + .pincfg = PWM_TIM4_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32H7_TIM4_CH3MODE, +#ifdef CONFIG_STM32H7_TIM4_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM4_CH3POL, + .idle = CONFIG_STM32H7_TIM4_CH3IDLE, + .pincfg = PWM_TIM4_CH3CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32H7_TIM4_CH4MODE, +#ifdef CONFIG_STM32H7_TIM4_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM4_CH4POL, + .idle = CONFIG_STM32H7_TIM4_CH4IDLE, + .pincfg = PWM_TIM4_CH4CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm4dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 4, + .chan_num = PWM_TIM4_NCHANNELS, + .channels = g_pwm4channels, + .timtype = TIMTYPE_TIM4, + .mode = CONFIG_STM32H7_TIM4_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) + .trgo = STM32_TIM4_TRGO, +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM4, +#endif + .base = STM32_TIM4_BASE, + .pclk = TIMCLK_TIM4, +}; +#endif /* CONFIG_STM32H7_TIM4_PWM */ + +#ifdef CONFIG_STM32H7_TIM5_PWM + +static struct stm32_pwmchan_s g_pwm5channels[] = +{ + /* TIM5 has 4 channels */ + +#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM5_CH1MODE, +#ifdef CONFIG_STM32H7_TIM5_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM5_CH1POL, + .idle = CONFIG_STM32H7_TIM5_CH1IDLE, + .pincfg = PWM_TIM5_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM5_CH2MODE, +#ifdef CONFIG_STM32H7_TIM5_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM5_CH2POL, + .idle = CONFIG_STM32H7_TIM5_CH2IDLE, + .pincfg = PWM_TIM5_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32H7_TIM5_CH3MODE, +#ifdef CONFIG_STM32H7_TIM5_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM5_CH3POL, + .idle = CONFIG_STM32H7_TIM5_CH3IDLE, + .pincfg = PWM_TIM5_CH3CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32H7_TIM5_CH4MODE, +#ifdef CONFIG_STM32H7_TIM5_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM5_CH4POL, + .idle = CONFIG_STM32H7_TIM5_CH4IDLE, + .pincfg = PWM_TIM5_CH4CFG, + } +#endif + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm5dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 5, + .chan_num = PWM_TIM5_NCHANNELS, + .channels = g_pwm5channels, + .timtype = TIMTYPE_TIM5, + .mode = CONFIG_STM32H7_TIM5_MODE, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) + .trgo = STM32_TIM5_TRGO +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM5, +#endif + .base = STM32_TIM5_BASE, + .pclk = TIMCLK_TIM5, +}; +#endif /* CONFIG_STM32H7_TIM5_PWM */ + +#ifdef CONFIG_STM32H7_TIM8_PWM + +static struct stm32_pwmchan_s g_pwm8channels[] = +{ + /* TIM8 has 4 channels, 4 complementary */ + +#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM8_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32H7_TIM8_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32H7_TIM8_BRK1POL, +#endif +#ifdef CONFIG_STM32H7_TIM8_BREAK2 + .en2 = 1, + .pol2 = CONFIG_STM32H7_TIM8_BRK2POL, + .flt2 = CONFIG_STM32H7_TIM8_BRK2FLT, +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH1POL, + .idle = CONFIG_STM32H7_TIM8_CH1IDLE, + .pincfg = PWM_TIM8_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH1NPOL, + .idle = CONFIG_STM32H7_TIM8_CH1NIDLE, + .pincfg = PWM_TIM8_CH1NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM8_CH2MODE, +#ifdef CONFIG_STM32H7_TIM8_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH2POL, + .idle = CONFIG_STM32H7_TIM8_CH2IDLE, + .pincfg = PWM_TIM8_CH2CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CH2NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH2NPOL, + .idle = CONFIG_STM32H7_TIM8_CH2NIDLE, + .pincfg = PWM_TIM8_CH2NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 + { + .channel = 3, + .mode = CONFIG_STM32H7_TIM8_CH3MODE, +#ifdef CONFIG_STM32H7_TIM8_CH3OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH3POL, + .idle = CONFIG_STM32H7_TIM8_CH3IDLE, + .pincfg = PWM_TIM8_CH3CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CH3NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH3NPOL, + .idle = CONFIG_STM32H7_TIM8_CH3NIDLE, + .pincfg = PWM_TIM8_CH3NCFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 + { + .channel = 4, + .mode = CONFIG_STM32H7_TIM8_CH4MODE, +#ifdef CONFIG_STM32H7_TIM8_CH4OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH4POL, + .idle = CONFIG_STM32H7_TIM8_CH4IDLE, + .pincfg = PWM_TIM8_CH4CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 + { + .channel = 5, + .mode = CONFIG_STM32H7_TIM8_CH5MODE, +#ifdef CONFIG_STM32H7_TIM8_CH5OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH5POL, + .idle = CONFIG_STM32H7_TIM8_CH5IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 + { + .channel = 6, + .mode = CONFIG_STM32H7_TIM8_CH6MODE, +#ifdef CONFIG_STM32H7_TIM8_CH6OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM8_CH6POL, + .idle = CONFIG_STM32H7_TIM8_CH6IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm8dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 8, + .chan_num = PWM_TIM8_NCHANNELS, + .channels = g_pwm8channels, + .timtype = TIMTYPE_TIM8, + .mode = CONFIG_STM32H7_TIM8_MODE, + .lock = CONFIG_STM32H7_TIM8_LOCK, + .t_dts = CONFIG_STM32H7_TIM8_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32H7_TIM8_DEADTIME, +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) + .trgo = STM32_TIM8_TRGO, +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM8UP, +#endif + .base = STM32_TIM8_BASE, + .pclk = TIMCLK_TIM8, +}; +#endif /* CONFIG_STM32H7_TIM8_PWM */ + +#ifdef CONFIG_STM32H7_TIM12_PWM + +static struct stm32_pwmchan_s g_pwm12channels[] = +{ + /* TIM12 has 2 channels */ + +#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM12_CH1MODE, +#ifdef CONFIG_STM32H7_TIM12_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM12_CH1POL, + .idle = CONFIG_STM32H7_TIM12_CH1IDLE, + .pincfg = PWM_TIM12_CH1CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM12_CH2MODE, +#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM12_CH2POL, + .idle = CONFIG_STM32H7_TIM12_CH2IDLE, + .pincfg = PWM_TIM12_CH2CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm12dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 12, + .chan_num = PWM_TIM12_NCHANNELS, + .channels = g_pwm12channels, + .timtype = TIMTYPE_TIM12, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM12 */ +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM12, +#endif + .base = STM32_TIM12_BASE, + .pclk = TIMCLK_TIM12, +}; +#endif /* CONFIG_STM32H7_TIM12_PWM */ + +#ifdef CONFIG_STM32H7_TIM13_PWM + +static struct stm32_pwmchan_s g_pwm13channels[] = +{ + /* TIM13 has 1 channel */ + +#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM13_CH1MODE, +#ifdef CONFIG_STM32H7_TIM13_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM13_CH1POL, + .idle = CONFIG_STM32H7_TIM13_CH1IDLE, + .pincfg = PWM_TIM13_CH1CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm13dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 13, + .chan_num = PWM_TIM13_NCHANNELS, + .channels = g_pwm13channels, + .timtype = TIMTYPE_TIM13, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM13 */ +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM13, +#endif + .base = STM32_TIM13_BASE, + .pclk = TIMCLK_TIM13, +}; +#endif /* CONFIG_STM32H7_TIM13_PWM */ + +#ifdef CONFIG_STM32H7_TIM14_PWM + +static struct stm32_pwmchan_s g_pwm14channels[] = +{ + /* TIM14 has 1 channel */ + +#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM14_CH1MODE, +#ifdef CONFIG_STM32H7_TIM14_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM14_CH1POL, + .idle = CONFIG_STM32H7_TIM14_CH1IDLE, + .pincfg = PWM_TIM14_CH1CFG, + } +#endif + /* No complementary outputs */ + } +#endif +}; + +static struct stm32_pwmtimer_s g_pwm14dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 14, + .chan_num = PWM_TIM14_NCHANNELS, + .channels = g_pwm14channels, + .timtype = TIMTYPE_TIM14, + .mode = STM32_TIMMODE_COUNTUP, + .lock = 0, /* No lock */ + .t_dts = 0, /* No t_dts */ +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = 0, /* No deadtime */ +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM14 */ +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM14, +#endif + .base = STM32_TIM14_BASE, + .pclk = TIMCLK_TIM14, +}; +#endif /* CONFIG_STM32H7_TIM14_PWM */ + +#ifdef CONFIG_STM32H7_TIM15_PWM + +static struct stm32_pwmchan_s g_pwm15channels[] = +{ + /* TIM15 has 2 channels, 1 complementary */ + +#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM15_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32H7_TIM15_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32H7_TIM15_BRK1POL, +#endif + /* No BREAK2 */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM15_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM15_CH1POL, + .idle = CONFIG_STM32H7_TIM15_CH1IDLE, + .pincfg = PWM_TIM15_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM15_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM15_CH1NPOL, + .idle = CONFIG_STM32H7_TIM15_CH1NIDLE, + .pincfg = PWM_TIM15_CH2CFG, + } +#endif + }, +#endif +#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 + { + .channel = 2, + .mode = CONFIG_STM32H7_TIM15_CH2MODE, +#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM15_CH2POL, + .idle = CONFIG_STM32H7_TIM15_CH2IDLE, + .pincfg = PWM_TIM15_CH2CFG, + } +#endif + /* No complementary outputs */ + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm15dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 15, + .chan_num = PWM_TIM15_NCHANNELS, + .channels = g_pwm15channels, + .timtype = TIMTYPE_TIM15, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32H7_TIM15_LOCK, + .t_dts = CONFIG_STM32H7_TIM15_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32H7_TIM15_DEADTIME, +#endif +#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) + .trgo = STM32_TIM15_TRGO, +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM15, +#endif + .base = STM32_TIM15_BASE, + .pclk = TIMCLK_TIM15, +}; +#endif /* CONFIG_STM32H7_TIM15_PWM */ + +#ifdef CONFIG_STM32H7_TIM16_PWM + +static struct stm32_pwmchan_s g_pwm16channels[] = +{ + /* TIM16 has 1 channel, 1 complementary */ + +#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM16_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32H7_TIM16_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32H7_TIM16_BRK1POL, +#endif + /* No BREAK2 */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM16_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM16_CH1POL, + .idle = CONFIG_STM32H7_TIM16_CH1IDLE, + .pincfg = PWM_TIM16_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM16_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM16_CH1NPOL, + .idle = CONFIG_STM32H7_TIM16_CH1NIDLE, + .pincfg = PWM_TIM16_CH2CFG, + } +#endif + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm16dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 16, + .chan_num = PWM_TIM16_NCHANNELS, + .channels = g_pwm16channels, + .timtype = TIMTYPE_TIM16, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32H7_TIM16_LOCK, + .t_dts = CONFIG_STM32H7_TIM16_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32H7_TIM16_DEADTIME, +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM16 */ +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM16, +#endif + .base = STM32_TIM16_BASE, + .pclk = TIMCLK_TIM16, +}; +#endif /* CONFIG_STM32H7_TIM16_PWM */ + +#ifdef CONFIG_STM32H7_TIM17_PWM + +static struct stm32_pwmchan_s g_pwm17channels[] = +{ + /* TIM17 has 1 channel, 1 complementary */ + +#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 + { + .channel = 1, + .mode = CONFIG_STM32H7_TIM17_CH1MODE, +#ifdef HAVE_BREAK + .brk = + { +#ifdef CONFIG_STM32H7_TIM17_BREAK1 + .en1 = 1, + .pol1 = CONFIG_STM32H7_TIM17_BRK1POL, +#endif + /* No BREAK2 */ + }, +#endif +#ifdef CONFIG_STM32H7_TIM17_CH1OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM17_CH1POL, + .idle = CONFIG_STM32H7_TIM17_CH1IDLE, + .pincfg = PWM_TIM17_CH1CFG, + }, +#endif +#ifdef CONFIG_STM32H7_TIM17_CH1NOUT + .out2 = + { + .in_use = 1, + .pol = CONFIG_STM32H7_TIM17_CH1NPOL, + .idle = CONFIG_STM32H7_TIM17_CH1NIDLE, + .pincfg = PWM_TIM17_CH2CFG, + } +#endif + }, +#endif +}; + +static struct stm32_pwmtimer_s g_pwm17dev = +{ + .ops = &g_pwmops, +#ifdef CONFIG_STM32H7_PWM_LL_OPS + .llops = &g_llpwmops, +#endif + .timid = 17, + .chan_num = PWM_TIM17_NCHANNELS, + .channels = g_pwm17channels, + .timtype = TIMTYPE_TIM17, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32H7_TIM17_LOCK, + .t_dts = CONFIG_STM32H7_TIM17_TDTS, +#ifdef HAVE_PWM_COMPLEMENTARY + .deadtime = CONFIG_STM32H7_TIM17_DEADTIME, +#endif +#if defined(HAVE_TRGO) + .trgo = 0, /* TRGO not supported for TIM17 */ +#endif +#ifdef CONFIG_PWM_PULSECOUNT + .irq = STM32_IRQ_TIM17, +#endif + .base = STM32_TIM17_BASE, + .pclk = TIMCLK_TIM17, +}; +#endif /* CONFIG_STM32H7_TIM17_PWM */ + +/* TODO: support for TIM19,20,21,22 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pwm_reg_is_32bit + ****************************************************************************/ + +static bool pwm_reg_is_32bit(uint8_t timtype, uint32_t offset) +{ + bool ret = false; + + if (timtype == TIMTYPE_GENERAL32) + { + if (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET) + { + ret = true; + } + } +#ifdef HAVE_IP_TIMERS_V2 + else if (timtype == TIMTYPE_ADVANCED) + { + if (offset == STM32_ATIM_CR2_OFFSET || + offset == STM32_ATIM_CCMR1_OFFSET || + offset == STM32_ATIM_CCMR2_OFFSET || + offset == STM32_ATIM_CCER_OFFSET || + offset == STM32_ATIM_BDTR_OFFSET || + offset == STM32_ATIM_CCMR3_OFFSET || + offset == STM32_ATIM_CCR5_OFFSET) + { + ret = true; + } + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: pwm_getreg + * + * Description: + * Read the value of an PWM timer register + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) +{ + uint32_t retval = 0; + + if (pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + retval = getreg32(priv->base + offset); + } + else + { + /* 16-bit register */ + + retval = getreg16(priv->base + offset); + } + + /* Return 32-bit value */ + + return retval; +} + +/**************************************************************************** + * Name: pwm_putreg + * + * Description: + * Read the value of an PWM timer register + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, + uint32_t value) +{ + if (pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + putreg32(value, priv->base + offset); + } + else + { + /* 16-bit register */ + + putreg16((uint16_t)value, priv->base + offset); + } +} + +/**************************************************************************** + * Name: pwm_modifyreg + * + * Description: + * Modify PWM register (32-bit or 16-bit) + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, + uint32_t clearbits, uint32_t setbits) +{ + + if (pwm_reg_is_32bit(priv->timtype, offset) == true) + { + /* 32-bit register */ + + modifyreg32(priv->base + offset, clearbits, setbits); + } + else + { + /* 16-bit register */ + + modifyreg16(priv->base + offset, (uint16_t)clearbits, + (uint16_t)setbits); + } +} + +/**************************************************************************** + * Name: pwm_dumpregs + * + * Description: + * Dump all timer registers. + * + * Input Parameters: + * priv - A reference to the PWM block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_PWM_INFO +static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) +{ + pwminfo("%s:\n", msg); + if (priv->timid == 16 || priv->timid == 17) + { + pwminfo(" CR1: %04x CR2: %04x DIER: %04x\n", + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + } + else + { + pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); + } + + if (priv->timid >= 15 && priv->timid <= 17) + { + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x\n", + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET)); + } + else + { + pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); + } + + /* REVISIT: CNT and ARR may be 32-bits wide */ + + pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); + + if (priv->timid == 1 || priv->timid == 8 || + (priv->timid >= 15 && priv->timid <= 17)) + { + pwminfo(" RCR: %04x BDTR: %04x\n", + pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); + } + + /* REVISIT: CCR1-CCR4 may be 32-bits wide */ + + if (priv->timid == 16 || priv->timid == 17) + { + pwminfo(" CCR1: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET)); + } + else if (priv->timid == 15) + { + pwminfo(" CCR1: %04x CCR2: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET)); + } + else + { + pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); + } + + pwminfo(" DCR: %04x DMAR: %04x\n", + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype == TIMTYPE_ADVANCED) + { + pwminfo(" CCMR3: %04x CCR5: %04x CCR6: %04x\n", + pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET), + pwm_getreg(priv, STM32_ATIM_CCR5_OFFSET), + pwm_getreg(priv, STM32_ATIM_CCR6_OFFSET)); + } +#endif +} +#endif + +/**************************************************************************** + * Name: pwm_ccr_update + ****************************************************************************/ + +static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index, + uint32_t ccr) + +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t offset = 0; + + /* Only ADV timers have CC5 and CC6 */ + +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype != TIMTYPE_ADVANCED && (index == 5 || index == 6)) + { + pwmerr("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } +#endif + + /* REVISIT: start index from 0? */ + + switch (index) + { + case STM32_PWM_CHAN1: + { + offset = STM32_GTIM_CCR1_OFFSET; + break; + } + + case STM32_PWM_CHAN2: + { + offset = STM32_GTIM_CCR2_OFFSET; + break; + } + + case STM32_PWM_CHAN3: + { + offset = STM32_GTIM_CCR3_OFFSET; + break; + } + + case STM32_PWM_CHAN4: + { + offset = STM32_GTIM_CCR4_OFFSET; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: + { + offset = STM32_ATIM_CCR5_OFFSET; + break; + } + + case STM32_PWM_CHAN6: + { + offset = STM32_ATIM_CCR6_OFFSET; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } + } + + /* Update CCR register */ + + pwm_putreg(priv, offset, ccr); + + return OK; +} + +/**************************************************************************** + * Name: pwm_ccr_get + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_PWM_LL_OPS +static uint32_t pwm_ccr_get(FAR struct pwm_lowerhalf_s *dev, uint8_t index) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t offset = 0; + + switch (index) + { + case STM32_PWM_CHAN1: + { + offset = STM32_GTIM_CCR1_OFFSET; + break; + } + + case STM32_PWM_CHAN2: + { + offset = STM32_GTIM_CCR2_OFFSET; + break; + } + + case STM32_PWM_CHAN3: + { + offset = STM32_GTIM_CCR3_OFFSET; + break; + } + + case STM32_PWM_CHAN4: + { + offset = STM32_GTIM_CCR4_OFFSET; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: + { + offset = STM32_ATIM_CCR5_OFFSET; + break; + } + + case STM32_PWM_CHAN6: + { + offset = STM32_ATIM_CCR6_OFFSET; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such CCR: %u\n", index); + return -EINVAL; + } + } + + /* Return CCR register */ + + return pwm_getreg(priv, offset); +} +#endif /* CONFIG_STM32H7_PWM_LL_OPS */ + +/**************************************************************************** + * Name: pwm_arr_update + ****************************************************************************/ + +static int pwm_arr_update(FAR struct pwm_lowerhalf_s *dev, uint32_t arr) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + /* Update ARR register */ + + pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); + + return OK; +} + +/**************************************************************************** + * Name: pwm_arr_get + ****************************************************************************/ + +static uint32_t pwm_arr_get(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); +} + +/**************************************************************************** + * Name: pwm_duty_update + * + * Description: + * Try to change only channel duty + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * channel - Channel to by updated + * duty - New duty + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_duty_update(FAR struct pwm_lowerhalf_s *dev, uint8_t channel, + ub16_t duty) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t reload = 0; + uint32_t ccr = 0; + + /* We don't want compilation warnings if no DEBUGASSERT */ + + UNUSED(priv); + + DEBUGASSERT(priv != NULL); + + pwminfo("TIM%u channel: %u duty: %08x\n", + priv->timid, channel, duty); + +#ifndef CONFIG_PWM_MULTICHAN + DEBUGASSERT(channel == priv->channels[0].channel); + DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); +#endif + + /* Get the reload values */ + + reload = pwm_arr_get(dev); + + /* Duty cycle: + * + * duty cycle = ccr / reload (fractional value) + */ + + ccr = b16toi(duty * reload + b16HALF); + + pwminfo("ccr: %u\n", ccr); + + /* Write coresponding CCR register */ + + pwm_ccr_update(dev, channel, ccr); + + return OK; +} + +/**************************************************************************** + * Name: pwm_timer_enable + ****************************************************************************/ + +static int pwm_timer_enable(FAR struct pwm_lowerhalf_s *dev, bool state) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + if (state == true) + { + /* Enable timer counter */ + + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + } + else + { + /* Disable timer counter */ + + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: pwm_frequency_update + * + * Description: + * Update a PWM timer frequency + * + ****************************************************************************/ + +static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev, + uint32_t frequency) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t reload = 0; + uint32_t timclk = 0; + uint32_t prescaler = 0; + + /* Calculate optimal values for the timer prescaler and for the timer reload + * register. If 'frequency' is the desired frequency, then + * + * reload = timclk / frequency + * timclk = pclk / presc + * + * Or, + * + * reload = pclk / presc / frequency + * + * There are many solutions to this this, but the best solution will be the + * one that has the largest reload value and the smallest prescaler value. + * That is the solution that should give us the most accuracy in the timer + * control. Subject to: + * + * 0 <= presc <= 65536 + * 1 <= reload <= 65535 + * + * So presc = pclk / 65535 / frequency would be optimal. + * + * Example: + * + * pclk = 42 MHz + * frequency = 100 Hz + * + * prescaler = 42,000,000 / 65,535 / 100 + * = 6.4 (or 7 -- taking the ceiling always) + * timclk = 42,000,000 / 7 + * = 6,000,000 + * reload = 6,000,000 / 100 + * = 60,000 + */ + + prescaler = (priv->pclk / frequency + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = priv->pclk / prescaler; + + reload = timclk / frequency; + if (reload < 2) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + else + { + reload--; + } + + pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n", + priv->timid, priv->pclk, frequency, timclk, prescaler, reload); + + /* Set the reload and prescaler values */ + + pwm_arr_update(dev, reload); + pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + + return OK; +} + +/**************************************************************************** + * Name: pwm_timer_configure + * + * Description: + * Initial configuration for PWM timer + * + ****************************************************************************/ + +static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv) +{ + uint16_t cr1 = 0; + int ret = OK; + + /* Set up the timer CR1 register: + * + * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN + * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN + * 6-7 ARPE OPM URS UDIS CEN + * 9-14 CKD[1:0] ARPE URS UDIS CEN + * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN + */ + + cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); + + /* Set the counter mode for the advanced timers (1,8) and most general + * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 + * and TIMTYPE_BASIC + */ + + if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16) + { + /* Select the Counter Mode: + * + * GTIM_CR1_EDGE: The counter counts up or down depending on the + * direction bit (DIR). + * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter + * counts up then down. + * GTIM_CR1_DIR: 0: count up, 1: count down + */ + + cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); + + switch (priv->mode) + { + case STM32_TIMMODE_COUNTUP: + { + cr1 |= GTIM_CR1_EDGE; + break; + } + + case STM32_TIMMODE_COUNTDOWN: + { + cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; + break; + } + + case STM32_TIMMODE_CENTER1: + { + cr1 |= GTIM_CR1_CENTER1; + break; + } + + case STM32_TIMMODE_CENTER2: + { + cr1 |= GTIM_CR1_CENTER2; + break; + } + + case STM32_TIMMODE_CENTER3: + { + cr1 |= GTIM_CR1_CENTER3; + break; + } + + default: + { + pwmerr("ERROR: No such timer mode: %u\n", + (unsigned int)priv->mode); + ret = -EINVAL; + goto errout; + } + } + } + + /* Enable ARR Preload + * TODO: this should be configurable + */ + + cr1 |= GTIM_CR1_ARPE; + + /* Write CR1 */ + + pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_mode_configure + * + * Description: + * Configure a PWM mode for given channel + * + ****************************************************************************/ + +static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev, + uint8_t channel, uint32_t mode) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t chanmode = 0; + uint32_t ocmode = 0; + uint32_t ccmr = 0; + uint32_t offset = 0; + int ret = OK; +#ifdef HAVE_IP_TIMERS_V2 + bool ocmbit = false; +#endif + +#ifdef HAVE_IP_TIMERS_V2 + /* Only advanced timers have channels 5-6 */ + + if (channel > 4 && priv->timtype != TIMTYPE_ADVANCED) + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } +#endif + + /* Get channel mode + * TODO: configurable preload for CCxR + */ + + switch (mode) + { + case STM32_CHANMODE_FRZN: + { + chanmode = GTIM_CCMR_MODE_FRZN; + break; + } + + case STM32_CHANMODE_CHACT: + { + chanmode = GTIM_CCMR_MODE_CHACT; + break; + } + + case STM32_CHANMODE_CHINACT: + { + chanmode = GTIM_CCMR_MODE_CHINACT; + break; + } + + case STM32_CHANMODE_OCREFTOG: + { + chanmode = GTIM_CCMR_MODE_OCREFTOG; + break; + } + + case STM32_CHANMODE_OCREFLO: + { + chanmode = GTIM_CCMR_MODE_OCREFLO; + break; + } + + case STM32_CHANMODE_OCREFHI: + { + chanmode = GTIM_CCMR_MODE_OCREFHI; + break; + } + + case STM32_CHANMODE_PWM1: + { + chanmode = ATIM_CCMR_MODE_PWM1; + break; + } + + case STM32_CHANMODE_PWM2: + { + chanmode = ATIM_CCMR_MODE_PWM2; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_CHANMODE_COMBINED1: + { + chanmode = ATIM_CCMR_MODE_COMBINED1; + ocmbit = true; + break; + } + + case STM32_CHANMODE_COMBINED2: + { + chanmode = ATIM_CCMR_MODE_COMBINED2; + ocmbit = true; + break; + } + + case STM32_CHANMODE_ASYMMETRIC1: + { + chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; + ocmbit = true; + break; + } + + case STM32_CHANMODE_ASYMMETRIC2: + { + chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; + ocmbit = true; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode); + ret = -EINVAL; + goto errout; + } + } + + /* Get CCMR offset */ + + switch (channel) + { + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: + { + offset = STM32_GTIM_CCMR1_OFFSET; + break; + } + + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: + { + offset = STM32_GTIM_CCMR2_OFFSET; + break; + } + +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: + { + offset = STM32_ATIM_CCMR3_OFFSET; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } + } + + /* Get current registers */ + + ccmr = pwm_getreg(priv, offset); + + /* PWM mode configuration. + * NOTE: The CCMRx registers are identical if the channels are outputs. + */ + + switch (channel) + { + /* Configure channel 1/3/5 */ + + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN5: +#endif + { + /* Reset current channel 1/3/5 mode configuration */ + + ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | + ATIM_CCMR1_OC1PE); + + /* Configure CC1/3/5 as output */ + + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + + /* Configure Compare 1/3/5 mode */ + + ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); + + /* Enable CCR1/3/5 preload */ + + ocmode |= ATIM_CCMR1_OC1PE; + +#ifdef HAVE_IP_TIMERS_V2 + /* Reset current OC bit */ + + ccmr &= ~(ATIM_CCMR1_OC1M); + + /* Set an additional OC1/3/5M bit */ + + if (ocmbit) + { + ocmode |= ATIM_CCMR1_OC1M; + } +#endif + break; + } + + /* Configure channel 2/4/6 */ + + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: +#ifdef HAVE_IP_TIMERS_V2 + case STM32_PWM_CHAN6: +#endif + { + /* Reset current channel 2/4/6 mode configuration */ + + ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | + ATIM_CCMR1_OC2PE); + + /* Configure CC2/4/6 as output */ + + ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); + + /* Configure Compare 2/4/6 mode */ + + ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); + + /* Enable CCR2/4/6 preload */ + + ocmode |= ATIM_CCMR1_OC2PE; + +#ifdef HAVE_IP_TIMERS_V2 + /* Reset current OC bit */ + + ccmr &= ~(ATIM_CCMR1_OC2M); + + /* Set an additioneal OC2/4/6M bit */ + + if (ocmbit) + { + ocmode |= ATIM_CCMR1_OC2M; + } +#endif + break; + } + } + + /* Set the selected output compare mode */ + + ccmr |= ocmode; + + /* Write CCMRx registers */ + + pwm_putreg(priv, offset, ccmr); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_output_configure + * + * Description: + * Configure PWM output for given channel + * + ****************************************************************************/ + +static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv, + uint8_t channel) +{ + uint32_t cr2 = 0; + uint32_t ccer = 0; + + /* Get current registers state */ + + cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register + * | CCxP/CCxNP | POL | all PWM timers | CCER register + */ + + /* Configure output polarity (all PWM timers) */ + + if (priv->channels[channel-1].out1.pol == STM32_POL_NEG) + { + ccer |= (GTIM_CCER_CC1P << ((channel-1)*4)); + } + else + { + ccer &= ~(GTIM_CCER_CC1P << ((channel-1)*4)); + } + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + /* Configure output IDLE State */ + + if (priv->channels[channel-1].out1.idle == STM32_IDLE_ACTIVE) + { + cr2 |= (ATIM_CR2_OIS1 << ((channel-1)*2)); + } + else + { + cr2 &= ~(ATIM_CR2_OIS1 << ((channel-1)*2)); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Configure complementary output IDLE state */ + + if (priv->channels[channel-1].out2.idle == STM32_IDLE_ACTIVE) + { + cr2 |= (ATIM_CR2_OIS1N << ((channel-1)*2)); + } + else + { + cr2 &= ~(ATIM_CR2_OIS1N << ((channel-1)*2)); + } + + /* Configure complementary output polarity */ + + if (priv->channels[channel-1].out2.pol == STM32_POL_NEG) + { + ccer |= (ATIM_CCER_CC1NP << ((channel-1)*4)); + } + else + { + ccer &= ~(ATIM_CCER_CC1NP << ((channel-1)*4)); + } +#endif /* HAVE_PWM_COMPLEMENTARY */ + +#ifdef HAVE_IP_TIMERS_V2 + /* TODO: OIS5 and OIS6 */ + + cr2 &= ~(ATIM_CR2_OIS5 | ATIM_CR2_OIS6); + + /* TODO: CC5P and CC6P */ + + ccer &= ~(ATIM_CCER_CC5P | ATIM_CCER_CC6P); +#endif /* HAVE_IP_TIMERS_V2 */ + } +#ifdef HAVE_GTIM_CCXNP + else +#endif /* HAVE_GTIM_CCXNP */ +#endif /* HAVE_ADVTIM */ +#ifdef HAVE_GTIM_CCXNP + { + /* CCxNP must be cleared if not ADVANCED timer. + * + * REVISIT: not all families have CCxNP bits for GTIM, + * which causes an ugly condition above + */ + + ccer &= ~(GTIM_CCER_CC1NP << ((channel-1)*4)); + } +#endif /* HAVE_GTIM_CCXNP */ + + /* Write registers */ + + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); + + return OK; +} + +/**************************************************************************** + * Name: pwm_outputs_enable + * + * Description: + * Enable/disable given timer PWM outputs. + * + * NOTE: This is bulk operation - we can enable/disable many outputs + * at one time + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * outputs - outputs to set (look at enum stm32_chan_e in stm32_pwm.h) + * state - Enable/disable operation + * + ****************************************************************************/ + +static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev, + uint16_t outputs, bool state) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t ccer = 0; + uint32_t regval = 0; + + /* Get curren register state */ + + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); + + /* Get outputs configuration */ + + regval |= ((outputs & STM32_PWM_OUT1) ? ATIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? ATIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? ATIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? ATIM_CCER_CC4E : 0); + + /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ + +#ifdef HAVE_IP_TIMERS_V2 + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); +#endif + + if (state == true) + { + /* Enable outpus - set bits */ + + ccer |= regval; + } + else + { + /* Disable outputs - reset bits */ + + ccer &= ~regval; + } + + /* Write register */ + + pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + + return OK; +} + +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) + +/**************************************************************************** + * Name: pwm_deadtime_update + ****************************************************************************/ + +static int pwm_deadtime_update(FAR struct pwm_lowerhalf_s *dev, uint8_t dt) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t bdtr = 0; + int ret = OK; + + /* Check if locked */ + + if (priv->lock > 0) + { + ret = -EACCES; + goto errout; + } + + /* Get current register state */ + + bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); + + /* TODO: check if BDTR not locked */ + + /* Update deadtime */ + + bdtr &= ~(ATIM_BDTR_DTG_MASK); + bdtr |= (dt << ATIM_BDTR_DTG_SHIFT); + + /* Write BDTR register */ + + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); + +errout: + return ret; +} +#endif + +#ifdef HAVE_TRGO +/**************************************************************************** + * Name: pwm_sync_configure + * + * Description: + * Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2) + * + ****************************************************************************/ + +static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv, uint8_t trgo) +{ + uint32_t cr2 = 0; + + /* Configure TRGO (4 LSB in trgo) */ + + cr2 |= (((trgo >> 0) & 0x0f) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK; + +#ifdef HAVE_IP_TIMERS_V2 + /* Configure TRGO2 (4 MSB in trgo) */ + + cr2 |= (((trgo >> 4) & 0x0f) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK; +#endif + + /* Write register */ + + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + + return OK; +} +#endif + +/**************************************************************************** + * Name: pwm_soft_update + * + * Description: + * Generate an software update event + * + ****************************************************************************/ + +static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG); + + return OK; +} + +/**************************************************************************** + * Name: pwm_soft_break + * + * Description: + * Generate an software break event + * + * Outputs are enabled if state is false. + * Outputs are disabled if state is true. + * + * NOTE: only timers with complementary outputs have BDTR register and + * support software break. + * + ****************************************************************************/ + +static int pwm_soft_break(FAR struct pwm_lowerhalf_s *dev, bool state) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + if (state == true) + { + /* Reset MOE bit */ + + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + } + else + { + /* Set MOE bit */ + + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } + + return OK; +} + +/**************************************************************************** + * Name: pwm_outputs_from_channels + * + * Description: + * Get enabled outputs configuration from the PWM timer state + * + ****************************************************************************/ + +static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv) +{ + uint16_t outputs = 0; + uint8_t channel = 0; + uint8_t i = 0; + + for (i = 0; i < priv->chan_num; i += 1) + { + /* Get channel */ + + channel = priv->channels[i].channel; + + /* Set outputs if channel configured */ + + if (channel != 0) + { + /* Enable output if confiugred */ + + if (priv->channels[i].out1.in_use == 1) + { + outputs |= (STM32_PWM_OUT1 << ((channel-1)*2)); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Enable complementary output if configured */ + + if (priv->channels[i].out2.in_use == 1) + { + outputs |= (STM32_PWM_OUT1N << ((channel-1)*2)); + } +#endif + } + } + + return outputs; +} + +#ifdef HAVE_ADVTIM + +/**************************************************************************** + * Name: pwm_break_dt_configure + * + * Description: + * Configure break and deadtime + * + * NOTE: we have to configure all BDTR registers at once due to possible + * lock configuration + * + ****************************************************************************/ + +static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv) +{ + uint32_t bdtr = 0; + + /* Set the clock division to zero for all (but the basic timers, but there + * should be no basic timers in this context + */ + + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, + priv->t_dts << GTIM_CR1_CKD_SHIFT); + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Initialize deadtime */ + + bdtr |= (priv->deadtime << ATIM_BDTR_DTG_SHIFT); +#endif + +#ifdef HAVE_BREAK + /* Configure Break 1 */ + + if (priv->brk.en1 == 1) + { + /* Enable Break 1 */ + + bdtr |= ATIM_BDTR_BKE; + + /* Set Break 1 polarity */ + + bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); + } + +#ifdef HAVE_IP_TIMERS_V2 + /* Configure Break 1 */ + + if (priv->brk.en2 == 1) + { + /* Enable Break 2 */ + + bdtr |= ATIM_BDTR_BK2E; + + /* Set Break 2 polarity */ + + bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); + + /* Configure BRK2 filter */ + + bdtr |= (priv->brk.flt2 << ATIM_BDTR_BK2F_SHIFT); + + } +#endif /* HAVE_IP_TIMERS_V2 */ +#endif /* HAVE_BREAK */ + + /* Clear the OSSI and OSSR bits in the BDTR register. + * + * REVISIT: this should be configurable + */ + + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + + /* Configure lock */ + + bdtr |= priv->lock << ATIM_BDTR_LOCK_SHIFT; + + /* Write BDTR register at once */ + + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); + + return OK; +} +#endif + +#ifdef CONFIG_PWM_PULSECOUNT + +/**************************************************************************** + * Name: pwm_pulsecount_configure + * + * Description: + * Configure PWM timer in PULSECOUNT mode + * + ****************************************************************************/ + +static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint16_t outputs = 0; + uint8_t j = 0; + int ret = OK; + + UNUSED(priv); + + /* NOTE: leave timer counter disabled and all outputs disabled! */ + + /* Disable the timer until we get it configured */ + + pwm_timer_enable(dev, false); + + /* Get configured outputs */ + + outputs = pwm_outputs_from_channels(priv); + + /* REVISIT: Disable outputs */ + + ret = pwm_outputs_enable(dev, outputs, false); + if (ret < 0) + { + goto errout; + } + + /* Initial timer configuration */ + + ret = pwm_timer_configure(priv); + if (ret < 0) + { + goto errout; + } + + /* Configure break and deadtime register */ + + ret = pwm_break_dt_configure(priv); + if (ret < 0) + { + goto errout; + } + + /* Disable software break (enable outputs) */ + + ret = pwm_soft_break(dev, false); + if (ret < 0) + { + goto errout; + } + +#ifdef HAVE_TRGO + /* Configure TRGO/TRGO2 */ + + ret = pwm_sync_configure(priv, priv->trgo); + if (ret < 0) + { + goto errout; + } +#endif + + /* Configure timer channels */ + + for (j = 0; j < priv->chan_num; j++) + { + /* Skip channle if not in use */ + + if (priv->channels[j].channel != 0) + { + /* Update PWM mode */ + + pwm_mode_configure(dev, priv->channels[j].channel, + priv->channels[j].mode); + + /* PWM outputs configuration */ + + pwm_output_configure(priv, priv->channels[j].channel); + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_pulsecount_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * TODO: PWM_PULSECOUNT should be configurable for each timer instance + * TODO: PULSECOUNT doesnt work with MULTICHAN at this moment + * + ****************************************************************************/ + +static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + ub16_t duty = 0; + uint8_t channel = 0; + uint32_t mode = 0; + uint16_t outputs = 0; + int ret = OK; + + /* If we got here it means that timer instance support pulsecount mode! */ + + DEBUGASSERT(priv != NULL && info != NULL); + + pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n", + priv->timid, priv->channels[0].channel, info->frequency, + info->duty, info->count); + + DEBUGASSERT(info->frequency > 0); + + /* Channel specific setup */ + + duty = info->duty; + channel = priv->channels[0].channel; + mode = priv->channels[0].mode; + + /* Disable all interrupts and DMA requests, clear all pending status */ + + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Set timer frequency */ + + ret = pwm_frequency_update(dev, info->frequency); + if (ret < 0) + { + goto errout; + } + + /* Update duty cycle */ + + ret = pwm_duty_update(dev, channel, duty); + if (ret < 0) + { + goto errout; + } + + /* If a non-zero repetition count has been selected, then set the + * repitition counter to the count-1 (pwm_pulsecount_start() has already + * assured us that the count value is within range). + */ + + if (info->count > 0) + { + /* Save the remaining count and the number of counts that will have + * elapsed on the first interrupt. + */ + + /* If the first interrupt occurs at the end end of the first + * repetition count, then the count will be the same as the RCR + * value. + */ + + priv->prev = pwm_pulsecount(info->count); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->prev - 1); + + /* Generate an update event to reload the prescaler. This should + * preload the RCR into active repetition counter. + */ + + pwm_soft_update(dev); + +#if 0 + /* Now set the value of the RCR that will be loaded on the next + * update event. + */ + + priv->count = info->count; + priv->curr = pwm_pulsecount(info->count - priv->prev); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); +#endif + } + + /* Otherwise, just clear the repetition counter */ + + else + { + /* Set the repetition counter to zero */ + + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + + /* Generate an update event to reload the prescaler */ + + pwm_soft_update(dev); + } + + /* Get configured outputs */ + + outputs = pwm_outputs_from_channels(priv); + + /* Enable output */ + + ret = pwm_outputs_enable(dev, outputs, true); + if (ret < 0) + { + goto errout; + } + + /* Setup update interrupt. If info->count is > 0, then we can be + * assured that pwm_pulsecount_start() has already verified: (1) that this + * is an advanced timer, and that (2) the repetition count is within range. + */ + + if (info->count > 0) + { + /* Clear all pending interrupts and enable the update interrupt. */ + + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE); + + /* Enable the timer */ + + pwm_timer_enable(dev, true); + + /* And enable timer interrupts at the NVIC */ + + up_enable_irq(priv->irq); + } + + pwm_dumpregs(priv, "After starting"); + +errout: + return ret; +} + +#else /* !CONFIG_PWM_PULSECOUNT */ + +/**************************************************************************** + * Name: pwm_configure + * + * Description: + * Configure PWM timer in normal mode (no PULSECOUNT) + * + ****************************************************************************/ + +static int pwm_configure(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint16_t outputs = 0; + uint8_t j = 0; + int ret = OK; + + /* NOTE: leave timer counter disabled and all outputs disabled! */ + + /* Get configured outputs */ + + outputs = pwm_outputs_from_channels(priv); + + /* Disable outputs */ + + ret = pwm_outputs_enable(dev, outputs, false); + if (ret < 0) + { + goto errout; + } + + /* Disable the timer until we get it configured */ + + pwm_timer_enable(dev, false); + + /* Initial timer configuration */ + + ret = pwm_timer_configure(priv); + if (ret < 0) + { + goto errout; + } + + /* Some special setup for advanced timers */ + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + /* Configure break and deadtime register */ + + ret = pwm_break_dt_configure(priv); + if (ret < 0) + { + goto errout; + } + +#ifdef HAVE_TRGO + /* Configure TRGO/TRGO2 */ + + ret = pwm_sync_configure(priv, priv->trgo); + if (ret < 0) + { + goto errout; + } +#endif + } +#endif + + /* Configure timer channels */ + + for (j = 0; j < priv->chan_num; j++) + { + /* Skip channle if not in use */ + + if (priv->channels[j].channel != 0) + { + /* Update PWM mode */ + + ret = pwm_mode_configure(dev, priv->channels[j].channel, + priv->channels[j].mode); + if (ret < 0) + { + goto errout; + } + + /* PWM outputs configuration */ + + ret = pwm_output_configure(priv, priv->channels[j].channel); + if (ret < 0) + { + goto errout; + } + } + } + + /* Disable software break at the end of the outputs configuration (enablei + * outputs). + * + * NOTE: Only timers with complementary outputs have BDTR register and + * support software break. + */ + + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + ret = pwm_soft_break(dev, false); + if (ret < 0) + { + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_duty_channels_update + * + * Description: + * Update duty cycle for given channels + * + ****************************************************************************/ + +static int pwm_duty_channels_update(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint8_t channel = 0; + ub16_t duty = 0; + int ret = OK; +#ifdef CONFIG_PWM_MULTICHAN + int i = 0; + int j = 0; +#endif + +#ifdef CONFIG_PWM_MULTICHAN + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) +#endif + { +#ifdef CONFIG_PWM_MULTICHAN + duty = info->channels[i].duty; + channel = info->channels[i].channel; + + /* A value of zero means to skip this channel */ + + if (channel != 0) + { + /* Find the channel */ + + for (j = 0; j < priv->chan_num; j++) + { + if (priv->channels[j].channel == channel) + { + break; + } + } + + /* Check range */ + + if (j >= priv->chan_num) + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } +#else + duty = info->duty; + channel = priv->channels[0].channel; +#endif + + /* Update duty cycle */ + + ret = pwm_duty_update(dev, channel, duty); + if (ret < 0) + { + goto errout; + } +#ifdef CONFIG_PWM_MULTICHAN + } +#endif + } + +errout: + return OK; +} + +/**************************************************************************** + * Name: pwm_timer + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_timer(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint16_t outputs = 0; + int ret = OK; + + DEBUGASSERT(priv != NULL && info != NULL); + +#if defined(CONFIG_PWM_MULTICHAN) + pwminfo("TIM%u frequency: %u\n", + priv->timid, info->frequency); +#else + pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n", + priv->timid, priv->channels[0].channel, + info->frequency, info->duty); +#endif + + DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_PWM_MULTICHAN + DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); +#endif + + /* TODO: what if we have pwm running and we want disable some channels ? */ + + /* Set timer frequency */ + + ret = pwm_frequency_update(dev, info->frequency); + if (ret < 0) + { + goto errout; + } + + /* Channel specific configuration */ + + ret = pwm_duty_channels_update(dev, info); + if (ret < 0) + { + goto errout; + } + + /* Set the advanced timer's repetition counter */ + +#ifdef HAVE_ADVTIM + if (priv->timtype == TIMTYPE_ADVANCED || + priv->timtype == TIMTYPE_COUNTUP16_N) + { + /* If a non-zero repetition count has been selected, then set the + * repitition counter to the count-1 (pwm_start() has already + * assured us that the count value is within range). + */ + + /* Set the repetition counter to zero */ + + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + + /* Generate an update event to reload the prescaler */ + + pwm_soft_update(dev); + } + else +#endif + { + /* Generate an update event to reload the prescaler (all timers) */ + + pwm_soft_update(dev); + } + + /* Get configured outputs */ + + outputs = pwm_outputs_from_channels(priv); + + /* Enable outputs */ + + ret = pwm_outputs_enable(dev, outputs, true); + if (ret < 0) + { + goto errout; + } + + /* Just enable the timer, leaving all interrupts disabled */ + + pwm_timer_enable(dev, true); + + pwm_dumpregs(priv, "After starting"); + +errout: + return ret; +} +#endif /* CONFIG_PWM_PULSECOUNT */ + +#ifdef HAVE_PWM_INTERRUPT + +/**************************************************************************** + * Name: pwm_interrupt + * + * Description: + * Handle timer interrupts. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint16_t regval; + + /* Verify that this is an update interrupt. Nothing else is expected. */ + + regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET); + DEBUGASSERT((regval & ATIM_SR_UIF) != 0); + + /* Clear the UIF interrupt bit */ + + pwm_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF)); + + /* Calculate the new count by subtracting the number of pulses + * since the last interrupt. + */ + + if (priv->count <= priv->prev) + { + /* We are finished. Turn off the master output to stop the output as + * quickly as possible. + */ + + pwm_soft_break(dev, true); + + /* Disable first interrtups, stop and reset the timer */ + + (void)pwm_stop(dev); + + /* Then perform the callback into the upper half driver */ + + pwm_expired(priv->handle); + + priv->handle = NULL; + priv->count = 0; + priv->prev = 0; + priv->curr = 0; + } + else + { + /* Decrement the count of pulses remaining using the number of + * pulses generated since the last interrupt. + */ + + priv->count -= priv->prev; + + /* Set up the next RCR. Set 'prev' to the value of the RCR that + * was loaded when the update occurred (just before this interrupt) + * and set 'curr' to the current value of the RCR register (which + * will bet loaded on the next update event). + */ + + priv->prev = priv->curr; + priv->curr = pwm_pulsecount(priv->count - priv->prev); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); + } + + /* Now all of the time critical stuff is done so we can do some debug + * output. + */ + + pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n", + regval, priv->prev, priv->curr, priv->count); + + return OK; +} + +/**************************************************************************** + * Name: pwm_tim1/8interrupt + * + * Description: + * Handle timer 1 and 8 interrupts. + * + * Input Parameters: + * Standard NuttX interrupt inputs + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_TIM1_PWM +static int pwm_tim1interrupt(int irq, void *context, FAR void *arg) +{ + return pwm_interrupt((FAR struct pwm_lowerhalf_s *)&g_pwm1dev); +} +#endif /* CONFIG_STM32H7_TIM1_PWM */ + +#ifdef CONFIG_STM32H7_TIM8_PWM +static int pwm_tim8interrupt(int irq, void *context, FAR void *arg) +{ + return pwm_interrupt((FAR struct pwm_lowerhalf_s *)&g_pwm8dev); +} +#endif /* CONFIG_STM32H7_TIM8_PWM */ + +/**************************************************************************** + * Name: pwm_pulsecount + * + * Description: + * Pick an optimal pulse count to program the RCR. + * + * Input Parameters: + * count - The total count remaining + * + * Returned Value: + * The recommended pulse count + * + ****************************************************************************/ + +static uint8_t pwm_pulsecount(uint32_t count) +{ + /* REVISIT: RCR_REP_MAX for GTIM or ATIM ? */ + + /* The the remaining pulse count is less than or equal to the maximum, the + * just return the count. + */ + + if (count <= ATIM_RCR_REP_MAX) + { + return (uint8_t)count; + } + + /* Otherwise, we have to be careful. We do not want a small number of + * counts at the end because we might have trouble responding fast enough. + * If the remaining count is less than 150% of the maximum, then return + * half of the maximum. In this case the final sequence will be between 64 + * and 128. + */ + + else if (count < (3 * ATIM_RCR_REP_MAX / 2)) + { + return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); + } + + /* Otherwise, return the maximum. The final count will be 64 or more */ + + else + { + return (uint8_t)ATIM_RCR_REP_MAX; + } +} +#endif /* HAVE_PWM_INTERRUPT */ + +/**************************************************************************** + * Name: pwm_set_apb_clock + * + * Description: + * Enable or disable APB clock for the timer peripheral + * + * Input Parameters: + * priv - A reference to the PWM block status + * on - Enable clock if 'on' is 'true' and disable if 'false' + * + ****************************************************************************/ + +static int pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on) +{ + uint32_t en_bit = 0; + uint32_t regaddr = 0; + int ret = OK; + + pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); + + /* Determine which timer to configure */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32H7_TIM1_PWM + case 1: + { + regaddr = TIMRCCEN_TIM1; + en_bit = TIMEN_TIM1; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM2_PWM + case 2: + { + regaddr = TIMRCCEN_TIM2; + en_bit = TIMEN_TIM2; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM3_PWM + case 3: + { + regaddr = TIMRCCEN_TIM3; + en_bit = TIMEN_TIM3; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM4_PWM + case 4: + { + regaddr = TIMRCCEN_TIM4; + en_bit = TIMEN_TIM4; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM5_PWM + case 5: + { + regaddr = TIMRCCEN_TIM5; + en_bit = TIMEN_TIM5; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM8_PWM + case 8: + { + regaddr = TIMRCCEN_TIM8; + en_bit = TIMEN_TIM8; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM12_PWM + case 12: + { + regaddr = TIMRCCEN_TIM12; + en_bit = TIMEN_TIM12; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM13_PWM + case 13: + { + regaddr = TIMRCCEN_TIM13; + en_bit = TIMEN_TIM13; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM14_PWM + case 14: + { + regaddr = TIMRCCEN_TIM14; + en_bit = TIMEN_TIM14; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM15_PWM + case 15: + { + regaddr = TIMRCCEN_TIM15; + en_bit = TIMEN_TIM15; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM16_PWM + case 16: + { + regaddr = TIMRCCEN_TIM16; + en_bit = TIMEN_TIM16; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM17_PWM + case 17: + { + regaddr = TIMRCCEN_TIM17; + en_bit = TIMEN_TIM17; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such timer configured %d\n", priv->timid); + ret = -EINVAL; + goto errout; + } + } + + /* Enable/disable APB 1/2 clock for timer */ + + pwminfo("RCC_APBxENR base: %08x bits: %04x\n", regaddr, en_bit); + + if (on) + { + modifyreg32(regaddr, 0, en_bit); + } + else + { + modifyreg32(regaddr, en_bit, 0); + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * APB1 or 2 clocking for the GPIOs has already been configured by the RCC + * logic at power up. + * + ****************************************************************************/ + +static int pwm_setup(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t pincfg = 0; + int ret = OK; + int i = 0; + + pwminfo("TIM%u\n", priv->timid); + + /* Enable APB1/2 clocking for timer. */ + + ret = pwm_set_apb_clock(priv, true); + if (ret < 0) + { + goto errout; + } + + pwm_dumpregs(priv, "Initially"); + + /* Configure the PWM output pins, but do not start the timer yet */ + + for (i = 0; i < priv->chan_num; i++) + { + if (priv->channels[i].out1.in_use == 1) + { + pincfg = priv->channels[i].out1.pincfg; + pwminfo("pincfg: %08x\n", pincfg); + + stm32_configgpio(pincfg); + pwm_dumpgpio(pincfg, "PWM setup"); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + if (priv->channels[i].out2.in_use == 1) + { + pincfg = priv->channels[i].out2.pincfg; + pwminfo("pincfg: %08x\n", pincfg); + + stm32_configgpio(pincfg); + pwm_dumpgpio(pincfg, "PWM setup"); + } +#endif + } + + /* Configure PWM timer with the selected configuration. + * + * NOTE: We configure PWM here during setup, but leave timer with disabled + * counter, disabled outputs, not configured frequency and duty cycle + */ + +#ifdef CONFIG_PWM_PULSECOUNT + ret = pwm_pulsecount_configure(dev); +#else + ret = pwm_configure(dev); +#endif + if (ret < 0) + { + pwmerr("failed to configure PWM %d\n", priv->timid); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + uint32_t pincfg = 0; + int i = 0; + int ret = OK; + + pwminfo("TIM%u\n", priv->timid); + + /* Make sure that the output has been stopped */ + + pwm_stop(dev); + + /* Disable APB1/2 clocking for timer. */ + + ret = pwm_set_apb_clock(priv, false); + if (ret < 0) + { + goto errout; + } + + /* Then put the GPIO pins back to the default state */ + + for (i = 0; i < priv->chan_num; i++) + { + pincfg = priv->channels[i].out1.pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08x\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= PINCFG_DEFAULT; + + stm32_configgpio(pincfg); + } + +#ifdef HAVE_PWM_COMPLEMENTARY + pincfg = priv->channels[i].out2.pincfg; + if (pincfg != 0) + { + pwminfo("pincfg: %08x\n", pincfg); + + pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); + pincfg |= PINCFG_DEFAULT; + + stm32_configgpio(pincfg); + } +#endif + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +#ifdef CONFIG_PWM_PULSECOUNT +static int pwm_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info, + FAR void *handle) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + /* Check if a pulsecount has been selected */ + + if (info->count > 0) + { + /* Only the advanced timers (TIM1,8 can support the pulse counting) + * REVISIT: verify if TIMTYPE_COUNTUP16_N works with it + */ + + if (priv->timtype != TIMTYPE_ADVANCED) + { + pwmerr("ERROR: TIM%u cannot support pulse count: %u\n", + priv->timid, info->count); + return -EPERM; + } + } + + /* Save the handle */ + + priv->handle = handle; + + /* Start the time */ + + return pwm_pulsecount_timer(dev, info); +} +#else /* !CONFIG_PWM_PULSECOUNT */ +static int pwm_start(FAR struct pwm_lowerhalf_s *dev, + FAR const struct pwm_info_s *info) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + int ret = OK; + + /* if frequency has not changed we just update duty */ + + if (info->frequency == priv->frequency) + { +#ifdef CONFIG_PWM_MULTICHAN + int i; + + /* REVISIT: */ + + for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) + { + ret = pwm_duty_update(dev, info->channels[i].channel, + info->channels[i].duty); + } +#else + ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); +#endif /* CONFIG_PWM_MULTICHAN */ + } + else + { + ret = pwm_timer(dev, info); + + /* Save current frequency */ + + if (ret == OK) + { + priv->frequency = info->frequency; + } + } + + return ret; +} +#endif /* CONFIG_PWM_PULSECOUNT */ + +/**************************************************************************** + * Name: pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. This + * method is also called from the timer interrupt handler when a repetition + * count expires... automatically stopping the timer. + * + ****************************************************************************/ + +static int pwm_stop(FAR struct pwm_lowerhalf_s *dev) +{ + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + irqstate_t flags = 0; + uint32_t resetbit = 0; + uint32_t regaddr = 0; + uint32_t regval = 0; + int ret = OK; + + pwminfo("TIM%u\n", priv->timid); + + /* Determine which timer to reset */ + + switch (priv->timid) + { +#ifdef CONFIG_STM32H7_TIM1_PWM + case 1: + { + regaddr = TIMRCCRST_TIM1; + resetbit = TIMRST_TIM1; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM2_PWM + case 2: + { + regaddr = TIMRCCRST_TIM2; + resetbit = TIMRST_TIM2; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM3_PWM + case 3: + { + regaddr = TIMRCCRST_TIM3; + resetbit = TIMRST_TIM3; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM4_PWM + case 4: + { + regaddr = TIMRCCRST_TIM4; + resetbit = TIMRST_TIM4; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM5_PWM + case 5: + { + regaddr = TIMRCCRST_TIM5; + resetbit = TIMRST_TIM5; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM8_PWM + case 8: + { + regaddr = TIMRCCRST_TIM8; + resetbit = TIMRST_TIM8; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM12_PWM + case 12: + { + regaddr = TIMRCCRST_TIM12; + resetbit = TIMRST_TIM12; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM13_PWM + case 13: + { + regaddr = TIMRCCRST_TIM13; + resetbit = TIMRST_TIM13; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM14_PWM + case 14: + { + regaddr = TIMRCCRST_TIM14; + resetbit = TIMRST_TIM14; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM15_PWM + case 15: + { + regaddr = TIMRCCRST_TIM15; + resetbit = TIMRST_TIM15; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM16_PWM + case 16: + { + regaddr = TIMRCCRST_TIM16; + resetbit = TIMRST_TIM16; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM17_PWM + case 17: + { + regaddr = TIMRCCRST_TIM17; + resetbit = TIMRST_TIM17; + break; + } +#endif + + default: + { + ret = -EINVAL; + goto errout; + } + } + + /* Disable interrupts momentary to stop any ongoing timer processing and + * to prevent any concurrent access to the reset register. + */ + + flags = enter_critical_section(); + +#ifndef CONFIG_PWM_PULSECOUNT + /* Stopped so frequency is zero */ + + priv->frequency = 0; +#endif + + /* Disable further interrupts and stop the timer */ + + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + + /* Reset the timer - stopping the output and putting the timer back + * into a state where pwm_start() can be called. + */ + + regval = getreg32(regaddr); + regval |= resetbit; + putreg32(regval, regaddr); + + regval &= ~resetbit; + putreg32(regval, regaddr); + leave_critical_section(flags); + + pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit); + pwm_dumpregs(priv, "After stop"); + +errout: + return ret; +} + +/**************************************************************************** + * Name: pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ +#ifdef CONFIG_DEBUG_PWM_INFO + FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev; + + /* There are no platform-specific ioctl commands */ + + pwminfo("TIM%u\n", priv->timid); +#endif + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,17}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) +{ + FAR struct stm32_pwmtimer_s *lower = NULL; + + pwminfo("TIM%u\n", timer); + + switch (timer) + { +#ifdef CONFIG_STM32H7_TIM1_PWM + case 1: + { + lower = &g_pwm1dev; + + /* Attach but disable the TIM1 update interrupt */ + +#ifdef CONFIG_PWM_PULSECOUNT + irq_attach(lower->irq, pwm_tim1interrupt, NULL); + up_disable_irq(lower->irq); +#endif + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM2_PWM + case 2: + { + lower = &g_pwm2dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM3_PWM + case 3: + { + lower = &g_pwm3dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM4_PWM + case 4: + { + lower = &g_pwm4dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM5_PWM + case 5: + { + lower = &g_pwm5dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM8_PWM + case 8: + { + lower = &g_pwm8dev; + + /* Attach but disable the TIM8 update interrupt */ + +#ifdef CONFIG_PWM_PULSECOUNT + irq_attach(lower->irq, pwm_tim8interrupt, NULL); + up_disable_irq(lower->irq); +#endif + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM12_PWM + case 12: + { + lower = &g_pwm12dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM13_PWM + case 13: + { + lower = &g_pwm13dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM14_PWM + case 14: + { + lower = &g_pwm14dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM15_PWM + case 15: + { + lower = &g_pwm15dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM16_PWM + case 16: + { + lower = &g_pwm16dev; + break; + } +#endif + +#ifdef CONFIG_STM32H7_TIM17_PWM + case 17: + { + lower = &g_pwm17dev; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such timer configured %d\n", timer); + lower = NULL; + goto errout; + } + } + +errout: + return (FAR struct pwm_lowerhalf_s *)lower; +} + +#endif /* CONFIG_STM32H7_PWM */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h new file mode 100644 index 00000000000..6d0b0609149 --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -0,0 +1,1059 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/stm32_pwm.h + * + * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved. + * Authors: Gregory Nutt + * Paul Alexander Patience + * Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_STM32_PWM_H +#define __ARCH_ARM_SRC_STM32H7_STM32_PWM_H + +/* The STM32 does not have dedicated PWM hardware. Rather, pulsed output control + * is a capabilitiy of the STM32 timers. The logic in this file implements the + * lower half of the standard, NuttX PWM interface using the STM32 timers. That + * interface is described in include/nuttx/drivers/pwm.h. + */ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ +/* Timer devices may be used for different purposes. One special purpose is + * to generate modulated outputs for such things as motor control. If CONFIG_STM32H7_TIMn + * is defined then the CONFIG_STM32H7_TIMn_PWM must also be defined to indicate that + * timer "n" is intended to be used for pulsed output signal generation. + */ + +#ifndef CONFIG_STM32H7_TIM1 +# undef CONFIG_STM32H7_TIM1_PWM +#endif +#ifndef CONFIG_STM32H7_TIM2 +# undef CONFIG_STM32H7_TIM2_PWM +#endif +#ifndef CONFIG_STM32H7_TIM3 +# undef CONFIG_STM32H7_TIM3_PWM +#endif +#ifndef CONFIG_STM32H7_TIM4 +# undef CONFIG_STM32H7_TIM4_PWM +#endif +#ifndef CONFIG_STM32H7_TIM5 +# undef CONFIG_STM32H7_TIM5_PWM +#endif +#ifndef CONFIG_STM32H7_TIM8 +# undef CONFIG_STM32H7_TIM8_PWM +#endif +#ifndef CONFIG_STM32H7_TIM12 +# undef CONFIG_STM32H7_TIM12_PWM +#endif +#ifndef CONFIG_STM32H7_TIM13 +# undef CONFIG_STM32H7_TIM13_PWM +#endif +#ifndef CONFIG_STM32H7_TIM14 +# undef CONFIG_STM32H7_TIM14_PWM +#endif +#ifndef CONFIG_STM32H7_TIM15 +# undef CONFIG_STM32H7_TIM15_PWM +#endif +#ifndef CONFIG_STM32H7_TIM16 +# undef CONFIG_STM32H7_TIM16_PWM +#endif +#ifndef CONFIG_STM32H7_TIM17 +# undef CONFIG_STM32H7_TIM17_PWM +#endif + +/* The basic timers (timer 6 and 7) are not capable of generating output pulses */ + +#undef CONFIG_STM32H7_TIM6_PWM +#undef CONFIG_STM32H7_TIM7_PWM + +/* Check if PWM support for any channel is enabled. */ + +#ifdef CONFIG_STM32H7_PWM + +#include +#include "hardware/stm32_tim.h" + +/* PWM driver channels configuration */ + +#ifdef CONFIG_STM32H7_PWM_MULTICHAN + +#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +# define PWM_TIM1_CHANNEL1 1 +#else +# define PWM_TIM1_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +# define PWM_TIM1_CHANNEL2 1 +#else +# define PWM_TIM1_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +# define PWM_TIM1_CHANNEL3 1 +#else +# define PWM_TIM1_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +# define PWM_TIM1_CHANNEL4 1 +#else +# define PWM_TIM1_CHANNEL4 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +# define PWM_TIM1_CHANNEL5 1 +#else +# define PWM_TIM1_CHANNEL5 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +# define PWM_TIM1_CHANNEL6 1 +#else +# define PWM_TIM1_CHANNEL6 0 +#endif +#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ + PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ + PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) + +#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +# define PWM_TIM2_CHANNEL1 1 +#else +# define PWM_TIM2_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +# define PWM_TIM2_CHANNEL2 1 +#else +# define PWM_TIM2_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +# define PWM_TIM2_CHANNEL3 1 +#else +# define PWM_TIM2_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +# define PWM_TIM2_CHANNEL4 1 +#else +# define PWM_TIM2_CHANNEL4 0 +#endif +#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ + PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) + +#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +# define PWM_TIM3_CHANNEL1 1 +#else +# define PWM_TIM3_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +# define PWM_TIM3_CHANNEL2 1 +#else +# define PWM_TIM3_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +# define PWM_TIM3_CHANNEL3 1 +#else +# define PWM_TIM3_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +# define PWM_TIM3_CHANNEL4 1 +#else +# define PWM_TIM3_CHANNEL4 0 +#endif +#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ + PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) + +#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +# define PWM_TIM4_CHANNEL1 1 +#else +# define PWM_TIM4_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +# define PWM_TIM4_CHANNEL2 1 +#else +# define PWM_TIM4_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +# define PWM_TIM4_CHANNEL3 1 +#else +# define PWM_TIM4_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +# define PWM_TIM4_CHANNEL4 1 +#else +# define PWM_TIM4_CHANNEL4 0 +#endif +#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ + PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) + +#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +# define PWM_TIM5_CHANNEL1 1 +#else +# define PWM_TIM5_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +# define PWM_TIM5_CHANNEL2 1 +#else +# define PWM_TIM5_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +# define PWM_TIM5_CHANNEL3 1 +#else +# define PWM_TIM5_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +# define PWM_TIM5_CHANNEL4 1 +#else +# define PWM_TIM5_CHANNEL4 0 +#endif +#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ + PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) + +#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +# define PWM_TIM8_CHANNEL1 1 +#else +# define PWM_TIM8_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +# define PWM_TIM8_CHANNEL2 1 +#else +# define PWM_TIM8_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +# define PWM_TIM8_CHANNEL3 1 +#else +# define PWM_TIM8_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +# define PWM_TIM8_CHANNEL4 1 +#else +# define PWM_TIM8_CHANNEL4 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +# define PWM_TIM8_CHANNEL5 1 +#else +# define PWM_TIM8_CHANNEL5 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +# define PWM_TIM8_CHANNEL6 1 +#else +# define PWM_TIM8_CHANNEL6 0 +#endif +#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ + PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ + PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) + +#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +# define PWM_TIM12_CHANNEL1 1 +#else +# define PWM_TIM12_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +# define PWM_TIM12_CHANNEL2 1 +#else +# define PWM_TIM12_CHANNEL2 0 +#endif +#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) + +#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +# define PWM_TIM13_CHANNEL1 1 +#else +# define PWM_TIM13_CHANNEL1 0 +#endif +#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) + +#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +# define PWM_TIM14_CHANNEL1 1 +#else +# define PWM_TIM14_CHANNEL1 0 +#endif +#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) + +#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +# define PWM_TIM15_CHANNEL1 1 +#else +# define PWM_TIM15_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +# define PWM_TIM15_CHANNEL2 1 +#else +# define PWM_TIM15_CHANNEL2 0 +#endif +#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) + +#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +# define PWM_TIM16_CHANNEL1 1 +#else +# define PWM_TIM16_CHANNEL1 0 +#endif +#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 + +#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +# define PWM_TIM17_CHANNEL1 1 +#else +# define PWM_TIM17_CHANNEL1 0 +#endif +#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 + +#else /* !CONFIG_PWM_MULTICHAN */ + +/* For each timer that is enabled for PWM usage, we need the following additional + * configuration settings: + * + * CONFIG_STM32H7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the case + * where there are multiple pin selections, the correct setting must be provided + * in the arch/board/board.h file. + * + * NOTE: The STM32 timers are each capable of generating different signals on + * each of the four channels with different duty cycles. That capability is + * not supported by this driver: Only one output channel per timer. + */ + +#ifdef CONFIG_STM32H7_TIM1_PWM +# if !defined(CONFIG_STM32H7_TIM1_CHANNEL) +# error "CONFIG_STM32H7_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM1_CHANNEL == 1 +# define CONFIG_STM32H7_TIM1_CHANNEL1 1 +# define CONFIG_STM32H7_TIM1_CH1MODE CONFIG_STM32H7_TIM1_CHMODE +# elif CONFIG_STM32H7_TIM1_CHANNEL == 2 +# define CONFIG_STM32H7_TIM1_CHANNEL2 1 +# define CONFIG_STM32H7_TIM1_CH2MODE CONFIG_STM32H7_TIM1_CHMODE +# elif CONFIG_STM32H7_TIM1_CHANNEL == 3 +# define CONFIG_STM32H7_TIM1_CHANNEL3 1 +# define CONFIG_STM32H7_TIM1_CH3MODE CONFIG_STM32H7_TIM1_CHMODE +# elif CONFIG_STM32H7_TIM1_CHANNEL == 4 +# define CONFIG_STM32H7_TIM1_CHANNEL4 1 +# define CONFIG_STM32H7_TIM1_CH4MODE CONFIG_STM32H7_TIM1_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM1_CHANNEL" +# endif +# define PWM_TIM1_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM2_PWM +# if !defined(CONFIG_STM32H7_TIM2_CHANNEL) +# error "CONFIG_STM32H7_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM2_CHANNEL == 1 +# define CONFIG_STM32H7_TIM2_CHANNEL1 1 +# define CONFIG_STM32H7_TIM2_CH1MODE CONFIG_STM32H7_TIM2_CHMODE +# elif CONFIG_STM32H7_TIM2_CHANNEL == 2 +# define CONFIG_STM32H7_TIM2_CHANNEL2 1 +# define CONFIG_STM32H7_TIM2_CH2MODE CONFIG_STM32H7_TIM2_CHMODE +# elif CONFIG_STM32H7_TIM2_CHANNEL == 3 +# define CONFIG_STM32H7_TIM2_CHANNEL3 1 +# define CONFIG_STM32H7_TIM2_CH3MODE CONFIG_STM32H7_TIM2_CHMODE +# elif CONFIG_STM32H7_TIM2_CHANNEL == 4 +# define CONFIG_STM32H7_TIM2_CHANNEL4 1 +# define CONFIG_STM32H7_TIM2_CH4MODE CONFIG_STM32H7_TIM2_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM2_CHANNEL" +# endif +# define PWM_TIM2_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM3_PWM +# if !defined(CONFIG_STM32H7_TIM3_CHANNEL) +# error "CONFIG_STM32H7_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM3_CHANNEL == 1 +# define CONFIG_STM32H7_TIM3_CHANNEL1 1 +# define CONFIG_STM32H7_TIM3_CH1MODE CONFIG_STM32H7_TIM3_CHMODE +# elif CONFIG_STM32H7_TIM3_CHANNEL == 2 +# define CONFIG_STM32H7_TIM3_CHANNEL2 1 +# define CONFIG_STM32H7_TIM3_CH2MODE CONFIG_STM32H7_TIM3_CHMODE +# elif CONFIG_STM32H7_TIM3_CHANNEL == 3 +# define CONFIG_STM32H7_TIM3_CHANNEL3 1 +# define CONFIG_STM32H7_TIM3_CH3MODE CONFIG_STM32H7_TIM3_CHMODE +# elif CONFIG_STM32H7_TIM3_CHANNEL == 4 +# define CONFIG_STM32H7_TIM3_CHANNEL4 1 +# define CONFIG_STM32H7_TIM3_CH4MODE CONFIG_STM32H7_TIM3_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM3_CHANNEL" +# endif +# define PWM_TIM3_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM4_PWM +# if !defined(CONFIG_STM32H7_TIM4_CHANNEL) +# error "CONFIG_STM32H7_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM4_CHANNEL == 1 +# define CONFIG_STM32H7_TIM4_CHANNEL1 1 +# define CONFIG_STM32H7_TIM4_CH1MODE CONFIG_STM32H7_TIM4_CHMODE +# elif CONFIG_STM32H7_TIM4_CHANNEL == 2 +# define CONFIG_STM32H7_TIM4_CHANNEL2 1 +# define CONFIG_STM32H7_TIM4_CH2MODE CONFIG_STM32H7_TIM4_CHMODE +# elif CONFIG_STM32H7_TIM4_CHANNEL == 3 +# define CONFIG_STM32H7_TIM4_CHANNEL3 1 +# define CONFIG_STM32H7_TIM4_CH3MODE CONFIG_STM32H7_TIM4_CHMODE +# elif CONFIG_STM32H7_TIM4_CHANNEL == 4 +# define CONFIG_STM32H7_TIM4_CHANNEL4 1 +# define CONFIG_STM32H7_TIM4_CH4MODE CONFIG_STM32H7_TIM4_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM4_CHANNEL" +# endif +# define PWM_TIM4_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM5_PWM +# if !defined(CONFIG_STM32H7_TIM5_CHANNEL) +# error "CONFIG_STM32H7_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM5_CHANNEL == 1 +# define CONFIG_STM32H7_TIM5_CHANNEL1 1 +# define CONFIG_STM32H7_TIM5_CH1MODE CONFIG_STM32H7_TIM5_CHMODE +# elif CONFIG_STM32H7_TIM5_CHANNEL == 2 +# define CONFIG_STM32H7_TIM5_CHANNEL2 1 +# define CONFIG_STM32H7_TIM5_CH2MODE CONFIG_STM32H7_TIM5_CHMODE +# elif CONFIG_STM32H7_TIM5_CHANNEL == 3 +# define CONFIG_STM32H7_TIM5_CHANNEL3 1 +# define CONFIG_STM32H7_TIM5_CH3MODE CONFIG_STM32H7_TIM5_CHMODE +# elif CONFIG_STM32H7_TIM5_CHANNEL == 4 +# define CONFIG_STM32H7_TIM5_CHANNEL4 1 +# define CONFIG_STM32H7_TIM5_CH4MODE CONFIG_STM32H7_TIM5_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM5_CHANNEL" +# endif +# define PWM_TIM5_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM8_PWM +# if !defined(CONFIG_STM32H7_TIM8_CHANNEL) +# error "CONFIG_STM32H7_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM8_CHANNEL == 1 +# define CONFIG_STM32H7_TIM8_CHANNEL1 1 +# define CONFIG_STM32H7_TIM8_CH1MODE CONFIG_STM32H7_TIM8_CHMODE +# elif CONFIG_STM32H7_TIM8_CHANNEL == 2 +# define CONFIG_STM32H7_TIM8_CHANNEL2 1 +# define CONFIG_STM32H7_TIM8_CH2MODE CONFIG_STM32H7_TIM8_CHMODE +# elif CONFIG_STM32H7_TIM8_CHANNEL == 3 +# define CONFIG_STM32H7_TIM8_CHANNEL3 1 +# define CONFIG_STM32H7_TIM8_CH3MODE CONFIG_STM32H7_TIM8_CHMODE +# elif CONFIG_STM32H7_TIM8_CHANNEL == 4 +# define CONFIG_STM32H7_TIM8_CHANNEL4 1 +# define CONFIG_STM32H7_TIM8_CH4MODE CONFIG_STM32H7_TIM8_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM8_CHANNEL" +# endif +# define PWM_TIM8_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM12_PWM +# if !defined(CONFIG_STM32H7_TIM12_CHANNEL) +# error "CONFIG_STM32H7_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM12_CHANNEL == 1 +# define CONFIG_STM32H7_TIM12_CHANNEL1 1 +# define CONFIG_STM32H7_TIM12_CH1MODE CONFIG_STM32H7_TIM12_CHMODE +# elif CONFIG_STM32H7_TIM12_CHANNEL == 2 +# define CONFIG_STM32H7_TIM12_CHANNEL2 1 +# define CONFIG_STM32H7_TIM12_CH2MODE CONFIG_STM32H7_TIM12_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM12_CHANNEL" +# endif +# define PWM_TIM12_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM13_PWM +# if !defined(CONFIG_STM32H7_TIM13_CHANNEL) +# error "CONFIG_STM32H7_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM13_CHANNEL == 1 +# define CONFIG_STM32H7_TIM13_CHANNEL1 1 +# define CONFIG_STM32H7_TIM13_CH1MODE CONFIG_STM32H7_TIM13_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM13_CHANNEL" +# endif +# define PWM_TIM13_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM14_PWM +# if !defined(CONFIG_STM32H7_TIM14_CHANNEL) +# error "CONFIG_STM32H7_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM14_CHANNEL == 1 +# define CONFIG_STM32H7_TIM14_CHANNEL1 1 +# define CONFIG_STM32H7_TIM14_CH1MODE CONFIG_STM32H7_TIM14_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM14_CHANNEL" +# endif +# define PWM_TIM14_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM15_PWM +# if !defined(CONFIG_STM32H7_TIM15_CHANNEL) +# error "CONFIG_STM32H7_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM15_CHANNEL == 1 +# define CONFIG_STM32H7_TIM15_CHANNEL1 1 +# define CONFIG_STM32H7_TIM15_CH1MODE CONFIG_STM32H7_TIM15_CHMODE +# elif CONFIG_STM32H7_TIM15_CHANNEL == 2 +# define CONFIG_STM32H7_TIM15_CHANNEL2 1 +# define CONFIG_STM32H7_TIM15_CH2MODE CONFIG_STM32H7_TIM15_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM15_CHANNEL" +# endif +# define PWM_TIM15_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM16_PWM +# if !defined(CONFIG_STM32H7_TIM16_CHANNEL) +# error "CONFIG_STM32H7_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM16_CHANNEL == 1 +# define CONFIG_STM32H7_TIM16_CHANNEL1 1 +# define CONFIG_STM32H7_TIM16_CH1MODE CONFIG_STM32H7_TIM16_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM16_CHANNEL" +# endif +# define PWM_TIM16_NCHANNELS 1 +#endif + +#ifdef CONFIG_STM32H7_TIM17_PWM +# if !defined(CONFIG_STM32H7_TIM17_CHANNEL) +# error "CONFIG_STM32H7_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32H7_TIM17_CHANNEL == 1 +# define CONFIG_STM32H7_TIM17_CHANNEL1 1 +# define CONFIG_STM32H7_TIM17_CH1MODE CONFIG_STM32H7_TIM17_CHMODE +# else +# error "Unsupported value of CONFIG_STM32H7_TIM17_CHANNEL" +# endif +# define PWM_TIM17_NCHANNELS 1 +#endif + +#endif /* CONFIG_STM32H7_PWM_MULTICHAN */ + +#ifdef CONFIG_STM32H7_TIM1_CH1OUT +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +#else +# define PWM_TIM1_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +# define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT +#else +# define PWM_TIM1_CH1NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CH2OUT +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +#else +# define PWM_TIM1_CH2CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +# define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT +#else +# define PWM_TIM1_CH2NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CH3OUT +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +#else +# define PWM_TIM1_CH3CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +# define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT +#else +# define PWM_TIM1_CH3NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM1_CH4OUT +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +#else +# define PWM_TIM1_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM2_CH1OUT +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +#else +# define PWM_TIM2_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM2_CH2OUT +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +#else +# define PWM_TIM2_CH2CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM2_CH3OUT +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +#else +# define PWM_TIM2_CH3CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM2_CH4OUT +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +#else +# define PWM_TIM2_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM3_CH1OUT +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +#else +# define PWM_TIM3_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM3_CH2OUT +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +#else +# define PWM_TIM3_CH2CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM3_CH3OUT +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +#else +# define PWM_TIM3_CH3CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM3_CH4OUT +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +#else +# define PWM_TIM3_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM4_CH1OUT +# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT +#else +# define PWM_TIM4_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM4_CH2OUT +# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT +#else +# define PWM_TIM4_CH2CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM4_CH3OUT +# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT +#else +# define PWM_TIM4_CH3CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM4_CH4OUT +# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT +#else +# define PWM_TIM4_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM5_CH1OUT +# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT +#else +# define PWM_TIM5_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM5_CH2OUT +# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT +#else +# define PWM_TIM5_CH2CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM5_CH3OUT +# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT +#else +# define PWM_TIM5_CH3CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM5_CH4OUT +# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT +#else +# define PWM_TIM5_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM8_CH1OUT +# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT +#else +# define PWM_TIM8_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +# define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT +#else +# define PWM_TIM8_CH1NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CH2OUT +# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT +#else +# define PWM_TIM8_CH2CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +# define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT +#else +# define PWM_TIM8_CH2NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CH3OUT +# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT +#else +# define PWM_TIM8_CH3CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +# define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT +#else +# define PWM_TIM8_CH3NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM8_CH4OUT +# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT +#else +# define PWM_TIM8_CH4CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM12_CH1OUT +# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT +#else +# define PWM_TIM12_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM12_CH2OUT +# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT +#else +# define PWM_TIM12_CH2CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM13_CH1OUT +# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT +#else +# define PWM_TIM13_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM14_CH1OUT +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +#else +# define PWM_TIM14_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM15_CH1OUT +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +#else +# define PWM_TIM15_CH1CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +# define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT +#else +# define PWM_TIM15_CH1NCFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM15_CH2OUT +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +#else +# define PWM_TIM15_CH2CFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM16_CH1OUT +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +#else +# define PWM_TIM16_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +# define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT +#else +# define PWM_TIM16_CH1NCFG 0 +#endif + +#ifdef CONFIG_STM32H7_TIM17_CH1OUT +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +#else +# define PWM_TIM17_CH1CFG 0 +#endif +#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +# define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT +#else +# define PWM_TIM17_CH1NCFG 0 +#endif + +/* Complementary outputs support */ + +#if defined(CONFIG_STM32H7_TIM1_CH1NOUT) || defined(CONFIG_STM32H7_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32H7_TIM1_CH3NOUT) +# define HAVE_TIM1_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32H7_TIM8_CH1NOUT) || defined(CONFIG_STM32H7_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32H7_TIM8_CH3NOUT) +# define HAVE_TIM8_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32H7_TIM15_CH1NOUT) +# define HAVE_TIM15_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32H7_TIM16_CH1NOUT) +# define HAVE_TIM16_COMPLEMENTARY +#endif +#if defined(CONFIG_STM32H7_TIM17_CH1NOUT) +# define HAVE_TIM17_COMPLEMENTARY +#endif +#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ + defined(HAVE_TIM15_COMPLEMENTARY) || defined(HAVE_TIM16_COMPLEMENTARY) || \ + defined(HAVE_TIM17_COMPLEMENTARY) +# define HAVE_PWM_COMPLEMENTARY +#endif + +/* Low-level ops helpers ************************************************************/ + +#ifdef CONFIG_STM32H7_PWM_LL_OPS + +/* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops access + * can be found in stm32_pwm_dev_s + */ + +#define PWM_SETUP(dev) \ + (dev)->ops->setup((FAR struct pwm_lowerhalf_s *)dev) +#define PWM_SHUTDOWN(dev) \ + (dev)->ops->shutdown((FAR struct pwm_lowerhalf_s *)dev) +#define PWM_CCR_UPDATE(dev, index, ccr) \ + (dev)->llops->ccr_update((FAR struct pwm_lowerhalf_s *)dev, index, ccr) +#define PWM_MODE_UPDATE(dev, index, mode) \ + (dev)->llops->mode_update((FAR struct pwm_lowerhalf_s *)dev, index, mode) +#define PWM_CCR_GET(dev, index) \ + (dev)->llops->ccr_get((FAR struct pwm_lowerhalf_s *)dev, index) +#define PWM_ARR_UPDATE(dev, arr) \ + (dev)->llops->arr_update((FAR struct pwm_lowerhalf_s *)dev, arr) +#define PWM_ARR_GET(dev) \ + (dev)->llops->arr_get((FAR struct pwm_lowerhalf_s *)dev) +#define PWM_OUTPUTS_ENABLE(dev, out, state) \ + (dev)->llops->outputs_enable((FAR struct pwm_lowerhalf_s *)dev, out, state) +#define PWM_SOFT_UPDATE(dev) \ + (dev)->llops->soft_update((FAR struct pwm_lowerhalf_s *)dev) +#define PWM_CONFIGURE(dev) \ + (dev)->llops->configure((FAR struct pwm_lowerhalf_s *)dev) +#define PWM_SOFT_BREAK(dev, state) \ + (dev)->llops->soft_break((FAR struct pwm_lowerhalf_s *)dev, state) +#define PWM_FREQ_UPDATE(dev, freq) \ + (dev)->llops->freq_update((FAR struct pwm_lowerhalf_s *)dev, freq) +#define PWM_TIM_ENABLE(dev, state) \ + (dev)->llops->tim_enable((FAR struct pwm_lowerhalf_s *)dev, state) +#ifdef CONFIG_DEBUG_PWM_INFO +# define PWM_DUMP_REGS(dev) \ + (dev)->llops->dump_regs((FAR struct pwm_lowerhalf_s *)dev) +#else +# define PWM_DUMP_REGS(dev) +#endif +#define PWM_DT_UPDATE(dev, dt) \ + (dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt) + +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/* Timer mode */ + +enum stm32_pwm_tim_mode_e +{ + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, +}; + +/* Timer output polarity */ + +enum stm32_pwm_pol_e +{ + STM32_POL_POS = 0, + STM32_POL_NEG = 1, +}; + +/* Timer output IDLE state */ + +enum stm32_pwm_idle_e +{ + STM32_IDLE_INACTIVE = 0, + STM32_IDLE_ACTIVE = 1 +}; + +/* PWM channel mode */ + +enum stm32_pwm_chanmode_e +{ + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ +#ifdef HAVE_IP_TIMERS_V2 + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ +#endif +}; + +/* PWM timer channel */ + +enum stm32_pwm_chan_e +{ + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, +#ifdef HAVE_IP_TIMERS_V2 + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, +#endif +}; + +/* PWM timer channel output */ + +enum stm32_pwm_output_e +{ + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), + /* 1 << 7 reserved - no complementary output for CH4 */ +#ifdef HAVE_IP_TIMERS_V2 + /* Only available inside micro */ + + STM32_PWM_OUT5 = (1 << 8), + /* 1 << 9 reserved - no complementary output for CH5 */ + STM32_PWM_OUT6 = (1 << 10), + /* 1 << 11 reserved - no complementary output for CH6 */ +#endif +}; + +#ifdef CONFIG_STM32H7_PWM_LL_OPS + +/* This structure provides the publicly visable representation of the + * "lower-half" PWM driver structure. + */ + +struct stm32_pwm_dev_s +{ + /* The first field of this state structure must be a pointer to the PWM + * callback structure to be consistent with upper-half PWM driver. + */ + + FAR const struct pwm_ops_s *ops; + + /* Publicly visible portion of the "lower-half" PWM driver structure */ + + FAR const struct stm32_pwm_ops_s *llops; + + /* Require cast-compatibility with private "lower-half" PWM strucutre */ +}; + +/* Low-level operations for PWM */ + +struct pwm_lowerhalf_s; +struct stm32_pwm_ops_s +{ + /* Update CCR register */ + + int (*ccr_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr); + + /* Update PWM mode */ + + int (*mode_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t mode); + + /* Get CCR register */ + + uint32_t (*ccr_get)(FAR struct pwm_lowerhalf_s *dev, uint8_t index); + + /* Update ARR register */ + + int (*arr_update)(FAR struct pwm_lowerhalf_s *dev, uint32_t arr); + + /* Get ARR register */ + + uint32_t (*arr_get)(FAR struct pwm_lowerhalf_s *dev); + + /* Enable outputs */ + + int (*outputs_enable)(FAR struct pwm_lowerhalf_s *dev, uint16_t outputs, bool state); + + /* Software update */ + + int (*soft_update)(FAR struct pwm_lowerhalf_s *dev); + + /* PWM configure */ + + int (*configure)(FAR struct pwm_lowerhalf_s *dev); + + /* Software break */ + + int (*soft_break)(FAR struct pwm_lowerhalf_s *dev, bool state); + + /* Update frequency */ + + int (*freq_update)(FAR struct pwm_lowerhalf_s *dev, uint32_t frequency); + + /* Enable timer counter */ + + int (*tim_enable)(FAR struct pwm_lowerhalf_s *dev, bool state); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Dump timer registers */ + + int (*dump_regs)(FAR struct pwm_lowerhalf_s *dev); +#endif + +#ifdef HAVE_PWM_COMPLEMENTARY + /* Deadtime update */ + + int (*dt_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t dt); +#endif +}; + +#endif /* CONFIG_STM32H7_PWM_LL_OPS */ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. The number of valid timer + * IDs varies with the STM32 MCU and MCU family but is somewhere in + * the range of {1,..,17}. + * + * Returned Value: + * On success, a pointer to the STM32 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ************************************************************************************/ + +FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32H7_PWM */ +#endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWM_H */ diff --git a/configs/nucleo-h743zi/include/board.h b/configs/nucleo-h743zi/include/board.h index 382bfca1896..e0faca428db 100644 --- a/configs/nucleo-h743zi/include/board.h +++ b/configs/nucleo-h743zi/include/board.h @@ -380,6 +380,16 @@ #define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */ #define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 /* PA4 */ +/* TIM1 */ + +#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_2 /* PE9 - D6 */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1NOUT_3 /* PE8 - D42 */ +#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_2 /* PE11 - D5 */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_3 /* PE10 - D40 */ +#define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_2 /* PE13 - D3 */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3NOUT_3 /* PE12 - D39 */ +#define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_2 /* PE14 - D38 */ + /* DMA ******************************************************************************/ #define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* DMA1 */