From 01c98df18c402f7ec8b328f6300f43d22757bac3 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 20 Aug 2017 09:30:19 +0200 Subject: [PATCH 1/5] STM32F33: remove redundant DAC file --- arch/arm/src/stm32/chip/stm32_dac.h | 39 +++- arch/arm/src/stm32/chip/stm32f33xxx_dac.h | 238 ---------------------- arch/arm/src/stm32/stm32_dac.h | 4 - 3 files changed, 38 insertions(+), 243 deletions(-) delete mode 100644 arch/arm/src/stm32/chip/stm32f33xxx_dac.h diff --git a/arch/arm/src/stm32/chip/stm32_dac.h b/arch/arm/src/stm32/chip/stm32_dac.h index 07e4fe6c671..cd4e3ff90b7 100644 --- a/arch/arm/src/stm32/chip/stm32_dac.h +++ b/arch/arm/src/stm32/chip/stm32_dac.h @@ -129,15 +129,25 @@ #define DAC_CR_TSEL_SHIFT (3) /* Bits 3-5: DAC channel trigger selection */ #define DAC_CR_TSEL_MASK (7 << DAC_CR_TSEL_SHIFT) # define DAC_CR_TSEL_TIM6 (0 << DAC_CR_TSEL_SHIFT) /* Timer 6 TRGO event */ -#ifdef CONFIG_STM32_CONNECTIVITYLINE +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F33XX) # define DAC_CR_TSEL_TIM3 (1 << DAC_CR_TSEL_SHIFT) /* Timer 3 TRGO event */ #else # define DAC_CR_TSEL_TIM8 (1 << DAC_CR_TSEL_SHIFT) /* Timer 8 TRGO event */ #endif # define DAC_CR_TSEL_TIM7 (2 << DAC_CR_TSEL_SHIFT) /* Timer 7 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL_TIM15 (3 << DAC_CR_TSEL_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL_HRT1TRG1 (3 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG1 event */ +#else # define DAC_CR_TSEL_TIM5 (3 << DAC_CR_TSEL_SHIFT) /* Timer 5 TRGO event */ +#endif # define DAC_CR_TSEL_TIM2 (4 << DAC_CR_TSEL_SHIFT) /* Timer 2 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL_HRT1TRG2 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG2 event, or */ +# define DAC_CR_TSEL_HRT1TRG3 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG3 event */ +#else # define DAC_CR_TSEL_TIM4 (5 << DAC_CR_TSEL_SHIFT) /* Timer 4 TRGO event */ +#endif # define DAC_CR_TSEL_EXT9 (6 << DAC_CR_TSEL_SHIFT) /* External line9 */ # define DAC_CR_TSEL_SW (7 << DAC_CR_TSEL_SHIFT) /* Software trigger */ #define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */ @@ -170,11 +180,25 @@ #define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ #define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) # define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */ +#else # define DAC_CR_TSEL1_TIM8 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 8 TRGO event */ +#endif # define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL1_HRT1TRG1 (3 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG1 event (DAC1 only) */ +#else # define DAC_CR_TSEL1_TIM5 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 5 TRGO event */ +#endif # define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL1_HRT1TRG2 (5 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG2 event (DAC1), or */ +# define DAC_CR_TSEL1_HRT1TRG3 (5 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG3 event (DAC2) */ +#else # define DAC_CR_TSEL1_TIM4 (5 << DAC_CR_TSEL1_SHIFT) /* Timer 4 TRGO event */ +#endif # define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ # define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ #define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ @@ -205,11 +229,24 @@ #define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ #define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) # define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */ +#else # define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */ +#endif # define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL2_TIM15 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL2_HRT1TRG1 (3 << DAC_CR_TSEL2_SHIFT) /* HRTIM1 DACTRG1 event */ +#else # define DAC_CR_TSEL2_TIM5 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 5 TRGO event */ +#endif # define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL2_HRT1TRG2 (5 << DAC_CR_TSEL2_SHIFT) /* HRTIM1 DACTRG2 event */ +#else # define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */ +#endif # define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ # define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ #define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_dac.h b/arch/arm/src/stm32/chip/stm32f33xxx_dac.h deleted file mode 100644 index d3b4d920206..00000000000 --- a/arch/arm/src/stm32/chip/stm32f33xxx_dac.h +++ /dev/null @@ -1,238 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32/chip/stm32f33xxx_dac.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Modified for STM32F334 by Mateusz Szafoni - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ - -/* Register Addresses ***************************************************************/ - -/* DAC1 */ - -# define STM32_DAC1_CR (STM32_DAC1_BASE+STM32_DAC_CR_OFFSET) -# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE+STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE+STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE+STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE+STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE+STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE+STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE+STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE+STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE+STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE+STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC1_DOR1 (STM32_DAC1_BASE+STM32_DAC_DOR1_OFFSET) -# define STM32_DAC1_DOR2 (STM32_DAC1_BASE+STM32_DAC_DOR2_OFFSET) -# define STM32_DAC1_SR (STM32_DAC1_BASE+STM32_DAC_SR_OFFSET) - -/* DAC2 */ - -# define STM32_DAC2_CR (STM32_DAC2_BASE+STM32_DAC_CR_OFFSET) -# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE+STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE+STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE+STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE+STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE+STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE+STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE+STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE+STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE+STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE+STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC2_DOR1 (STM32_DAC2_BASE+STM32_DAC_DOR1_OFFSET) -# define STM32_DAC2_DOR2 (STM32_DAC2_BASE+STM32_DAC_DOR2_OFFSET) -# define STM32_DAC2_SR (STM32_DAC2_BASE+STM32_DAC_SR_OFFSET) - -/* Register Bitfield Definitions ****************************************************/ - -/* DAC control register */ -/* These definitions may be used with the full, 32-bit register */ - -#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ -#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ -#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ -#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) -# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ -# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */ -# define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */ -# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */ -# define DAC_CR_TSEL_HRT1TRG1 (3 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG1 event (DAC1 only) */ -# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ -# define DAC_CR_TSEL_HRT1TRG2 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG2 event (DAC1), or */ -# define DAC_CR_TSEL_HRT1TRG3 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG3 event (DAC2) */ -# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ -# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ -#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) -# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ -#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) -# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP1_AMP7 (2 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP1_AMP15 (3 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP1_AMP31 (4 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP1_AMP63 (5 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP1_AMP127 (6 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP1_AMP255 (7 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP1_AMP511 (8 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ -#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ - -#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ -#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ -#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ -#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) -# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ -# define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */ -# define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */ -# define DAC_CR_TSEL2_TIM5 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 5 TRGO event */ -# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ -# define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */ -# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ -# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ -#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) -# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ -#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) -# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP2_AMP7 (2 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP2_AMP15 (3 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP2_AMP31 (4 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP2_AMP63 (5 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP2_AMP127 (6 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP2_AMP255 (7 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP2_AMP511 (8 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ -#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ - -/* DAC software trigger register */ - -#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ - -/* DAC channel 1/2 12-bit right-aligned data holding register */ - -#define DAC_DHR12R_MASK (0x0fff) - -/* DAC channel 1/2 12-bit left aligned data holding register */ - -#define DAC_DHR12L_MASK (0xfff0) - -/* DAC channel 1/2 8-bit right aligned data holding register */ - -#define DAC_DHR8R_MASK (0x00ff) - -/* Dual DAC 12-bit right-aligned data holding register */ - -#define DAC_DHR12RD_DACC_SHIFT(n) (((n)-1) << 4) -#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) - -#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) -#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) - -/* Dual DAC 12-bit left-aligned data holding register */ - -#define DAC_DHR12LD_DACC_SHIFT(n) ((((n)-1) << 4) + 4) -#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) - -#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) -#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) - -/* DUAL DAC 8-bit right aligned data holding register */ - -#define DAC_DHR8RD_DACC_SHIFT(n) (((n)-1) << 3) -#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) - -#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) -#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) - -/* DAC channel 1/2 data output register */ - -#define DAC_DOR_MASK (0x0fff) - -/* DAC status register */ - -#define DAC_SR_DMAUDR(n) (1 << ((((n)-1) << 4) + 13)) -#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dac.h b/arch/arm/src/stm32/stm32_dac.h index 37ba66f0939..3718a245a4d 100644 --- a/arch/arm/src/stm32/stm32_dac.h +++ b/arch/arm/src/stm32/stm32_dac.h @@ -43,11 +43,7 @@ #include #include "chip.h" -#ifdef CONFIG_STM32_STM32F33XX -#include "chip/stm32f33xxx_dac.h" -#else #include "chip/stm32_dac.h" -#endif #include From 241c42447f40af5eaaae2e728bf13483c968dccb Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 20 Aug 2017 09:44:03 +0200 Subject: [PATCH 2/5] stm32f33xxx_comp.h: typos --- arch/arm/src/stm32/chip/stm32f33xxx_comp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_comp.h b/arch/arm/src/stm32/chip/stm32f33xxx_comp.h index 0e83a1c965c..cb3ce96a8fc 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_comp.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_comp.h @@ -76,8 +76,8 @@ # define COMP_CSR_INMSEL_DAC1CH1 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: DAC1_CH1 output if enabled */ # define COMP_CSR_INMSEL_DAC1CH2 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH2 output */ # define COMP_CSR_INMSEL_PA2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA2 (COMP2 only) */ -# define COMP_CSR_INMSEL_PB2 (7 << COMP4_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */ -# define COMP_CSR_INMSEL_PB15 (7 << COMP6_CSR_INMSEL_SHIFT) /* 0110: PB15 (COMP6 only) */ +# define COMP_CSR_INMSEL_PB2 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */ +# define COMP_CSR_INMSEL_PB15 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB15 (COMP6 only) */ /* 1000: DAC2_CH1 output, look at bit 22 */ /* Bits 7-9: Reserved */ #define COMP_CSR_OUTSEL_SHIFT (4) /* Bits 10-13: Comparator output selection */ From 30ebd32ab4ceba55a4a7a8add4d18d52b11b4b67 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 20 Aug 2017 09:46:51 +0200 Subject: [PATCH 3/5] stm32f33xxx_pinmap.h: missing define --- arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h index e0ad65fc1af..d9d3826f033 100644 --- a/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h @@ -128,7 +128,8 @@ /* Comparator Inputs inverting*/ -#define GPIO_COMP2_INM (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) +#define GPIO_COMP2_INM_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2) +#define GPIO_COMP2_INM_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) #define GPIO_COMP4_INM_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN2) #define GPIO_COMP4_INM_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) #define GPIO_COMP6_INM_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4) From 1479fd6075fd7f016a088744769199b2e3930988 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 20 Aug 2017 09:54:17 +0200 Subject: [PATCH 4/5] stm32_comp: add default INM configuration and some missing COMP1,3,5,7 code --- arch/arm/src/stm32/stm32_comp.c | 48 ++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c index b580f853987..ada26004210 100644 --- a/arch/arm/src/stm32/stm32_comp.c +++ b/arch/arm/src/stm32/stm32_comp.c @@ -104,6 +104,10 @@ # ifndef COMP2_LOCK # define COMP2_LOCK COMP_LOCK_DEFAULT # endif +# ifndef GPIO_COMP2_INM +# warning "GPIO_COMP2_INM not selected. Set default value to GPIO_COMP2_INM1" +# define GPIO_COMP2_INM GPIO_COMP4_INM_1 +# endif #endif /* COMP4 default configuration **********************************************/ @@ -124,6 +128,10 @@ # ifndef COMP4_LOCK # define COMP4_LOCK COMP_LOCK_DEFAULT # endif +# ifndef GPIO_COMP4_INM +# warning "GPIO_COMP4_INM not selected. Set default value to GPIO_COMP4_INM1" +# define GPIO_COMP4_INM GPIO_COMP4_INM_1 +# endif #endif /* COMP6 default configuration **********************************************/ @@ -144,6 +152,10 @@ # ifndef COMP6_LOCK # define COMP6_LOCK COMP_LOCK_DEFAULT # endif +# ifndef GPIO_COMP6_INM +# warning "GPIO_COMP6_INM not selected. Set default value to GPIO_COMP6_INM1" +# define GPIO_COMP6_INM GPIO_COMP6_INM_1 +# endif #endif /**************************************************************************** @@ -528,9 +540,11 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) break; #endif +#ifdef CONFIG_STM32_COMP2 case STM32_COMP2_CSR: index = 2; break; +#endif #ifdef CONFIG_STM32_COMP3 case STM32_COMP3_CSR: @@ -538,9 +552,11 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) break; #endif +#ifdef CONFIG_STM32_COMP4 case STM32_COMP4_CSR: index = 4; break; +#endif #ifdef CONFIG_STM32_COMP5 case STM32_COMP5_CSR: @@ -548,9 +564,11 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) break; #endif +#ifdef CONFIG_STM32_COMP6 case STM32_COMP6_CSR: index = 6; break; +#endif #ifdef CONFIG_STM32_COMP7 case STM32_COMP7_CSR: @@ -566,24 +584,48 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) switch (index) { +#ifdef CONFIG_STM32_COMP1 + case 1: + stm32_configgpio(GPIO_COMP1_INP); + break; +#endif + #ifdef CONFIG_STM32_COMP2 case 2: stm32_configgpio(GPIO_COMP2_INP); break; #endif +#ifdef CONFIG_STM32_COMP3 + case 3: + stm32_configgpio(GPIO_COMP3_INP); + break; +#endif + #ifdef CONFIG_STM32_COMP4 case 4: stm32_configgpio(GPIO_COMP4_INP); break; #endif +#ifdef CONFIG_STM32_COMP5 + case 5: + stm32_configgpio(GPIO_COMP5_INP); + break; +#endif + #ifdef CONFIG_STM32_COMP6 case 6: stm32_configgpio(GPIO_COMP6_INP); break; #endif +#ifdef CONFIG_STM32_COMP7 + case 7: + stm32_configgpio(GPIO_COMP7_INP); + break; +#endif + default: return -EINVAL; } @@ -622,11 +664,15 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv) switch (index) { + /* TODO: Inverting input pin configuration for COMP1/3/5/7 */ + #ifdef CONFIG_STM32_COMP2 case 2: { + /* COMP2_INM can be PA2 or PA4 */ + stm32_configgpio(GPIO_COMP2_INM); - regval |= COMP_CSR_INMSEL_PA2; + regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4); break; } #endif From a8e8862ef9f9f199bb31ff1923662910f523c4e2 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 20 Aug 2017 19:02:56 +0200 Subject: [PATCH 5/5] stm32_dac.c: fix some configuration logic. When STM32_NDAC is greather than 1, then second channel is always DAC1OUT2. --- arch/arm/src/stm32/stm32_dac.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index bc997e48c37..fb0f477ad66 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -67,7 +67,7 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ -/* Up to 2 DAC interfaces are supported */ +/* Up to 2 DAC interfaces for up to 3 channels are supported */ #if STM32_NDAC < 2 # undef CONFIG_STM32_DAC2 @@ -417,7 +417,7 @@ static const struct dac_ops_s g_dacops = }; #ifdef CONFIG_STM32_DAC1 -/* Channel 1 */ +/* Channel 1: DAC1 channel 1 */ static struct stm32_chan_s g_dac1priv = { @@ -447,20 +447,15 @@ static struct dac_dev_s g_dac1dev = .ad_priv = &g_dac1priv, }; -/* Channel 2 */ +#if STM32_NDAC > 1 +/* Channel 2: DAC1 channel 2 */ static struct stm32_chan_s g_dac2priv = { .intf = 1, -#if STM32_NDAC < 2 - .pin = GPIO_DAC2_OUT, - .dro = STM32_DAC_DHR12R2, - .cr = STM32_DAC_CR, -#else .pin = GPIO_DAC1_OUT2, .dro = STM32_DAC1_DHR12R2, .cr = STM32_DAC1_CR, -#endif #ifdef CONFIG_STM32_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, @@ -476,10 +471,12 @@ static struct dac_dev_s g_dac2dev = .ad_ops = &g_dacops, .ad_priv = &g_dac2priv, }; -#endif +#endif /* STM32_NDAC > 1 */ + +#endif /* CONFIG_STM32_DAC1 */ #ifdef CONFIG_STM32_DAC2 -/* Channel 3 */ +/* Channel 3: DAC2 channel 1 */ static struct stm32_chan_s g_dac3priv = { @@ -494,7 +491,7 @@ static struct dac_dev_s g_dac3dev = .ad_ops = &g_dacops, .ad_priv = &g_dac3priv, }; -#endif +#endif /* CONFIG_STM32_DAC2 */ static struct stm32_dac_s g_dacblock;