mirror of
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arch/xtensa/esp32: Merge esp32_intdecode with esp32_irq.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche
committed by
Masayuki Ishikawa
Masayuki Ishikawa
parent
79cc12c034
commit
04cd520293
@@ -70,7 +70,7 @@ endif
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# Required ESP32 files (arch/xtensa/src/lx6)
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# Required ESP32 files (arch/xtensa/src/lx6)
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CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_gpio.c
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CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_gpio.c
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CHIP_CSRCS += esp32_intdecode.c esp32_irq.c esp32_region.c
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CHIP_CSRCS += esp32_irq.c esp32_region.c
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CHIP_CSRCS += esp32_user.c
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CHIP_CSRCS += esp32_user.c
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CHIP_CSRCS += esp32_dma.c
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CHIP_CSRCS += esp32_dma.c
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@@ -1,137 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_intdecode.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "xtensa.h"
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#include "esp32_irq.h"
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_intclear
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****************************************************************************/
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static inline void xtensa_intclear(uint32_t mask)
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{
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__asm__ __volatile__
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(
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"wsr %0, INTCLEAR\n"
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: "=r"(mask) : :
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);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: xtensa_int_decode
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*
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* Description:
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* Determine the peripheral that generated the interrupt and dispatch
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* handling to the registered interrupt handler via xtensa_irq_dispatch().
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*
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* Input Parameters:
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* cpuints - Set of pending interrupts valid for this level
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* regs - Saves processor state on the stack
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*
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* Returned Value:
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* Normally the same value as regs is returned. But, in the event of an
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* interrupt level context switch, the returned value will, instead point
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* to the saved processor state in the TCB of the newly started task.
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*
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****************************************************************************/
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uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
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{
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uint8_t *intmap;
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uint32_t mask;
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int bit;
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#ifdef CONFIG_SMP
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int cpu;
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#endif
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#ifdef CONFIG_SMP
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/* Select PRO or APP CPU interrupt mapping table */
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cpu = up_cpu_index();
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if (cpu != 0)
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{
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intmap = g_cpu1_intmap;
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}
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else
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#endif
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{
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intmap = g_cpu0_intmap;
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}
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/* Skip over zero bits, eight at a time */
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for (bit = 0, mask = 0xff;
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bit < ESP32_NCPUINTS && (cpuints & mask) == 0;
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bit += 8, mask <<= 8);
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/* Process each pending CPU interrupt */
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for (; bit < ESP32_NCPUINTS && cpuints != 0; bit++)
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{
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mask = (1 << bit);
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if ((cpuints & mask) != 0)
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{
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/* Extract the IRQ number from the mapping table */
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uint8_t irq = intmap[bit];
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DEBUGASSERT(irq != CPUINT_UNASSIGNED);
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/* Clear software or edge-triggered interrupt */
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xtensa_intclear(mask);
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/* Dispatch the CPU interrupt.
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*
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* NOTE that regs may be altered in the case of an interrupt
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* level context switch.
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*/
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regs = xtensa_irq_dispatch((int)irq, regs);
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/* Clear the bit in the pending interrupt so that perhaps
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* we can exit the look early.
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*/
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cpuints &= ~mask;
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}
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}
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return regs;
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}
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@@ -122,29 +122,29 @@ uintptr_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
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};
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};
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#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 */
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#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 */
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static volatile uint8_t g_irqmap[NR_IRQS];
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
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/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
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uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
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static uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
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static uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
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#endif
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#endif
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static volatile uint8_t g_irqmap[NR_IRQS];
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/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
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/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
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* content.
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* content.
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*/
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*/
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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uint32_t g_intenable[CONFIG_SMP_NCPUS];
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static uint32_t g_intenable[CONFIG_SMP_NCPUS];
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#else
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#else
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uint32_t g_intenable[1];
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static uint32_t g_intenable[1];
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#endif
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Bitsets for free, unallocated CPU interrupts available to peripheral
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/* Bitsets for free, unallocated CPU interrupts available to peripheral
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* devices.
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* devices.
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*/
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*/
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@@ -230,6 +230,19 @@ static inline void xtensa_disable_all(void)
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);
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);
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}
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}
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/****************************************************************************
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* Name: xtensa_intclear
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****************************************************************************/
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static inline void xtensa_intclear(uint32_t mask)
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{
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__asm__ __volatile__
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(
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"wsr %0, INTCLEAR\n"
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: "=r"(mask) : :
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);
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}
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/****************************************************************************
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/****************************************************************************
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* Name: esp32_intinfo
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* Name: esp32_intinfo
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*
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*
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@@ -828,3 +841,85 @@ void esp32_teardown_irq(int cpu, int periphid, int cpuint)
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leave_critical_section(irqstate);
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leave_critical_section(irqstate);
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}
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}
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/****************************************************************************
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* Name: xtensa_int_decode
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*
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* Description:
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* Determine the peripheral that generated the interrupt and dispatch
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* handling to the registered interrupt handler via xtensa_irq_dispatch().
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*
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* Input Parameters:
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* cpuints - Set of pending interrupts valid for this level
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* regs - Saves processor state on the stack
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*
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* Returned Value:
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* Normally the same value as regs is returned. But, in the event of an
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* interrupt level context switch, the returned value will, instead point
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* to the saved processor state in the TCB of the newly started task.
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*
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****************************************************************************/
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uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
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{
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uint8_t *intmap;
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uint32_t mask;
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int bit;
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#ifdef CONFIG_SMP
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int cpu;
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#endif
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#ifdef CONFIG_SMP
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/* Select PRO or APP CPU interrupt mapping table */
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cpu = up_cpu_index();
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if (cpu != 0)
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{
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intmap = g_cpu1_intmap;
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}
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else
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#endif
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{
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intmap = g_cpu0_intmap;
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}
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/* Skip over zero bits, eight at a time */
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for (bit = 0, mask = 0xff;
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bit < ESP32_NCPUINTS && (cpuints & mask) == 0;
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bit += 8, mask <<= 8);
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/* Process each pending CPU interrupt */
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for (; bit < ESP32_NCPUINTS && cpuints != 0; bit++)
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{
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mask = (1 << bit);
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if ((cpuints & mask) != 0)
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{
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/* Extract the IRQ number from the mapping table */
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uint8_t irq = intmap[bit];
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DEBUGASSERT(irq != CPUINT_UNASSIGNED);
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/* Clear software or edge-triggered interrupt */
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xtensa_intclear(mask);
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/* Dispatch the CPU interrupt.
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*
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* NOTE that regs may be altered in the case of an interrupt
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* level context switch.
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*/
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regs = xtensa_irq_dispatch((int)irq, regs);
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/* Clear the bit in the pending interrupt so that perhaps
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* we can exit the look early.
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*/
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cpuints &= ~mask;
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}
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}
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return regs;
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}
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@@ -53,27 +53,6 @@ extern "C"
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#define ESP32_CPUINT_LEVEL 0
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#define ESP32_CPUINT_LEVEL 0
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#define ESP32_CPUINT_EDGE 1
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#define ESP32_CPUINT_EDGE 1
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
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extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS];
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#ifdef CONFIG_SMP
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extern uint8_t g_cpu1_intmap[ESP32_NCPUINTS];
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#endif
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/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
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* content.
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*/
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#ifdef CONFIG_SMP
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extern uint32_t g_intenable[CONFIG_SMP_NCPUS];
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#else
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extern uint32_t g_intenable[1];
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#endif
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/****************************************************************************
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/****************************************************************************
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* Public Functions Prototypes
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* Public Functions Prototypes
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****************************************************************************/
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****************************************************************************/
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