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Merged in david_s5/nuttx/master_h7 (pull request #1037)
stm32h7:RCC Add PLL3 Support and only enable PLLs if used Approved-by: Gregory Nutt <gnutt@nuttx.org>
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committed by
Gregory Nutt
parent
08ffb3d285
commit
04b501eddf
@@ -70,6 +70,26 @@
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# error BOARD_FLASH_WAITSTATES is out of range
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#endif
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/* PLL are only enabled if the P,Q or R outputs are enabled. */
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#undef USE_PLL1
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#if STM32_PLLCFG_PLL1CFG & (RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | \
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RCC_PLLCFGR_DIVR1EN)
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# define USE_PLL1
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#endif
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#undef USE_PLL2
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#if STM32_PLLCFG_PLL2CFG & (RCC_PLLCFGR_DIVP2EN | RCC_PLLCFGR_DIVQ2EN | \
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RCC_PLLCFGR_DIVR2EN)
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# define USE_PLL2
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#endif
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#undef USE_PLL3
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#if STM32_PLLCFG_PLL3CFG & (RCC_PLLCFGR_DIVP3EN | RCC_PLLCFGR_DIVQ3EN | \
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RCC_PLLCFGR_DIVR3EN)
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# define USE_PLL3
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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@@ -686,32 +706,48 @@ static void stm32_stdclockconfig(void)
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STM32_PLLCFG_PLL3CFG);
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putreg32(regval, STM32_RCC_PLLCFGR);
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regval = getreg32(STM32_RCC_CR);
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#if defined(USE_PLL1)
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/* Enable the PLL1 */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLL1ON;
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putreg32(regval, STM32_RCC_CR);
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#endif
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#if defined(USE_PLL2)
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/* Enable the PLL2 */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLL2ON;
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#endif
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#if defined(USE_PLL3)
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/* Enable the PLL3 */
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regval |= RCC_CR_PLL3ON;
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#endif
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putreg32(regval, STM32_RCC_CR);
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/* TODO: Enable the PLL3 */
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#if defined(USE_PLL1)
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/* Wait until the PLL1 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0)
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{
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}
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#endif
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#if defined(USE_PLL2)
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/* Wait until the PLL2 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0)
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{
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}
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#endif
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#if defined(USE_PLL3)
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/* Wait until the PLL3 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0)
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{
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}
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#endif
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/* Configure FLASH wait states */
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regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
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