diff --git a/arch/arm/src/tms570/Kconfig b/arch/arm/src/tms570/Kconfig
index c1271601416..5425a91e118 100644
--- a/arch/arm/src/tms570/Kconfig
+++ b/arch/arm/src/tms570/Kconfig
@@ -84,4 +84,10 @@ config TMS570_SCI1
 
 endmenu # TMS570 Peripheral Support
 
+config TMS570_SELFTEST
+	bool "Power-on Selftest"
+	default n
+	---help---
+		Enable power-on self-test of memories and ECC logic.
+
 endif # ARCH_CHIP_TMS570
diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/chip/tms570_sys.h
index 855b9ea7da0..b1819aa1361 100644
--- a/arch/arm/src/tms570/chip/tms570_sys.h
+++ b/arch/arm/src/tms570/chip/tms570_sys.h
@@ -290,7 +290,17 @@
 /* System Exception Control Register */
 #define SYS_ECR_
 /* System Exception Status Register */
-#define SYS_ESR_
+
+#define SYS_ESR_MPMODE  (1 << 0)  /* Bit 0:  Current memory protection unit (MPU) mode */
+#define SYS_ESR_EXTRST  (1 << 3)  /* Bit 3:  External reset flag */
+#define SYS_ESR_SWRST   (1 << 4)  /* Bit 4:  Software reset flag */
+#define SYS_ESR_CPURST  (1 << 5)  /* Bit 5:  CPU reset flag */
+#define SYS_ESR_WDRST   (1 << 13) /* Bit 13: Watchdog reset flag */
+#define SYS_ESR_OSCRST  (1 << 14) /* Bit 14: Reset caused by an oscillator failure or PLL cycle slip */
+#define SYS_ESR_PORST   (1 << 15) /* Bit 15: Power-up reset */
+
+#define SYS_ESR_RSTALL  (0x0000e038)
+
 /* System Test Abort Status Register */
 #define SYS_TASR_
 /* Global Status Register */
diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c
index 173b34eea40..88f720ec01b 100644
--- a/arch/arm/src/tms570/tms570_boot.c
+++ b/arch/arm/src/tms570/tms570_boot.c
@@ -196,7 +196,6 @@ void arm_boot(void)
 
   tms570_event_export();
 
-#if 0 // REVISIT: Need SYS header file
   /* Read from the system exception status register to identify the cause of
    * the CPU reset.
    *
@@ -205,12 +204,11 @@ void arm_boot(void)
    * to do that.
    */
 
-  DEBUGASSERT((getreg(TMS570_SYS_SYSESR) & SYS_ESR_PORST) != 0);
+  DEBUGASSERT((getreg(TMS570_SYS_ESR) & SYS_ESR_PORST) != 0);
 
    /* Clear all reset status flags on successful power on reset */
 
-   putreg32(SYS_ESR_ALLRST, TMS570_SYS_SYSESR);
-#endif
+   putreg32(SYS_ESR_RSTALL, TMS570_SYS_ESR);
 
   /* Check if there were ESM group3 errors during power-up.
    *
@@ -230,7 +228,7 @@ void arm_boot(void)
 
   tms570_clockconfig();
 
-#ifdef CONFIG_TMS570_BIST
+#ifdef CONFIG_TMS570_SELFTEST
   /* Run a diagnostic check on the memory self-test controller. */
 #  warning Missing logic
 
@@ -239,7 +237,7 @@ void arm_boot(void)
 
   /* Disable PBIST clocks and disable memory self-test mode */
 #  warning Missing logic
-#endif /* CONFIG_TMS570_BIST */
+#endif /* CONFIG_TMS570_SELFTEST */
 
   /* Initialize CPU RAM. */
 
@@ -249,14 +247,14 @@ void arm_boot(void)
 
   tms570_enable_ramecc();
 
-#ifdef CONFIG_TMS570_BIST
+#ifdef CONFIG_TMS570_SELFTEST
   /* Perform PBIST on all dual-port memories */
 #warning Missing logic
 
   /* Test the CPU ECC mechanism for RAM accesses. */
 #warning Missing logic
 
-#endif /* CONFIG_TMS570_BIST */
+#endif /* CONFIG_TMS570_SELFTEST */
 
   /* Release the MibSPI1 modules from local reset. */
 #warning Missing logic