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libc:machine:risc-v:unifying elf relocation code.

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Signed-off-by: hotislandn <hotislandn@hotmail.com>
This commit is contained in:
hotislandn
2021-02-18 14:24:39 +08:00
committed by Xiang Xiao
parent 33005897ba
commit 0337cd05d7
5 changed files with 61 additions and 554 deletions
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libs/libc/machine/risc-v/Make.defs
+6
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@@ -18,6 +18,12 @@
# #
############################################################################ ############################################################################
ifeq ($(CONFIG_LIBC_ARCH_ELF),y)
CSRCS += arch_elf.c
DEPPATH += --dep-path machine/risc-v/common
VPATH += :machine/risc-v/common
endif
ifeq ($(CONFIG_ARCH_RV64GC),y) ifeq ($(CONFIG_ARCH_RV64GC),y)
include $(TOPDIR)/libs/libc/machine/risc-v/rv64/Make.defs include $(TOPDIR)/libs/libc/machine/risc-v/rv64/Make.defs
endif endif
libs/libc/machine/risc-v/rv32/arch_elf.c → libs/libc/machine/risc-v/common/arch_elf.c
+55 -32
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@@ -1,5 +1,5 @@
/**************************************************************************** /****************************************************************************
* libs/libc/machine/risc-v/rv32/arch_elf.c * libs/libc/machine/risc-v/common/arch_elf.c
* *
* Licensed to the Apache Software Foundation (ASF) under one or more * Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with * contributor license agreements. See the NOTICE file distributed with
@@ -42,6 +42,18 @@
#define RVI_OPCODE_MASK 0x7F #define RVI_OPCODE_MASK 0x7F
/* ELF32 and ELF64 definitions */
#ifdef CONFIG_LIBC_ARCH_ELF_64BIT
# define ARCH_ELF_TYP_STR "64"
# define ARCH_ELF_CLASS ELFCLASS64
# define ARCH_ELF_RELTYPE ELF64_R_TYPE
#else /* !CONFIG_LIBC_ARCH_ELF_64BIT */
# define ARCH_ELF_TYP_STR "32"
# define ARCH_ELF_CLASS ELFCLASS32
# define ARCH_ELF_RELTYPE ELF32_R_TYPE
#endif /* CONFIG_LIBC_ARCH_ELF_64BIT */
/**************************************************************************** /****************************************************************************
* Private Data Types * Private Data Types
****************************************************************************/ ****************************************************************************/
@@ -60,6 +72,7 @@ static struct rname_code_s _rname_table[] =
{ {
{"RELAX", R_RISCV_RELAX}, {"RELAX", R_RISCV_RELAX},
{"RISCV_32", R_RISCV_32}, {"RISCV_32", R_RISCV_32},
{"RISCV_64", R_RISCV_64},
{"PCREL_LO12_I", R_RISCV_PCREL_LO12_I}, {"PCREL_LO12_I", R_RISCV_PCREL_LO12_I},
{"PCREL_LO12_S", R_RISCV_PCREL_LO12_S}, {"PCREL_LO12_S", R_RISCV_PCREL_LO12_S},
{"PCREL_HI20", R_RISCV_PCREL_HI20}, {"PCREL_HI20", R_RISCV_PCREL_HI20},
@@ -198,11 +211,12 @@ bool up_checkarch(FAR const Elf_Ehdr *ehdr)
return false; return false;
} }
/* Make sure that 32-bit objects are supported */ /* Make sure that current objects are supported */
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32) if (ehdr->e_ident[EI_CLASS] != ARCH_ELF_CLASS)
{ {
berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", berr("ERROR: Need " ARCH_ELF_TYP_STR "-bit "
"objects: e_ident[EI_CLASS]=%02x\n",
ehdr->e_ident[EI_CLASS]); ehdr->e_ident[EI_CLASS]);
return false; return false;
} }
@@ -224,7 +238,7 @@ bool up_checkarch(FAR const Elf_Ehdr *ehdr)
if ((ehdr->e_entry & 1) != 0) if ((ehdr->e_entry & 1) != 0)
{ {
berr("ERROR: Entry point is not properly aligned: %08" PRIx32 "\n", berr("ERROR: Entry point is not properly aligned: %08lx\n",
ehdr->e_entry); ehdr->e_entry);
} }
@@ -270,7 +284,7 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
/* All relocations depend upon having valid symbol information */ /* All relocations depend upon having valid symbol information */
relotype = ELF32_R_TYPE(rel->r_info); relotype = ARCH_ELF_RELTYPE(rel->r_info);
if (relotype == R_RISCV_RELAX) if (relotype == R_RISCV_RELAX)
{ {
@@ -293,9 +307,10 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
switch (relotype) switch (relotype)
{ {
case R_RISCV_32: case R_RISCV_32:
case R_RISCV_64:
{ {
binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] " binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08" PRIx32 "\n", "to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, sym->st_value); sym, sym->st_value);
@@ -309,7 +324,7 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_PCREL_LO12_S: case R_RISCV_PCREL_LO12_S:
{ {
binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] " binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08" PRIx32 "\n", "to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, sym->st_value); sym, sym->st_value);
@@ -323,7 +338,7 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_CALL_PLT: case R_RISCV_CALL_PLT:
{ {
binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] " binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08" PRIx32 "\n", "to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, sym->st_value); sym, sym->st_value);
@@ -347,7 +362,8 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
(((int32_t)imm_lo >> 5) << 25) + (((int32_t)imm_lo >> 5) << 25) +
(((int32_t)imm_lo & 0x1f) << 7); (((int32_t)imm_lo & 0x1f) << 7);
binfo("imm_lo=%ld (%lx), val=%lx \n", imm_lo, imm_lo, val); binfo("imm_lo=%ld (%lx), val=%" PRIx32 "\n",
imm_lo, imm_lo, val);
_add_val((uint16_t *)(addr + 4), val); _add_val((uint16_t *)(addr + 4), val);
} }
@@ -362,10 +378,11 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_BRANCH: case R_RISCV_BRANCH:
{ {
binfo("%s at %08lx [%08lx] to sym=%p st_value=%08lx\n", binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
(long)addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, (long)sym->st_value); sym, sym->st_value);
/* P.23 Conditinal Branches : B type (imm=12bit) */ /* P.23 Conditinal Branches : B type (imm=12bit) */
@@ -376,17 +393,19 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
ASSERT(offset && val); ASSERT(offset && val);
binfo("offset for Bx=%ld (0x%lx) (val=0x%08lx) already set! \n", binfo("offset for Bx=%ld (0x%lx) (val=0x%08" PRIx32 ") "
"already set! \n",
offset, offset, val); offset, offset, val);
} }
break; break;
case R_RISCV_HI20: case R_RISCV_HI20:
{ {
binfo("%s at %08lx [%08lx] to sym=%p st_value=%08lx\n", binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
(long)addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, (long)sym->st_value); sym, sym->st_value);
/* P.19 LUI */ /* P.19 LUI */
@@ -406,10 +425,11 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_LO12_I: case R_RISCV_LO12_I:
{ {
binfo("%s at %08lx [%08lx] to sym=%p st_value=%08lx\n", binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
(long)addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, (long)sym->st_value); sym, sym->st_value);
/* ADDI, FLW, LD, ... : I-type */ /* ADDI, FLW, LD, ... : I-type */
@@ -427,10 +447,11 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_LO12_S: case R_RISCV_LO12_S:
{ {
binfo("%s at %08lx [%08lx] to sym=%p st_value=%08lx\n", binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
(long)addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, (long)sym->st_value); sym, sym->st_value);
/* SW : S-type. /* SW : S-type.
* not merge with R_RISCV_HI20 since the compiler * not merge with R_RISCV_HI20 since the compiler
@@ -447,7 +468,7 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
(((int32_t)imm_lo >> 5) << 25) + (((int32_t)imm_lo >> 5) << 25) +
(((int32_t)imm_lo & 0x1f) << 7); (((int32_t)imm_lo & 0x1f) << 7);
binfo("imm_lo=%ld (%lx), val=%lx \n", imm_lo, imm_lo, val); binfo("imm_lo=%ld (%lx), val=%" PRIx32 "\n", imm_lo, imm_lo, val);
_add_val((uint16_t *)addr, val); _add_val((uint16_t *)addr, val);
} }
@@ -455,10 +476,11 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_RVC_JUMP: case R_RISCV_RVC_JUMP:
{ {
binfo("%s at %08lx [%04lx] to sym=%p st_value=%08lx\n", binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
(long)addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, (long)sym->st_value); sym, sym->st_value);
/* P.111 Table 16.6 : Instruction listings for RVC */ /* P.111 Table 16.6 : Instruction listings for RVC */
@@ -478,10 +500,11 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
case R_RISCV_RVC_BRANCH: case R_RISCV_RVC_BRANCH:
{ {
binfo("%s at %08lx [%04lx] to sym=%p st_value=%08lx\n", binfo("%s at %08" PRIxPTR " [%08" PRIx32 "] "
"to sym=%p st_value=%08lx\n",
_get_rname(relotype), _get_rname(relotype),
(long)addr, _get_val((uint16_t *)addr), addr, _get_val((uint16_t *)addr),
sym, (long)sym->st_value); sym, sym->st_value);
/* P.111 Table 16.6 : Instruction listings for RVC */ /* P.111 Table 16.6 : Instruction listings for RVC */
@@ -500,8 +523,8 @@ int up_relocateadd(FAR const Elf_Rela *rel, FAR const Elf_Sym *sym,
break; break;
default: default:
berr("ERROR: Unsupported relocation: %" PRId32 "\n", berr("ERROR: Unsupported relocation: %ld\n",
ELF32_R_TYPE(rel->r_info)); ARCH_ELF_RELTYPE(rel->r_info));
ASSERT(false); ASSERT(false);
return -EINVAL; return -EINVAL;
} }
libs/libc/machine/risc-v/rv32/Make.defs
-4
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@@ -22,10 +22,6 @@ ifeq ($(CONFIG_RISCV_MEMCPY),y)
ASRCS += arch_memcpy.S ASRCS += arch_memcpy.S
endif endif
ifeq ($(CONFIG_LIBC_ARCH_ELF),y)
CSRCS += arch_elf.c
endif
DEPPATH += --dep-path machine/risc-v/rv32 DEPPATH += --dep-path machine/risc-v/rv32
VPATH += :machine/risc-v/rv32 VPATH += :machine/risc-v/rv32
libs/libc/machine/risc-v/rv64/Make.defs
-8
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@@ -18,11 +18,3 @@
# #
############################################################################ ############################################################################
ifeq ($(CONFIG_LIBC_ARCH_ELF),y)
CSRCS += arch_elf.c
DEPPATH += --dep-path machine/risc-v/rv64
VPATH += :machine/risc-v/rv64
endif
libs/libc/machine/risc-v/rv64/arch_elf.c
-510
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