#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#

if ARCH_CHIP_STM32L4

comment "STM32L4 Configuration Options"

choice
	prompt "STM32 L4 Chip Selection"
	default ARCH_CHIP_STM32L476RG
	depends on ARCH_CHIP_STM32L4

config ARCH_CHIP_STM32L476RG
	bool "STM32L476RG"
	select STM32L4_STM32L476XX
	select STM32L4_FLASH_1024KB
	---help---
		STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM

config ARCH_CHIP_STM32L476RE
	bool "STM32L476RE"
	select STM32L4_STM32L476XX
	select STM32L4_FLASH_512KB
	---help---
		STM32 L4 Cortex M4, 512 FLASH, 96+32 Kb SRAM

config ARCH_CHIP_STM32L486
	bool "STM32L486xx"
	select STM32L4_STM32L486XX
	select STM32L4_HAVE_AES
	---help---
		STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM

endchoice # STM32 L4 Chip Selection

# Chip families

config STM32L4_STM32L476XX
	bool
	default n
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU # REVISIT
	select ARMV7M_HAVE_ITCM
	select ARMV7M_HAVE_DTCM

config STM32L4_STM32L486XX
	bool
	default n
	select ARCH_HAVE_FPU
	select ARCH_HAVE_DPFPU # REVISIT
	select ARMV7M_HAVE_ITCM
	select ARMV7M_HAVE_DTCM
	select STM32L4_FLASH_1024KB

choice
	prompt "Embedded FLASH size"
	default STM32L4_FLASH_1024KB

config STM32L4_FLASH_256KB
	bool "256 KB"

config STM32L4_FLASH_512KB
	bool "512 KB"

config STM32L4_FLASH_1024KB
	bool "1024 KB"

endchoice # Embedded FLASH size

comment "SRAM2 Options"

config STM32L4_SRAM2_HEAP
	bool "SRAM2 is used for heap"
	default n
	select STM32L4_SRAM2_INIT
	---help---
		The STM32L4 SRAM2 region has special properties (power, protection, parity)
		which may be used by the application for special purposes.  But if these
		special properties are not needed, it may be instead added to the heap for
		use by malloc().
		NOTE: you must also select an appropriate number of memory regions in the
		'Memory Management' section.

config STM32L4_SRAM2_INIT
	bool "SRAM2 is initialized to zero"
	default n
	---help---
		The STM32L4 SRAM2 region has parity checking.  However, when the system
		powers on, the memory is in an unknown state, and reads from uninitialized
		memory can trigger parity faults from the random data.  This can be
		avoided by first writing to all locations to force the parity into a valid
		state.
		However, if the SRAM2 is being used for it's battery-backed capability,
		this may be undesireable (because it will destroy the contents).  In that
		case, the board should handle the initialization itself at the appropriate
		time.

menu "STM32L4 Peripheral Support"

# These "hidden" settings determine is a peripheral option is available for the
# selection MCU

config STM32L4_HAVE_LTDC
	bool
	default n

# These "hidden" settings are the OR of individual peripheral selections
# indicating that the general capability is required.

config STM32L4_ADC
	bool
	default n

config STM32L4_CAN
	bool
	default n

config STM32L4_DAC
	bool
	default n

config STM32L4_DMA
	bool
	default n

config STM32L4_I2C
	bool
	default n

config STM32L4_SAI
	bool
	default n

config STM32L4_SPI
	bool
	default n

config STM32L4_USART
	bool
	default n

config STM32L4_LPTIM
    bool
    default n

# These are the peripheral selections proper

comment "AHB1 Peripherals"

config STM32L4_DMA1
	bool "DMA1"
	default n
	select STM32L4_DMA
	select ARCH_DMA

config STM32L4_DMA2
	bool "DMA2"
	default n
	select STM32L4_DMA
	select ARCH_DMA

config STM32L4_CRC
	bool "CRC"
	default n

config STM32L4_TSC
	bool "TSC"
	default n

comment "AHB2 Peripherals"

config STM32L4_OTGFS
	bool "OTG FS"
	default n
	select USBHOST_HAVE_ASYNCH if USBHOST

config STM32L4_ADC1
	bool "ADC1"
	default n
	select STM32L4_ADC

config STM32L4_ADC2
	bool "ADC2"
	default n
	select STM32L4_ADC

config STM32L4_ADC3
	bool "ADC3"
	default n
	select STM32L4_ADC

config STM32L4_AES
	bool "AES"
	default n

config STM32L4_RNG
	bool "RNG"
	default n
	select ARCH_HAVE_RNG

comment "AHB3 Peripherals"

config STM32L4_FMC
	bool "FMC"
	default n

config STM32L4_QSPI
	bool "QuadSPI"
	default n
	---help---
		The STM32L4 QSPI block is intended to support one serial NOR flash device

if STM32L4_QSPI

config STM32L4_QSPI_FLASH_SIZE
	int "Size of attached serial flash, bytes"
	default 16777216
	range 1 2147483648
	---help---
		The STM32L4 QSPI peripheral requires the size of the Flash be specified

config STM32L4_QSPI_FIFO_THESHOLD
	int "Number of bytes before asserting FIFO threshold flag"
	default 4
	range 1 16
	---help---
		The STM32L4 QSPI peripheral requires that the FIFO threshold be specified
		I would leave it at the default value of 4 unless you know what you are doing.

config STM32L4_QSPI_CSHT
	int "Number of cycles Chip Select must be inactive between transactions"
	default 1
	range 1 8
	---help---
		The STM32L4 QSPI peripheral requires that it be specified the minimum number
		of AHB cycles that Chip Select be held inactive between transactions.

choice
	prompt "Transfer technique"
	default STM32L4_QSPI_DMA
	---help---
		You can choose between using polling, interrupts, or DMA to transfer data
		over the QSPI interface.

config STM32L4_QSPI_POLLING
	bool "Polling"
	---help---
		Use conventional register I/O with status polling to transfer data.

config STM32L4_QSPI_INTERRUPTS
	bool "Interrupts"
	---help---
		User interrupt driven I/O transfers.

config STM32L4_QSPI_DMA
	bool "DMA"
	depends on STM32L4_DMA
	---help---
		Use DMA to improve QSPI transfer performance.

endchoice

choice
	prompt "DMA Channel"
	default STM32L4_QSPI_DMA_CHAN_1_5
	depends on STM32L4_DMA
	---help---
		You can choose between two DMA channels for use with QSPI:
		either DMA1 channel 5, or DMA2 channel 7.
		If you only see one choice here, it is probably because
		you have not also enabled the associated DMA controller.

config STM32L4_QSPI_DMA_CHAN_1_5
	bool "DMA1 Channel 5"
	depends on STM32L4_DMA1
	---help---
		Use DMA1 channel 5 for QSPI.

config STM32L4_QSPI_DMA_CHAN_2_7
	bool "DMA2 Channel 7"
	depends on STM32L4_DMA2
	---help---
		Use DMA2 channel 7 for QSPI.

endchoice

choice
	prompt "DMA Priority"
	default STM32L4_QSPI_DMAPRIORITY_MEDIUM
	depends on STM32L4_DMA
	---help---
		The DMA controller supports priority levels.  You are probably fine
		with the default of 'medium' except for special cases.  In the event
		of contention between to channels at the same priority, the lower
		numbered channel has hardware priority over the higher numbered one.

config STM32L4_QSPI_DMAPRIORITY_VERYHIGH
	bool "Very High priority"
	depends on STM32L4_DMA
	---help---
		'Highest' priority.

config STM32L4_QSPI_DMAPRIORITY_HIGH
	bool "High priority"
	depends on STM32L4_DMA
	---help---
		'High' priority.

config STM32L4_QSPI_DMAPRIORITY_MEDIUM
	bool "Medium priority"
	depends on STM32L4_DMA
	---help---
		'Medium' priority.

config STM32L4_QSPI_DMAPRIORITY_LOW
	bool "Low priority"
	depends on STM32L4_DMA
	---help---
		'Low' priority.

endchoice

config STM32L4_QSPI_DMATHRESHOLD
	int "QSPI DMA threshold"
	default 4
	depends on STM32L4_QSPI_DMA
	---help---
		When QSPI DMA is enabled, small DMA transfers will still be performed
		by polling logic.  This value is the threshold below which transfers
		will still be performed by conventional register status polling.

config STM32L4_QSPI_DMADEBUG
	bool "QSPI DMA transfer debug"
	depends on STM32L4_QSPI_DMA && DEBUG && DEBUG_DMA
	default n
	---help---
		Enable special debug instrumentation to analyze QSPI DMA data transfers.
		This logic is as non-invasive as possible:  It samples DMA
		registers at key points in the data transfer and then dumps all of
		the registers at the end of the transfer.

config STM32L4_QSPI_REGDEBUG
	bool "QSPI Register level debug"
	depends on DEBUG
	default n
	---help---
		Output detailed register-level QSPI device debug information.
		Requires also DEBUG.

endif

comment "APB1 Peripherals"

config STM32L4_PWR
	bool "PWR"
	default n

config STM32L4_TIM2
	bool "TIM2"
	default n

config STM32L4_TIM3
	bool "TIM3"
	default n

config STM32L4_TIM4
	bool "TIM4"
	default n

config STM32L4_TIM5
	bool "TIM5"
	default n

config STM32L4_TIM6
	bool "TIM6"
	default n

config STM32L4_TIM7
	bool "TIM7"
	default n

config STM32L4_LCD
    bool "LCD"
    default n

config STM32L4_SPI2
	bool "SPI2"
	default n
	select SPI
	select STM32L4_SPI

config STM32L4_SPI3
	bool "SPI3"
	default n
	select SPI
	select STM32L4_SPI

config STM32L4_USART1
	bool "USART1"
	default n
	select ARCH_HAVE_USART1
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32L4_USART

config STM32L4_USART2
	bool "USART2"
	default n
	select ARCH_HAVE_USART2
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32L4_USART

config STM32L4_USART3
	bool "USART3"
	default n
	select ARCH_HAVE_SERIAL_TERMIOS
	select ARCH_HAVE_USART3
	select STM32L4_USART

config STM32L4_UART4
	bool "UART4"
	default n
	select ARCH_HAVE_SERIAL_TERMIOS
	select ARCH_HAVE_UART4
	select STM32L4_USART

config STM32L4_UART5
	bool "UART5"
	default n
	select ARCH_HAVE_SERIAL_TERMIOS
	select ARCH_HAVE_UART5
	select STM32L4_USART

config STM32L4_I2C1
	bool "I2C1"
	default n
	select STM32L4_I2C

config STM32L4_I2C2
	bool "I2C2"
	default n
	select STM32L4_I2C

config STM32L4_I2C3
	bool "I2C3"
	default n
	select STM32L4_I2C

config STM32L4_CAN1
	bool "CAN1"
	default n
	select CAN
	select STM32L4_CAN

config STM32L4_DAC1
	bool "DAC1"
	default n
	select STM32L4_DAC

config STM32L4_DAC2
	bool "DAC2"
	default n
	select STM32L4_DAC

config STM32L4_OPAMP
    bool "OPAMP"
    default n

config STM32L4_LPTIM1
	bool "LPTIM1"
	default n
    select STM32L4_LPTIM

config STM32L4_LPUART1
	bool "LPUART1"
	default n
	select ARCH_HAVE_SERIAL_TERMIOS
	select ARCH_HAVE_LPUART1

config STM32L4_SWPMI
    bool "SWPMI"
    default n

config STM32L4_LPTIM2
	bool "LPTIM2"
	default n
    select STM32L4_LPTIM

comment "APB2 Peripherals"

config STM32L4_SYSCFG
	bool "SYSCFG"
	default y

config STM32L4_FIREWALL
	bool "FIREWALL"
	default y
	depends on STM32L4_SYSCFG

config STM32L4_SDMMC1
	bool "SDMMC1"
	default n
	select ARCH_HAVE_SDIO

config STM32L4_TIM1
	bool "TIM1"
	default n

config STM32L4_SPI1
	bool "SPI1"
	default n
	select SPI
	select STM32L4_SPI

config STM32L4_TIM8
	bool "TIM8"
	default n

config STM32L4_USART1
	bool "USART1"
	default n
	select ARCH_HAVE_USART1
	select ARCH_HAVE_SERIAL_TERMIOS
	select STM32L4_USART

config STM32L4_TIM15
	bool "TIM15"
	default n

config STM32L4_TIM16
	bool "TIM16"
	default n

config STM32L4_TIM17
	bool "TIM17"
	default n

config STM32L4_SAI1
	bool "SAI1"
	default n
	select STM32L4_SAI

config STM32L4_SAI2
	bool "SAI2"
	default n
	select STM32L4_SAI

config STM32L4_DFSDM
    bool "DFSDM"
    default n

comment "Other Peripherals"

config STM32L4_BKPSRAM
	bool "Enable BKP RAM Domain"
	default n

config STM32L4_IWDG
	bool "IWDG"
	default n
	select WATCHDOG

config STM32L4_WWDG
	bool "WWDG"
	default n
	select WATCHDOG

endmenu

config STM32L4_FLASH_PREFETCH
	bool "Enable FLASH Pre-fetch"
	default y
	---help---
	Enable FLASH prefetch

config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG
	bool "Disable IDLE Sleep (WFI) in debug mode"
	default n
	---help---
		In debug configuration, disables the WFI instruction in the IDLE loop
		to prevent the JTAG from disconnecting.  With some JTAG debuggers, such
		as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI
		instruction, the debugger will disconnect, terminating the debug session.

config ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG
	bool "Custom clock configuration"
	default n
	---help---
		Enables special, board-specific STM32 clock configuration.

choice
	prompt "RTC clock source"
	default STM32L4_RTC_LSECLOCK
	depends on RTC

config STM32L4_RTC_LSECLOCK
	bool "LSE clock"
	---help---
		Drive the RTC with the LSE clock

config STM32L4_RTC_LSICLOCK
	bool "LSI clock"
	---help---
		Drive the RTC with the LSI clock

config STM32L4_RTC_HSECLOCK
	bool "HSE clock"
	---help---
		Drive the RTC with the HSE clock, divided down to 1MHz.

endchoice

config STM32L4_SAI1PLL
	bool "SAI1PLL"
	default n
	---help---
		The STM32L476 has a separate PLL for the SAI1 block.
		Set this true and provide configuration parameters in
		board.h to use this PLL.

config STM32L4_SAI2PLL
	bool "SAI2PLL"
	default n
	---help---
		The STM32L476 has a separate PLL for the SAI2 block.
		Set this true and provide configuration parameters in
		board.h to use this PLL.

config STM32L4_USART
	bool

menu "U[S]ART Configuration"
	depends on STM32L4_USART

config USART1_RS485
	bool "RS-485 on USART1"
	default n
	depends on STM32L4_USART1
	---help---
		Enable RS-485 interface on USART1. Your board config will have to
		provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
		used with USART1_RXDMA.

config USART1_RS485_DIR_POLARITY
	int "USART1 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART1_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART1_RXDMA
	bool "USART1 Rx DMA"
	default n
	depends on STM32L4_USART1 && ( STM32L4_DMA1 || STM32L4_DMA2 )
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

config USART2_RS485
	bool "RS-485 on USART2"
	default n
	depends on STM32L4_USART2
	---help---
		Enable RS-485 interface on USART2. Your board config will have to
		provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be
		used with USART2_RXDMA.

config USART2_RS485_DIR_POLARITY
	int "USART2 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART2_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART2_RXDMA
	bool "USART2 Rx DMA"
	default n
	depends on STM32L4_USART2 && STM32L4_DMA1
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

config USART3_RS485
	bool "RS-485 on USART3"
	default n
	depends on STM32L4_USART3
	---help---
		Enable RS-485 interface on USART3. Your board config will have to
		provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be
		used with USART3_RXDMA.

config USART3_RS485_DIR_POLARITY
	int "USART3 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on USART3_RS485
	---help---
		Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config USART3_RXDMA
	bool "USART3 Rx DMA"
	default n
	depends on STM32L4_USART3 && STM32L4_DMA1
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

config UART4_RS485
	bool "RS-485 on UART4"
	default n
	depends on STM32L4_UART4
	---help---
		Enable RS-485 interface on UART4. Your board config will have to
		provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be
		used with UART4_RXDMA.

config UART4_RS485_DIR_POLARITY
	int "UART4 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART4_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART4_RXDMA
	bool "UART4 Rx DMA"
	default n
	depends on STM32L4_UART4 && STM32L4_DMA2
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

config UART5_RS485
	bool "RS-485 on UART5"
	default n
	depends on STM32L4_UART5
	---help---
		Enable RS-485 interface on UART5. Your board config will have to
		provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be
		used with UART5_RXDMA.

config UART5_RS485_DIR_POLARITY
	int "UART5 RS-485 DIR pin polarity"
	default 1
	range 0 1
	depends on UART5_RS485
	---help---
		Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which
		enables TX (0 - low / nTXEN, 1 - high / TXEN).

config UART5_RXDMA
	bool "UART5 Rx DMA"
	default n
	depends on STM32L4_UART5 && STM32L4_DMA2
	---help---
		In high data rate usage, Rx DMA may eliminate Rx overrun errors

config SERIAL_DISABLE_REORDERING
	bool "Disable reordering of ttySx devices."
	depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5
	default n
	---help---
		NuttX per default reorders the serial ports (/dev/ttySx) so that the
		console is always on /dev/ttyS0. If more than one UART is in use this
		can, however, have the side-effect that all port mappings
		(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
		UART. This is in particular relevant if a project uses the USB console
		in some configs and a serial console in other configs, but does not
		want the side effect of having all serial port names change when just
		the console is moved from serial to USB.

config STM32L4_FLOWCONTROL_BROKEN
	bool "Use Software UART RTS flow control"
	depends on STM32L4_USART
	default n
	---help---
		Enable UART RTS flow control using Software. Because STM
		Current STM32 have broken HW based RTS behavior (they assert
		nRTS after every byte received)  Enable this setting workaround
		this issue by useing software based management of RTS

config STM32L4_USART_BREAKS
	bool "Add TIOxSBRK to support sending Breaks"
	depends on STM32_USART
	default n
	---help---
		Add TIOCxBRK routines to send a line break per the STM32 manual, the
		break will be a pulse based on the value M. This is not a BSD compatible
		break.

config STM32L4_SERIALBRK_BSDCOMPAT
	bool "Use GPIO To send Break"
	depends on STM32_USART && STM32_USART_BREAKS
	default n
	---help---
		Enable using GPIO on the TX pin to send a BSD compatible break:
		TIOCSBRK will start the break and TIOCCBRK will end the break.
		The current STM32 U[S]ARTS have no way to leave the break (TX=LOW)
		on because the SW starts the break and then the HW automatically clears
		the break. This makes it is difficult to sent a long break.

endmenu # U[S]ART Configuration

menu "SPI Configuration"
	depends on STM32L4_SPI

config STM32L4_SPI_INTERRUPTS
	bool "Interrupt driver SPI"
	default n
	---help---
		Select to enable interrupt driven SPI support. Non-interrupt-driven,
		poll-waiting is recommended if the interrupt rate would be to high in
		the interrupt driven case.

config STM32L4_SPI_DMA
	bool "SPI DMA"
	default n
	---help---
		Use DMA to improve SPI transfer performance.  Cannot be used with STM32L4_SPI_INTERRUPT.

endmenu

menu "I2C Configuration"
	depends on STM32L4_I2C

config STM32L4_I2C_DYNTIMEO
	bool "Use dynamic timeouts"
	default n
	depends on STM32L4_I2C

config STM32L4_I2C_DYNTIMEO_USECPERBYTE
	int "Timeout Microseconds per Byte"
	default 500
	depends on STM32L4_I2C_DYNTIMEO

config STM32L4_I2C_DYNTIMEO_STARTSTOP
	int "Timeout for Start/Stop (Milliseconds)"
	default 1000
	depends on STM32L4_I2C_DYNTIMEO

config STM32L4_I2CTIMEOSEC
	int "Timeout seconds"
	default 0
	depends on STM32L4_I2C

config STM32L4_I2CTIMEOMS
	int "Timeout Milliseconds"
	default 500
	depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO

config STM32L4_I2CTIMEOTICKS
	int "Timeout for Done and Stop (ticks)"
	default 500
	depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO

config STM32L4_I2C_DUTY16_9
	bool "Frequency with Tlow/Thigh = 16/9 "
	default n
	depends on STM32L4_I2C

endmenu

menu "CAN driver configuration"
	depends on STM32L4_CAN1

config CAN1_BAUD
	int "CAN1 BAUD"
	default 250000
	depends on STM32L4_CAN1
	---help---
		CAN1 BAUD rate.  Required if STM32L4_CAN1 is defined.

config CAN_TSEG1
	int "TSEG1 quanta"
	default 6
	---help---
		The number of CAN time quanta in segment 1. Default: 6

config CAN_TSEG2
	int "TSEG2 quanta"
	default 7
	---help---
		The number of CAN time quanta in segment 2. Default: 7
endmenu

endif # ARCH_CHIP_STM32L4
