diff --git a/Ghidra/Processors/x86/data/languages/avx512.sinc b/Ghidra/Processors/x86/data/languages/avx512.sinc index a882bd1061..2c88dc743f 100644 --- a/Ghidra/Processors/x86/data/languages/avx512.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512.sinc @@ -4,7 +4,7 @@ # ADDPD 3-33 PAGE 603 LINE 33411 define pcodeop vaddpd_avx512vl ; -:VADDPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VADDPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vaddpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -15,7 +15,7 @@ define pcodeop vaddpd_avx512vl ; } # ADDPD 3-33 PAGE 603 LINE 33414 -:VADDPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VADDPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vaddpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -27,7 +27,7 @@ define pcodeop vaddpd_avx512vl ; # ADDPD 3-33 PAGE 603 LINE 33417 define pcodeop vaddpd_avx512f ; -:VADDPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VADDPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vaddpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -39,7 +39,7 @@ define pcodeop vaddpd_avx512f ; # ADDPS 3-36 PAGE 606 LINE 33562 define pcodeop vaddps_avx512vl ; -:VADDPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VADDPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vaddps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -50,7 +50,7 @@ define pcodeop vaddps_avx512vl ; } # ADDPS 3-36 PAGE 606 LINE 33565 -:VADDPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VADDPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vaddps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst); @@ -62,7 +62,7 @@ define pcodeop vaddps_avx512vl ; # ADDPS 3-36 PAGE 606 LINE 33568 define pcodeop vaddps_avx512f ; -:VADDPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VADDPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vaddps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -74,7 +74,7 @@ define pcodeop vaddps_avx512f ; # ADDSD 3-39 PAGE 609 LINE 33721 define pcodeop vaddsd_avx512f ; -:VADDSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VADDSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vaddsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -86,7 +86,7 @@ define pcodeop vaddsd_avx512f ; # ADDSS 3-41 PAGE 611 LINE 33815 define pcodeop vaddss_avx512f ; -:VADDSS XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32 +:VADDSS XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vaddss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -98,7 +98,7 @@ define pcodeop vaddss_avx512f ; # ANDPD 3-64 PAGE 634 LINE 34827 define pcodeop vandpd_avx512vl ; -:VANDPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VANDPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vandpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -109,7 +109,7 @@ define pcodeop vandpd_avx512vl ; } # ANDPD 3-64 PAGE 634 LINE 34830 -:VANDPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VANDPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vandpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -121,7 +121,7 @@ define pcodeop vandpd_avx512vl ; # ANDPD 3-64 PAGE 634 LINE 34833 define pcodeop vandpd_avx512dq ; -:VANDPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VANDPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vandpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -133,7 +133,7 @@ define pcodeop vandpd_avx512dq ; # ANDPS 3-67 PAGE 637 LINE 34953 define pcodeop vandps_avx512vl ; -:VANDPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VANDPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vandps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -144,7 +144,7 @@ define pcodeop vandps_avx512vl ; } # ANDPS 3-67 PAGE 637 LINE 34956 -:VANDPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VANDPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vandps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -155,7 +155,7 @@ define pcodeop vandps_avx512vl ; # ANDPS 3-67 PAGE 637 LINE 34959 define pcodeop vandps_avx512dq ; -:VANDPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VANDPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vandps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -166,7 +166,7 @@ define pcodeop vandps_avx512dq ; # ANDNPD 3-70 PAGE 640 LINE 35087 define pcodeop vandnpd_avx512vl ; -:VANDNPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VANDNPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vandnpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -176,7 +176,7 @@ define pcodeop vandnpd_avx512vl ; } # ANDNPD 3-70 PAGE 640 LINE 35090 -:VANDNPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VANDNPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vandnpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -187,7 +187,7 @@ define pcodeop vandnpd_avx512vl ; # ANDNPD 3-70 PAGE 640 LINE 35093 define pcodeop vandnpd_avx512dq ; -:VANDNPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VANDNPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vandnpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -198,7 +198,7 @@ define pcodeop vandnpd_avx512dq ; # ANDNPS 3-73 PAGE 643 LINE 35213 define pcodeop vandnps_avx512vl ; -:VANDNPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VANDNPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vandnps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -208,7 +208,7 @@ define pcodeop vandnps_avx512vl ; } # ANDNPS 3-73 PAGE 643 LINE 35216 -:VANDNPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VANDNPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vandnps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -219,7 +219,7 @@ define pcodeop vandnps_avx512vl ; # ANDNPS 3-73 PAGE 643 LINE 35219 define pcodeop vandnps_avx512dq ; -:VANDNPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VANDNPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x55; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vandnps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -318,7 +318,7 @@ define pcodeop vcomiss_avx512f ; # CVTDQ2PD 3-228 PAGE 798 LINE 43080 define pcodeop vcvtdq2pd_avx512vl ; -:VCVTDQ2PD XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTDQ2PD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -328,7 +328,7 @@ define pcodeop vcvtdq2pd_avx512vl ; } # CVTDQ2PD 3-228 PAGE 798 LINE 43083 -:VCVTDQ2PD YmmReg1 YmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTDQ2PD YmmReg1^YmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -339,7 +339,7 @@ define pcodeop vcvtdq2pd_avx512vl ; # CVTDQ2PD 3-228 PAGE 798 LINE 43086 define pcodeop vcvtdq2pd_avx512f ; -:VCVTDQ2PD ZmmReg1 ZmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTDQ2PD ZmmReg1^ZmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0xE6; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvtdq2pd_avx512f( YmmReg2_m256_m32bcst ); @@ -350,7 +350,7 @@ define pcodeop vcvtdq2pd_avx512f ; # CVTDQ2PS 3-232 PAGE 802 LINE 43248 define pcodeop vcvtdq2ps_avx512vl ; -:VCVTDQ2PS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTDQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtdq2ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -360,7 +360,7 @@ define pcodeop vcvtdq2ps_avx512vl ; } # CVTDQ2PS 3-232 PAGE 802 LINE 43251 -:VCVTDQ2PS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTDQ2PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtdq2ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -371,7 +371,7 @@ define pcodeop vcvtdq2ps_avx512vl ; # CVTDQ2PS 3-232 PAGE 802 LINE 43254 define pcodeop vcvtdq2ps_avx512f ; -:VCVTDQ2PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VCVTDQ2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtdq2ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -382,7 +382,7 @@ define pcodeop vcvtdq2ps_avx512f ; # CVTPD2DQ 3-235 PAGE 805 LINE 43414 define pcodeop vcvtpd2dq_avx512vl ; -:VCVTPD2DQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTPD2DQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2dq_avx512vl( XmmReg2_m128_m64bcst ); @@ -392,7 +392,7 @@ define pcodeop vcvtpd2dq_avx512vl ; } # CVTPD2DQ 3-235 PAGE 805 LINE 43417 -:VCVTPD2DQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTPD2DQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtpd2dq_avx512vl( YmmReg2_m256_m64bcst ); @@ -403,7 +403,7 @@ define pcodeop vcvtpd2dq_avx512vl ; # CVTPD2DQ 3-235 PAGE 805 LINE 43420 define pcodeop vcvtpd2dq_avx512f ; -:VCVTPD2DQ YmmReg1 YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTPD2DQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtpd2dq_avx512f( ZmmReg2_m512_m64bcst ); @@ -414,7 +414,7 @@ define pcodeop vcvtpd2dq_avx512f ; # CVTPD2PS 3-240 PAGE 810 LINE 43649 define pcodeop vcvtpd2ps_avx512vl ; -:VCVTPD2PS XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTPD2PS XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2ps_avx512vl( XmmReg2_m128_m64bcst ); @@ -424,7 +424,7 @@ define pcodeop vcvtpd2ps_avx512vl ; } # CVTPD2PS 3-240 PAGE 810 LINE 43653 -:VCVTPD2PS XmmReg1 XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTPD2PS XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2ps_avx512vl( YmmReg2_m256_m64bcst ); @@ -435,7 +435,7 @@ define pcodeop vcvtpd2ps_avx512vl ; # CVTPD2PS 3-240 PAGE 810 LINE 43657 define pcodeop vcvtpd2ps_avx512f ; -:VCVTPD2PS YmmReg1 YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTPD2PS YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtpd2ps_avx512f( ZmmReg2_m512_m64bcst ); @@ -446,7 +446,7 @@ define pcodeop vcvtpd2ps_avx512f ; # CVTPS2DQ 3-246 PAGE 816 LINE 43933 define pcodeop vcvtps2dq_avx512vl ; -:VCVTPS2DQ XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTPS2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtps2dq_avx512vl( XmmReg2_m128_m32bcst ); @@ -456,7 +456,7 @@ define pcodeop vcvtps2dq_avx512vl ; } # CVTPS2DQ 3-246 PAGE 816 LINE 43936 -:VCVTPS2DQ YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTPS2DQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtps2dq_avx512vl( YmmReg2_m256_m32bcst ); @@ -467,7 +467,7 @@ define pcodeop vcvtps2dq_avx512vl ; # CVTPS2DQ 3-246 PAGE 816 LINE 43939 define pcodeop vcvtps2dq_avx512f ; -:VCVTPS2DQ ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VCVTPS2DQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtps2dq_avx512f( ZmmReg2_m512_m32bcst ); @@ -478,7 +478,7 @@ define pcodeop vcvtps2dq_avx512f ; # CVTPS2PD 3-249 PAGE 819 LINE 44104 define pcodeop vcvtps2pd_avx512vl ; -:VCVTPS2PD XmmReg1 XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst +:VCVTPS2PD XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvtps2pd_avx512vl( XmmReg2_m64_m32bcst ); @@ -488,7 +488,7 @@ define pcodeop vcvtps2pd_avx512vl ; } # CVTPS2PD 3-249 PAGE 819 LINE 44107 -:VCVTPS2PD YmmReg1 YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst +:VCVTPS2PD YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvtps2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -499,7 +499,7 @@ define pcodeop vcvtps2pd_avx512vl ; # CVTPS2PD 3-249 PAGE 819 LINE 44110 define pcodeop vcvtps2pd_avx512f ; -:VCVTPS2PD ZmmReg1 ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst +:VCVTPS2PD ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvtps2pd_avx512f( YmmReg2_m256_m32bcst ); @@ -528,7 +528,7 @@ define pcodeop vcvtsd2si_avx512f ; # CVTSD2SS 3-255 PAGE 825 LINE 44417 define pcodeop vcvtsd2ss_avx512f ; -:VCVTSD2SS XmmReg1 XmmOpMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64 +:VCVTSD2SS XmmReg1^XmmOpMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vcvtsd2ss_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -578,7 +578,7 @@ define pcodeop vcvtsi2ss_avx512f ; # CVTSS2SD 3-261 PAGE 831 LINE 44747 define pcodeop vcvtss2sd_avx512f ; -:VCVTSS2SD XmmReg1 XmmOpMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32 +:VCVTSS2SD XmmReg1^XmmOpMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vcvtss2sd_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -608,7 +608,7 @@ define pcodeop vcvtss2si_avx512f ; # CVTTPD2DQ 3-265 PAGE 835 LINE 44936 define pcodeop vcvttpd2dq_avx512vl ; -:VCVTTPD2DQ XmmReg1 XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst +:VCVTTPD2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttpd2dq_avx512vl( XmmReg2_m128_m64bcst ); @@ -618,7 +618,7 @@ define pcodeop vcvttpd2dq_avx512vl ; } # CVTTPD2DQ 3-265 PAGE 835 LINE 44940 -:VCVTTPD2DQ XmmReg1 XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst +:VCVTTPD2DQ XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttpd2dq_avx512vl( YmmReg2_m256_m64bcst ); @@ -629,7 +629,7 @@ define pcodeop vcvttpd2dq_avx512vl ; # CVTTPD2DQ 3-265 PAGE 835 LINE 44944 define pcodeop vcvttpd2dq_avx512f ; -:VCVTTPD2DQ YmmReg1 YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst +:VCVTTPD2DQ YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvttpd2dq_avx512f( ZmmReg2_m512_m64bcst ); @@ -640,7 +640,7 @@ define pcodeop vcvttpd2dq_avx512f ; # CVTTPS2DQ 3-270 PAGE 840 LINE 45169 define pcodeop vcvttps2dq_avx512vl ; -:VCVTTPS2DQ XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTTPS2DQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttps2dq_avx512vl( XmmReg2_m128_m32bcst ); @@ -650,7 +650,7 @@ define pcodeop vcvttps2dq_avx512vl ; } # CVTTPS2DQ 3-270 PAGE 840 LINE 45173 -:VCVTTPS2DQ YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTTPS2DQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvttps2dq_avx512vl( YmmReg2_m256_m32bcst ); @@ -661,7 +661,7 @@ define pcodeop vcvttps2dq_avx512vl ; # CVTTPS2DQ 3-270 PAGE 840 LINE 45177 define pcodeop vcvttps2dq_avx512f ; -:VCVTTPS2DQ ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VCVTTPS2DQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvttps2dq_avx512f( ZmmReg2_m512_m32bcst ); @@ -708,7 +708,7 @@ define pcodeop vcvttss2si_avx512f ; # DIVPD 3-288 PAGE 858 LINE 46029 define pcodeop vdivpd_avx512vl ; -:VDIVPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VDIVPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vdivpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -718,7 +718,7 @@ define pcodeop vdivpd_avx512vl ; } # DIVPD 3-288 PAGE 858 LINE 46033 -:VDIVPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VDIVPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vdivpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -729,7 +729,7 @@ define pcodeop vdivpd_avx512vl ; # DIVPD 3-288 PAGE 858 LINE 46037 define pcodeop vdivpd_avx512f ; -:VDIVPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VDIVPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vdivpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -740,7 +740,7 @@ define pcodeop vdivpd_avx512f ; # DIVPS 3-291 PAGE 861 LINE 46170 define pcodeop vdivps_avx512vl ; -:VDIVPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VDIVPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vdivps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -750,7 +750,7 @@ define pcodeop vdivps_avx512vl ; } # DIVPS 3-291 PAGE 861 LINE 46174 -:VDIVPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VDIVPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vdivps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -761,7 +761,7 @@ define pcodeop vdivps_avx512vl ; # DIVPS 3-291 PAGE 861 LINE 46178 define pcodeop vdivps_avx512f ; -:VDIVPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VDIVPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vdivps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -772,7 +772,7 @@ define pcodeop vdivps_avx512f ; # DIVSD 3-294 PAGE 864 LINE 46315 define pcodeop vdivsd_avx512f ; -:VDIVSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VDIVSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vdivsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -783,7 +783,7 @@ define pcodeop vdivsd_avx512f ; # DIVSS 3-296 PAGE 866 LINE 46413 define pcodeop vdivss_avx512f ; -:VDIVSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VDIVSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vdivss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -812,7 +812,7 @@ define pcodeop vinsertps_avx512f ; # MAXPD 4-12 PAGE 1132 LINE 59206 define pcodeop vmaxpd_avx512vl ; -:VMAXPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VMAXPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vmaxpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -822,7 +822,7 @@ define pcodeop vmaxpd_avx512vl ; } # MAXPD 4-12 PAGE 1132 LINE 59210 -:VMAXPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VMAXPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vmaxpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -833,7 +833,7 @@ define pcodeop vmaxpd_avx512vl ; # MAXPD 4-12 PAGE 1132 LINE 59214 define pcodeop vmaxpd_avx512f ; -:VMAXPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VMAXPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vmaxpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -844,7 +844,7 @@ define pcodeop vmaxpd_avx512f ; # MAXPS 4-15 PAGE 1135 LINE 59356 define pcodeop vmaxps_avx512vl ; -:VMAXPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VMAXPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vmaxps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -854,7 +854,7 @@ define pcodeop vmaxps_avx512vl ; } # MAXPS 4-15 PAGE 1135 LINE 59359 -:VMAXPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VMAXPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vmaxps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -865,7 +865,7 @@ define pcodeop vmaxps_avx512vl ; # MAXPS 4-15 PAGE 1135 LINE 59362 define pcodeop vmaxps_avx512f ; -:VMAXPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VMAXPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vmaxps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -876,7 +876,7 @@ define pcodeop vmaxps_avx512f ; # MAXSD 4-18 PAGE 1138 LINE 59506 define pcodeop vmaxsd_avx512f ; -:VMAXSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VMAXSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vmaxsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -887,7 +887,7 @@ define pcodeop vmaxsd_avx512f ; # MAXSS 4-20 PAGE 1140 LINE 59609 define pcodeop vmaxss_avx512f ; -:VMAXSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VMAXSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vmaxss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -898,7 +898,7 @@ define pcodeop vmaxss_avx512f ; # MINPD 4-23 PAGE 1143 LINE 59771 define pcodeop vminpd_avx512vl ; -:VMINPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VMINPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vminpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -908,7 +908,7 @@ define pcodeop vminpd_avx512vl ; } # MINPD 4-23 PAGE 1143 LINE 59774 -:VMINPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VMINPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vminpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -919,7 +919,7 @@ define pcodeop vminpd_avx512vl ; # MINPD 4-23 PAGE 1143 LINE 59777 define pcodeop vminpd_avx512f ; -:VMINPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VMINPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vminpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -930,7 +930,7 @@ define pcodeop vminpd_avx512f ; # MINPS 4-26 PAGE 1146 LINE 59915 define pcodeop vminps_avx512vl ; -:VMINPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VMINPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vminps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -940,7 +940,7 @@ define pcodeop vminps_avx512vl ; } # MINPS 4-26 PAGE 1146 LINE 59918 -:VMINPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VMINPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vminps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -951,7 +951,7 @@ define pcodeop vminps_avx512vl ; # MINPS 4-26 PAGE 1146 LINE 59921 define pcodeop vminps_avx512f ; -:VMINPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VMINPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vminps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -962,7 +962,7 @@ define pcodeop vminps_avx512f ; # MINSD 4-29 PAGE 1149 LINE 60063 define pcodeop vminsd_avx512f ; -:VMINSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VMINSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vminsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -973,7 +973,7 @@ define pcodeop vminsd_avx512f ; # MINSS 4-31 PAGE 1151 LINE 60166 define pcodeop vminss_avx512f ; -:VMINSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VMINSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vminss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -983,7 +983,7 @@ define pcodeop vminss_avx512f ; } # MOVAPD 4-45 PAGE 1165 LINE 60852 -:VMOVAPD XmmReg1 XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VMOVAPD XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = XmmReg2_m128 ; @@ -993,7 +993,7 @@ define pcodeop vminss_avx512f ; } # MOVAPD 4-45 PAGE 1165 LINE 60855 -:VMOVAPD YmmReg1 YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVAPD YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = YmmReg2_m256; @@ -1004,7 +1004,7 @@ define pcodeop vminss_avx512f ; # MOVAPD 4-45 PAGE 1165 LINE 60858 define pcodeop vmovapd_avx512f ; -:VMOVAPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVAPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = ZmmReg2_m512; @@ -1013,7 +1013,7 @@ define pcodeop vmovapd_avx512f ; ZmmReg1 = ZmmResult; } -:VMOVAPD XmmReg2 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VMOVAPD XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1 ; @@ -1022,7 +1022,7 @@ define pcodeop vmovapd_avx512f ; ZmmReg2 = zext(XmmResult); } -:VMOVAPD m128 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 ... & m128 +:VMOVAPD m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x29; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1 ; @@ -1032,7 +1032,7 @@ define pcodeop vmovapd_avx512f ; } # MOVAPD 4-45 PAGE 1165 LINE 60864 -:VMOVAPD YmmReg2 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VMOVAPD YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmResult = YmmReg1 ; @@ -1051,7 +1051,7 @@ define pcodeop vmovapd_avx512f ; } # MOVAPD 4-45 PAGE 1165 LINE 60867 -:VMOVAPD ZmmReg2 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x29; ZmmReg1 & mod=3 & ZmmReg2 +:VMOVAPD ZmmReg2^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x29; ZmmReg1 & mod=3 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmResult = ZmmReg1 ; @@ -1070,7 +1070,7 @@ define pcodeop vmovapd_avx512f ; } # MOVAPS 4-49 PAGE 1169 LINE 61047 -:VMOVAPS XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVAPS XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = XmmReg2_m128; @@ -1080,7 +1080,7 @@ define pcodeop vmovapd_avx512f ; } # MOVAPS 4-49 PAGE 1169 LINE 61050 -:VMOVAPS YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVAPS YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = YmmReg2_m256; @@ -1091,7 +1091,7 @@ define pcodeop vmovapd_avx512f ; # MOVAPS 4-49 PAGE 1169 LINE 61053 define pcodeop vmovaps_avx512f ; -:VMOVAPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVAPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x28; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = ZmmReg2_m512 ; @@ -1101,7 +1101,7 @@ define pcodeop vmovaps_avx512f ; } # MOVAPS 4-49 PAGE 1169 LINE 61056 -:VMOVAPS XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VMOVAPS XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1; @@ -1110,7 +1110,7 @@ define pcodeop vmovaps_avx512f ; ZmmReg2 = zext(XmmResult); } -:VMOVAPS m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; (XmmReg1) ... & m128 +:VMOVAPS m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x29; (XmmReg1) ... & m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1; @@ -1120,7 +1120,7 @@ define pcodeop vmovaps_avx512f ; } # MOVAPS 4-49 PAGE 1169 LINE 61059 -:VMOVAPS YmmReg2 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VMOVAPS YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x29; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmResult = YmmReg1; @@ -1139,7 +1139,7 @@ define pcodeop vmovaps_avx512f ; } # MOVAPS 4-49 PAGE 1169 LINE 61062 -:VMOVAPS ZmmReg2 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; ZmmReg1 & mod=3 & ZmmOpMask32 & ZmmReg2 +:VMOVAPS ZmmReg2^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x29; ZmmReg1 & mod=3 & ZmmOpMask32 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmResult = ZmmReg1 ; @@ -1191,7 +1191,7 @@ define pcodeop vmovaps_avx512f ; # MOVDDUP 4-59 PAGE 1179 LINE 61526 define pcodeop vmovddup_avx512vl ; -:VMOVDDUP XmmReg1 XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VMOVDDUP XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM) { XmmResult = vmovddup_avx512vl( XmmReg2_m64 ); @@ -1201,7 +1201,7 @@ define pcodeop vmovddup_avx512vl ; } # MOVDDUP 4-59 PAGE 1179 LINE 61529 -:VMOVDDUP YmmReg1 YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVDDUP YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM) { YmmResult = vmovddup_avx512vl( YmmReg2_m256 ); @@ -1212,7 +1212,7 @@ define pcodeop vmovddup_avx512vl ; # MOVDDUP 4-59 PAGE 1179 LINE 61532 define pcodeop vmovddup_avx512f ; -:VMOVDDUP ZmmReg1 ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVDDUP ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x12; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM) { ZmmResult = vmovddup_avx512f( ZmmReg2_m512 ); @@ -1223,7 +1223,7 @@ define pcodeop vmovddup_avx512f ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61675 define pcodeop vmovdqa32_avx512vl ; -:VMOVDQA32 XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVDQA32 XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = vmovdqa32_avx512vl( XmmReg2_m128 ); @@ -1233,7 +1233,7 @@ define pcodeop vmovdqa32_avx512vl ; } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61678 -:VMOVDQA32 YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVDQA32 YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = vmovdqa32_avx512vl( YmmReg2_m256 ); @@ -1244,7 +1244,7 @@ define pcodeop vmovdqa32_avx512vl ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61681 define pcodeop vmovdqa32_avx512f ; -:VMOVDQA32 ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVDQA32 ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = vmovdqa32_avx512f( ZmmReg2_m512 ); @@ -1254,21 +1254,21 @@ define pcodeop vmovdqa32_avx512f ; } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61684 -:VMOVDQA32 XmmReg2_m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVDQA32 XmmReg2_m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqa32_avx512vl( XmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61687 -:VMOVDQA32 YmmReg2_m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVDQA32 YmmReg2_m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqa32_avx512vl( YmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61690 -:VMOVDQA32 ZmmReg2_m512 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVDQA32 ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqa32_avx512f( ZmmReg1 ); @@ -1276,7 +1276,7 @@ define pcodeop vmovdqa32_avx512f ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61693 define pcodeop vmovdqa64_avx512vl ; -:VMOVDQA64 XmmReg1 XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VMOVDQA64 XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = vmovdqa64_avx512vl( XmmReg2_m128 ); @@ -1286,7 +1286,7 @@ define pcodeop vmovdqa64_avx512vl ; } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61696 -:VMOVDQA64 YmmReg1 YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVDQA64 YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = vmovdqa64_avx512vl( YmmReg2_m256 ); @@ -1297,7 +1297,7 @@ define pcodeop vmovdqa64_avx512vl ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61699 define pcodeop vmovdqa64_avx512f ; -:VMOVDQA64 ZmmReg1 ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVDQA64 ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = vmovdqa64_avx512f( ZmmReg2_m512 ); @@ -1307,21 +1307,21 @@ define pcodeop vmovdqa64_avx512f ; } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61702 -:VMOVDQA64 XmmReg2_m128 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VMOVDQA64 XmmReg2_m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqa64_avx512vl( XmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61705 -:VMOVDQA64 YmmReg2_m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVDQA64 YmmReg2_m256^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqa64_avx512vl( YmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61708 -:VMOVDQA64 ZmmReg2_m512 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVDQA64 ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqa64_avx512f( ZmmReg1 ); @@ -1329,7 +1329,7 @@ define pcodeop vmovdqa64_avx512f ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61938 define pcodeop vmovdqu8_avx512vl ; -:VMOVDQU8 XmmReg1 XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VMOVDQU8 XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = vmovdqu8_avx512vl( XmmReg2_m128 ); @@ -1339,7 +1339,7 @@ define pcodeop vmovdqu8_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61941 -:VMOVDQU8 YmmReg1 YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VMOVDQU8 YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = vmovdqu8_avx512vl( YmmReg2_m256 ); @@ -1350,7 +1350,7 @@ define pcodeop vmovdqu8_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61944 define pcodeop vmovdqu8_avx512bw ; -:VMOVDQU8 ZmmReg1 ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VMOVDQU8 ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = vmovdqu8_avx512bw( ZmmReg2_m512 ); @@ -1360,21 +1360,21 @@ define pcodeop vmovdqu8_avx512bw ; } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61947 -:VMOVDQU8 XmmReg2_m128 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VMOVDQU8 XmmReg2_m128^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu8_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61950 -:VMOVDQU8 YmmReg2_m256 YmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VMOVDQU8 YmmReg2_m256^YmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu8_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61953 -:VMOVDQU8 ZmmReg2_m512 ZmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VMOVDQU8 ZmmReg2_m512^ZmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu8_avx512bw( ZmmReg1 ); @@ -1382,7 +1382,7 @@ define pcodeop vmovdqu8_avx512bw ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61956 define pcodeop vmovdqu16_avx512vl ; -:VMOVDQU16 XmmReg1 XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VMOVDQU16 XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = vmovdqu16_avx512vl( XmmReg2_m128 ); @@ -1392,7 +1392,7 @@ define pcodeop vmovdqu16_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61959 -:VMOVDQU16 YmmReg1 YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VMOVDQU16 YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = vmovdqu16_avx512vl( YmmReg2_m256 ); @@ -1403,7 +1403,7 @@ define pcodeop vmovdqu16_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61962 define pcodeop vmovdqu16_avx512bw ; -:VMOVDQU16 ZmmReg1 ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VMOVDQU16 ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = vmovdqu16_avx512bw( ZmmReg2_m512 ); @@ -1413,21 +1413,21 @@ define pcodeop vmovdqu16_avx512bw ; } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61965 -:VMOVDQU16 XmmReg2_m128 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VMOVDQU16 XmmReg2_m128^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu16_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61968 -:VMOVDQU16 YmmReg2_m256 YmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VMOVDQU16 YmmReg2_m256^YmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu16_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61971 -:VMOVDQU16 ZmmReg2_m512 ZmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VMOVDQU16 ZmmReg2_m512^ZmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu16_avx512bw( ZmmReg1 ); @@ -1435,7 +1435,7 @@ define pcodeop vmovdqu16_avx512bw ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61974 define pcodeop vmovdqu32_avx512vl ; -:VMOVDQU32 XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVDQU32 XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = vmovdqu32_avx512vl( XmmReg2_m128 ); @@ -1445,7 +1445,7 @@ define pcodeop vmovdqu32_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61987 -:VMOVDQU32 YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVDQU32 YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = vmovdqu32_avx512vl( YmmReg2_m256 ); @@ -1456,7 +1456,7 @@ define pcodeop vmovdqu32_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61990 define pcodeop vmovdqu32_avx512f ; -:VMOVDQU32 ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVDQU32 ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x6F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = vmovdqu32_avx512f( ZmmReg2_m512 ); @@ -1466,21 +1466,21 @@ define pcodeop vmovdqu32_avx512f ; } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61993 -:VMOVDQU32 XmmReg2_m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVDQU32 XmmReg2_m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (XmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu32_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61996 -:VMOVDQU32 YmmReg2_m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVDQU32 YmmReg2_m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (YmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu32_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61999 -:VMOVDQU32 ZmmReg2_m512 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVDQU32 ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu32_avx512f( ZmmReg1 ); @@ -1488,7 +1488,7 @@ define pcodeop vmovdqu32_avx512f ; # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62002 define pcodeop vmovdqu64_avx512vl ; -:VMOVDQU64 XmmReg1 XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VMOVDQU64 XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = vmovdqu64_avx512vl( XmmReg2_m128 ); @@ -1498,7 +1498,7 @@ define pcodeop vmovdqu64_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62005 -:VMOVDQU64 YmmReg1 YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVDQU64 YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = vmovdqu64_avx512vl( YmmReg2_m256 ); @@ -1509,7 +1509,7 @@ define pcodeop vmovdqu64_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62008 define pcodeop vmovdqu64_avx512f ; -:VMOVDQU64 ZmmReg1 ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVDQU64 ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x6F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = vmovdqu64_avx512f( ZmmReg2_m512 ); @@ -1519,21 +1519,21 @@ define pcodeop vmovdqu64_avx512f ; } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62011 -:VMOVDQU64 XmmReg2_m128 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VMOVDQU64 XmmReg2_m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (XmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu64_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62014 -:VMOVDQU64 YmmReg2_m256 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVDQU64 YmmReg2_m256^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (YmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu64_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62017 -:VMOVDQU64 ZmmReg2_m512 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVDQU64 ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1); byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu64_avx512f( ZmmReg1 ); @@ -1744,7 +1744,7 @@ define pcodeop vmovntps_avx512f ; # MOVSD 4-111 PAGE 1231 LINE 63978 define pcodeop vmovsd_avx512f ; -:VMOVSD XmmReg1 XmmOpMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2) +:VMOVSD XmmReg1^XmmOpMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2) { XmmResult = XmmReg2; XmmMask = XmmReg1; @@ -1755,7 +1755,7 @@ define pcodeop vmovsd_avx512f ; } # MOVSD 4-111 PAGE 1231 LINE 63981 -:VMOVSD XmmReg1 XmmOpMask, m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m64 +:VMOVSD XmmReg1^XmmOpMask, m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM) { local tmp:8 = m64; @@ -1766,7 +1766,7 @@ define pcodeop vmovsd_avx512f ; } # MOVSD 4-111 PAGE 1231 LINE 63983 -:VMOVSD XmmReg2 XmmOpMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & ZmmReg1 & XmmOpMask & (mod=0x3 & XmmReg2) +:VMOVSD XmmReg2^XmmOpMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & ZmmReg1 & XmmOpMask & (mod=0x3 & XmmReg2) { XmmResult = XmmReg1; XmmMask = XmmReg2; @@ -1777,7 +1777,7 @@ define pcodeop vmovsd_avx512f ; } # MOVSD 4-111 PAGE 1231 LINE 63986 -:VMOVSD m64 XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & XmmOpMask; byte=0x11; XmmReg1 ... & m64 +:VMOVSD m64^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & XmmOpMask; byte=0x11; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR) { XmmResult = vmovsd_avx512f( XmmReg1 ); @@ -1791,7 +1791,7 @@ define pcodeop vmovsd_avx512f ; # MOVSHDUP 4-114 PAGE 1234 LINE 64130 define pcodeop vmovshdup_avx512vl ; -:VMOVSHDUP XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVSHDUP XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vmovshdup_avx512vl( XmmReg2_m128 ); @@ -1801,7 +1801,7 @@ define pcodeop vmovshdup_avx512vl ; } # MOVSHDUP 4-114 PAGE 1234 LINE 64133 -:VMOVSHDUP YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVSHDUP YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vmovshdup_avx512vl( YmmReg2_m256 ); @@ -1812,7 +1812,7 @@ define pcodeop vmovshdup_avx512vl ; # MOVSHDUP 4-114 PAGE 1234 LINE 64136 define pcodeop vmovshdup_avx512f ; -:VMOVSHDUP ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVSHDUP ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vmovshdup_avx512f( ZmmReg2_m512 ); @@ -1823,7 +1823,7 @@ define pcodeop vmovshdup_avx512f ; # MOVSLDUP 4-117 PAGE 1237 LINE 64284 define pcodeop vmovsldup_avx512vl ; -:VMOVSLDUP XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVSLDUP XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vmovsldup_avx512vl( XmmReg2_m128 ); @@ -1833,7 +1833,7 @@ define pcodeop vmovsldup_avx512vl ; } # MOVSLDUP 4-117 PAGE 1237 LINE 64287 -:VMOVSLDUP YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVSLDUP YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vmovsldup_avx512vl( YmmReg2_m256 ); @@ -1844,7 +1844,7 @@ define pcodeop vmovsldup_avx512vl ; # MOVSLDUP 4-117 PAGE 1237 LINE 64290 define pcodeop vmovsldup_avx512f ; -:VMOVSLDUP ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVSLDUP ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x12; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vmovsldup_avx512f( ZmmReg2_m512 ); @@ -1854,7 +1854,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVSS 4-120 PAGE 1240 LINE 64443 -:VMOVSS XmmReg1 XmmOpMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2) +:VMOVSS XmmReg1^XmmOpMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) & (mod=0x3 & XmmReg2) { local tmp:4 = XmmReg2[0,32]; XmmMask = XmmReg1; @@ -1865,7 +1865,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVSS 4-120 PAGE 1240 LINE 64446 -:VMOVSS XmmReg1 XmmOpMask, m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m32 +:VMOVSS XmmReg1^XmmOpMask, m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM) { local tmp:4 = m32; @@ -1876,7 +1876,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVSS 4-120 PAGE 1240 LINE 64448 -:VMOVSS XmmReg2 XmmOpMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2)) +:VMOVSS XmmReg2^XmmOpMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2)) { local tmp:4 = XmmReg1[0,32]; XmmMask = XmmReg2; @@ -1887,7 +1887,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVSS 4-120 PAGE 1240 LINE 64451 -:VMOVSS m32 XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask; byte=0x11; XmmReg1 ... & m32 +:VMOVSS m32^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & XmmOpMask; byte=0x11; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR) { local tmp:4 = XmmReg1[0,32]; @@ -1897,7 +1897,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPD 4-126 PAGE 1246 LINE 64695 -:VMOVUPD XmmReg1 XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VMOVUPD XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = XmmReg2_m128 ; @@ -1907,7 +1907,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPD 4-126 PAGE 1246 LINE 64698 -:VMOVUPD XmmReg2 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VMOVUPD XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1; @@ -1916,7 +1916,7 @@ define pcodeop vmovsldup_avx512f ; ZmmReg2 = zext(XmmResult); } -:VMOVUPD m128 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; (XmmReg1) ... & m128 +:VMOVUPD m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & XmmOpMask64; byte=0x11; (XmmReg1) ... & m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1; @@ -1926,7 +1926,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPD 4-126 PAGE 1246 LINE 64701 -:VMOVUPD YmmReg1 YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VMOVUPD YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = YmmReg2_m256; @@ -1936,7 +1936,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPD 4-126 PAGE 1246 LINE 64704 -:VMOVUPD YmmReg2 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VMOVUPD YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & YmmOpMask64; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmResult = YmmReg1; @@ -1955,7 +1955,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPD 4-126 PAGE 1246 LINE 64707 -:VMOVUPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VMOVUPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x10; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = ZmmReg2_m512; @@ -1965,7 +1965,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPD 4-126 PAGE 1246 LINE 64710 -:VMOVUPD ZmmReg2_m512 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 +:VMOVUPD ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & ZmmOpMask64; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmResult = ZmmReg1; @@ -1975,7 +1975,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPS 4-130 PAGE 1250 LINE 64880 -:VMOVUPS XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VMOVUPS XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { XmmResult = XmmReg2_m128; @@ -1985,7 +1985,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPS 4-130 PAGE 1250 LINE 64883 -:VMOVUPS YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VMOVUPS YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { YmmResult = YmmReg2_m256; @@ -1995,7 +1995,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPS 4-130 PAGE 1250 LINE 64886 -:VMOVUPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VMOVUPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x10; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmResult = ZmmReg2_m512; @@ -2005,7 +2005,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPS 4-130 PAGE 1250 LINE 64889 -:VMOVUPS XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VMOVUPS XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1; @@ -2014,7 +2014,7 @@ define pcodeop vmovsldup_avx512f ; ZmmReg2 = zext(XmmResult); } -:VMOVUPS m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 ... & m128 +:VMOVUPS m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & XmmOpMask32; byte=0x11; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmResult = XmmReg1; @@ -2024,7 +2024,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPS 4-130 PAGE 1250 LINE 64892 -:VMOVUPS YmmReg2 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VMOVUPS YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & YmmOpMask32; byte=0x11; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmResult = YmmReg1; @@ -2043,7 +2043,7 @@ define pcodeop vmovsldup_avx512f ; } # MOVUPS 4-130 PAGE 1250 LINE 64895 -:VMOVUPS ZmmReg2_m512 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & ZmmOpMask32; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 +:VMOVUPS ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & ZmmOpMask32; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmResult = ZmmReg1; @@ -2054,7 +2054,7 @@ define pcodeop vmovsldup_avx512f ; # MULPD 4-146 PAGE 1266 LINE 65686 define pcodeop vmulpd_avx512vl ; -:VMULPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VMULPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vmulpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2064,7 +2064,7 @@ define pcodeop vmulpd_avx512vl ; } # MULPD 4-146 PAGE 1266 LINE 65689 -:VMULPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VMULPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vmulpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2075,7 +2075,7 @@ define pcodeop vmulpd_avx512vl ; # MULPD 4-146 PAGE 1266 LINE 65692 define pcodeop vmulpd_avx512f ; -:VMULPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VMULPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vmulpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2086,7 +2086,7 @@ define pcodeop vmulpd_avx512f ; # MULPS 4-149 PAGE 1269 LINE 65817 define pcodeop vmulps_avx512vl ; -:VMULPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VMULPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vmulps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2096,7 +2096,7 @@ define pcodeop vmulps_avx512vl ; } # MULPS 4-149 PAGE 1269 LINE 65820 -:VMULPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VMULPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vmulps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2107,7 +2107,7 @@ define pcodeop vmulps_avx512vl ; # MULPS 4-149 PAGE 1269 LINE 65823 define pcodeop vmulps_avx512f ; -:VMULPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VMULPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vmulps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2118,7 +2118,7 @@ define pcodeop vmulps_avx512f ; # MULSD 4-152 PAGE 1272 LINE 65959 define pcodeop vmulsd_avx512f ; -:VMULSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VMULSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vmulsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -2129,7 +2129,7 @@ define pcodeop vmulsd_avx512f ; # MULSS 4-154 PAGE 1274 LINE 66055 define pcodeop vmulss_avx512f ; -:VMULSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VMULSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vmulss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -2140,7 +2140,7 @@ define pcodeop vmulss_avx512f ; # ORPD 4-168 PAGE 1288 LINE 66724 define pcodeop vorpd_avx512vl ; -:VORPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VORPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vorpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2150,7 +2150,7 @@ define pcodeop vorpd_avx512vl ; } # ORPD 4-168 PAGE 1288 LINE 66727 -:VORPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VORPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vorpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2161,7 +2161,7 @@ define pcodeop vorpd_avx512vl ; # ORPD 4-168 PAGE 1288 LINE 66730 define pcodeop vorpd_avx512dq ; -:VORPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2172,7 +2172,7 @@ define pcodeop vorpd_avx512dq ; # ORPS 4-171 PAGE 1291 LINE 66850 define pcodeop vorps_avx512vl ; -:VORPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VORPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vorps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2182,7 +2182,7 @@ define pcodeop vorps_avx512vl ; } # ORPS 4-171 PAGE 1291 LINE 66853 -:VORPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VORPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vorps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2193,7 +2193,7 @@ define pcodeop vorps_avx512vl ; # ORPS 4-171 PAGE 1291 LINE 66856 define pcodeop vorps_avx512dq ; -:VORPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2204,7 +2204,7 @@ define pcodeop vorps_avx512dq ; # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67320 define pcodeop vpabsb_avx512vl ; -:VPABSB XmmReg1 XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPABSB XmmReg1^XmmOpMask8, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpabsb_avx512vl( XmmReg2_m128 ); @@ -2214,7 +2214,7 @@ define pcodeop vpabsb_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67323 -:VPABSB YmmReg1 YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPABSB YmmReg1^YmmOpMask8, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpabsb_avx512vl( YmmReg2_m256 ); @@ -2225,7 +2225,7 @@ define pcodeop vpabsb_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67326 define pcodeop vpabsb_avx512bw ; -:VPABSB ZmmReg1 ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPABSB ZmmReg1^ZmmOpMask8, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpabsb_avx512bw( ZmmReg2_m512 ); @@ -2236,7 +2236,7 @@ define pcodeop vpabsb_avx512bw ; # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67329 define pcodeop vpabsw_avx512vl ; -:VPABSW XmmReg1 XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPABSW XmmReg1^XmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpabsw_avx512vl( XmmReg2_m128 ); @@ -2246,7 +2246,7 @@ define pcodeop vpabsw_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67344 -:VPABSW YmmReg1 YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPABSW YmmReg1^YmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpabsw_avx512vl( YmmReg2_m256 ); @@ -2257,7 +2257,7 @@ define pcodeop vpabsw_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67347 define pcodeop vpabsw_avx512bw ; -:VPABSW ZmmReg1 ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPABSW ZmmReg1^ZmmOpMask16, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x1D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpabsw_avx512bw( ZmmReg2_m512 ); @@ -2268,7 +2268,7 @@ define pcodeop vpabsw_avx512bw ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67350 define pcodeop vpabsd_avx512vl ; -:VPABSD XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPABSD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpabsd_avx512vl( XmmReg2_m128_m32bcst ); @@ -2278,7 +2278,7 @@ define pcodeop vpabsd_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67353 -:VPABSD YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPABSD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpabsd_avx512vl( YmmReg2_m256_m32bcst ); @@ -2289,7 +2289,7 @@ define pcodeop vpabsd_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67357 define pcodeop vpabsd_avx512f ; -:VPABSD ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPABSD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpabsd_avx512f( ZmmReg2_m512_m32bcst ); @@ -2300,7 +2300,7 @@ define pcodeop vpabsd_avx512f ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67360 define pcodeop vpabsq_avx512vl ; -:VPABSQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPABSQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpabsq_avx512vl( XmmReg2_m128_m64bcst ); @@ -2310,7 +2310,7 @@ define pcodeop vpabsq_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67363 -:VPABSQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPABSQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpabsq_avx512vl( YmmReg2_m256_m64bcst ); @@ -2321,7 +2321,7 @@ define pcodeop vpabsq_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67366 define pcodeop vpabsq_avx512f ; -:VPABSQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPABSQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpabsq_avx512f( ZmmReg2_m512_m64bcst ); @@ -2332,7 +2332,7 @@ define pcodeop vpabsq_avx512f ; # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67645 define pcodeop vpacksswb_avx512vl ; -:VPACKSSWB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPACKSSWB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpacksswb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2342,7 +2342,7 @@ define pcodeop vpacksswb_avx512vl ; } # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67649 -:VPACKSSWB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPACKSSWB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpacksswb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2353,7 +2353,7 @@ define pcodeop vpacksswb_avx512vl ; # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67653 define pcodeop vpacksswb_avx512bw ; -:VPACKSSWB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x63; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPACKSSWB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x63; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpacksswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2364,7 +2364,7 @@ define pcodeop vpacksswb_avx512bw ; # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67657 define pcodeop vpackssdw_avx512vl ; -:VPACKSSDW XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPACKSSDW XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpackssdw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2374,7 +2374,7 @@ define pcodeop vpackssdw_avx512vl ; } # PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67674 -:VPACKSSDW YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPACKSSDW YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpackssdw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2385,7 +2385,7 @@ define pcodeop vpackssdw_avx512vl ; # PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67678 define pcodeop vpackssdw_avx512bw ; -:VPACKSSDW ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPACKSSDW ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpackssdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2396,7 +2396,7 @@ define pcodeop vpackssdw_avx512bw ; # PACKUSDW 4-194 PAGE 1314 LINE 68094 define pcodeop vpackusdw_avx512vl ; -:VPACKUSDW XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPACKUSDW XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpackusdw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2406,7 +2406,7 @@ define pcodeop vpackusdw_avx512vl ; } # PACKUSDW 4-194 PAGE 1314 LINE 68098 -:VPACKUSDW YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPACKUSDW YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpackusdw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2417,7 +2417,7 @@ define pcodeop vpackusdw_avx512vl ; # PACKUSDW 4-194 PAGE 1314 LINE 68103 define pcodeop vpackusdw_avx512bw ; -:VPACKUSDW ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPACKUSDW ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpackusdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2428,7 +2428,7 @@ define pcodeop vpackusdw_avx512bw ; # PACKUSWB 4-199 PAGE 1319 LINE 68374 define pcodeop vpackuswb_avx512vl ; -:VPACKUSWB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPACKUSWB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpackuswb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2438,7 +2438,7 @@ define pcodeop vpackuswb_avx512vl ; } # PACKUSWB 4-199 PAGE 1319 LINE 68378 -:VPACKUSWB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPACKUSWB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpackuswb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2449,7 +2449,7 @@ define pcodeop vpackuswb_avx512vl ; # PACKUSWB 4-199 PAGE 1319 LINE 68382 define pcodeop vpackuswb_avx512bw ; -:VPACKUSWB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x67; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPACKUSWB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x67; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpackuswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2460,7 +2460,7 @@ define pcodeop vpackuswb_avx512bw ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68674 define pcodeop vpaddb_avx512vl ; -:VPADDB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPADDB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpaddb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2471,7 +2471,7 @@ define pcodeop vpaddb_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68677 define pcodeop vpaddw_avx512vl ; -:VPADDW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPADDW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpaddw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2482,7 +2482,7 @@ define pcodeop vpaddw_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68680 define pcodeop vpaddd_avx512vl ; -:VPADDD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPADDD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpaddd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2493,7 +2493,7 @@ define pcodeop vpaddd_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68683 define pcodeop vpaddq_avx512vl ; -:VPADDQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPADDQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpaddq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2503,7 +2503,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68686 -:VPADDB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPADDB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpaddb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2513,7 +2513,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68689 -:VPADDW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPADDW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpaddw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2523,7 +2523,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68692 -:VPADDD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPADDD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpaddd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2533,7 +2533,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68707 -:VPADDQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPADDQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpaddq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2544,7 +2544,7 @@ define pcodeop vpaddq_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68710 define pcodeop vpaddb_avx512bw ; -:VPADDB ZmmReg1 ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFC; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512 +:VPADDB ZmmReg1^ZmmOpMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFC; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpaddb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2555,7 +2555,7 @@ define pcodeop vpaddb_avx512bw ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68713 define pcodeop vpaddw_avx512bw ; -:VPADDW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPADDW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xFD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpaddw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2566,7 +2566,7 @@ define pcodeop vpaddw_avx512bw ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68716 define pcodeop vpaddd_avx512f ; -:VPADDD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPADDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpaddd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2577,7 +2577,7 @@ define pcodeop vpaddd_avx512f ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68719 define pcodeop vpaddq_avx512f ; -:VPADDQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPADDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpaddq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2588,7 +2588,7 @@ define pcodeop vpaddq_avx512f ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69051 define pcodeop vpaddsb_avx512vl ; -:VPADDSB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPADDSB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpaddsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2598,7 +2598,7 @@ define pcodeop vpaddsb_avx512vl ; } # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69054 -:VPADDSB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPADDSB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpaddsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2609,7 +2609,7 @@ define pcodeop vpaddsb_avx512vl ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69057 define pcodeop vpaddsb_avx512bw ; -:VPADDSB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPADDSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpaddsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2620,7 +2620,7 @@ define pcodeop vpaddsb_avx512bw ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69060 define pcodeop vpaddsw_avx512vl ; -:VPADDSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPADDSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpaddsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2630,7 +2630,7 @@ define pcodeop vpaddsw_avx512vl ; } # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69063 -:VPADDSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPADDSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpaddsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2641,7 +2641,7 @@ define pcodeop vpaddsw_avx512vl ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69066 define pcodeop vpaddsw_avx512bw ; -:VPADDSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xED; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPADDSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xED; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpaddsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2652,7 +2652,7 @@ define pcodeop vpaddsw_avx512bw ; # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69269 define pcodeop vpaddusb_avx512vl ; -:VPADDUSB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPADDUSB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpaddusb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2662,7 +2662,7 @@ define pcodeop vpaddusb_avx512vl ; } # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69273 -:VPADDUSB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPADDUSB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpaddusb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2673,7 +2673,7 @@ define pcodeop vpaddusb_avx512vl ; # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69277 define pcodeop vpaddusb_avx512bw ; -:VPADDUSB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPADDUSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDC; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpaddusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2684,7 +2684,7 @@ define pcodeop vpaddusb_avx512bw ; # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69281 define pcodeop vpaddusw_avx512vl ; -:VPADDUSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPADDUSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpaddusw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2694,7 +2694,7 @@ define pcodeop vpaddusw_avx512vl ; } # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69285 -:VPADDUSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPADDUSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpaddusw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2705,7 +2705,7 @@ define pcodeop vpaddusw_avx512vl ; # PADDUSB/PADDUSW 4-216 PAGE 1336 LINE 69302 define pcodeop vpaddusw_avx512bw ; -:VPADDUSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPADDUSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDD; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpaddusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2716,7 +2716,7 @@ define pcodeop vpaddusw_avx512bw ; # PALIGNR 4-219 PAGE 1339 LINE 69495 define pcodeop vpalignr_avx512vl ; -:VPALIGNR XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPALIGNR XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpalignr_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2726,7 +2726,7 @@ define pcodeop vpalignr_avx512vl ; } # PALIGNR 4-219 PAGE 1339 LINE 69499 -:VPALIGNR YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPALIGNR YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpalignr_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2737,7 +2737,7 @@ define pcodeop vpalignr_avx512vl ; # PALIGNR 4-219 PAGE 1339 LINE 69505 define pcodeop vpalignr_avx512bw ; -:VPALIGNR ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPALIGNR ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0F; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2748,7 +2748,7 @@ define pcodeop vpalignr_avx512bw ; # PAND 4-223 PAGE 1343 LINE 69684 define pcodeop vpandd_avx512vl ; -:VPANDD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPANDD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpandd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2758,7 +2758,7 @@ define pcodeop vpandd_avx512vl ; } # PAND 4-223 PAGE 1343 LINE 69687 -:VPANDD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPANDD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpandd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2769,7 +2769,7 @@ define pcodeop vpandd_avx512vl ; # PAND 4-223 PAGE 1343 LINE 69690 define pcodeop vpandd_avx512f ; -:VPANDD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPANDD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpandd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2780,7 +2780,7 @@ define pcodeop vpandd_avx512f ; # PAND 4-223 PAGE 1343 LINE 69693 define pcodeop vpandq_avx512vl ; -:VPANDQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPANDQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpandq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2790,7 +2790,7 @@ define pcodeop vpandq_avx512vl ; } # PAND 4-223 PAGE 1343 LINE 69696 -:VPANDQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPANDQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpandq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2801,7 +2801,7 @@ define pcodeop vpandq_avx512vl ; # PAND 4-223 PAGE 1343 LINE 69699 define pcodeop vpandq_avx512f ; -:VPANDQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPANDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpandq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2812,7 +2812,7 @@ define pcodeop vpandq_avx512f ; # PANDN 4-226 PAGE 1346 LINE 69859 define pcodeop vpandnd_avx512vl ; -:VPANDND XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPANDND XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpandnd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2822,7 +2822,7 @@ define pcodeop vpandnd_avx512vl ; } # PANDN 4-226 PAGE 1346 LINE 69862 -:VPANDND YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPANDND YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpandnd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2833,7 +2833,7 @@ define pcodeop vpandnd_avx512vl ; # PANDN 4-226 PAGE 1346 LINE 69865 define pcodeop vpandnd_avx512f ; -:VPANDND ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPANDND ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpandnd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2844,7 +2844,7 @@ define pcodeop vpandnd_avx512f ; # PANDN 4-226 PAGE 1346 LINE 69868 define pcodeop vpandnq_avx512vl ; -:VPANDNQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPANDNQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpandnq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2854,7 +2854,7 @@ define pcodeop vpandnq_avx512vl ; } # PANDN 4-226 PAGE 1346 LINE 69871 -:VPANDNQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPANDNQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpandnq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2865,7 +2865,7 @@ define pcodeop vpandnq_avx512vl ; # PANDN 4-226 PAGE 1346 LINE 69874 define pcodeop vpandnq_avx512f ; -:VPANDNQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPANDNQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xDF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpandnq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2876,7 +2876,7 @@ define pcodeop vpandnq_avx512f ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70097 define pcodeop vpavgb_avx512vl ; -:VPAVGB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPAVGB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpavgb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2886,7 +2886,7 @@ define pcodeop vpavgb_avx512vl ; } # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70100 -:VPAVGB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPAVGB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpavgb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2897,7 +2897,7 @@ define pcodeop vpavgb_avx512vl ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70103 define pcodeop vpavgb_avx512bw ; -:VPAVGB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE0; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPAVGB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE0; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpavgb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2908,7 +2908,7 @@ define pcodeop vpavgb_avx512bw ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70106 define pcodeop vpavgw_avx512vl ; -:VPAVGW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPAVGW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpavgw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2918,7 +2918,7 @@ define pcodeop vpavgw_avx512vl ; } # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70109 -:VPAVGW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPAVGW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpavgw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2929,7 +2929,7 @@ define pcodeop vpavgw_avx512vl ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70112 define pcodeop vpavgw_avx512bw ; -:VPAVGW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE3; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPAVGW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE3; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpavgw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3261,7 +3261,7 @@ define pcodeop vpinsrw_avx512bw ; # PMADDUBSW 4-298 PAGE 1418 LINE 73558 define pcodeop vpmaddubsw_avx512vl ; -:VPMADDUBSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMADDUBSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmaddubsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3271,7 +3271,7 @@ define pcodeop vpmaddubsw_avx512vl ; } # PMADDUBSW 4-298 PAGE 1418 LINE 73562 -:VPMADDUBSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMADDUBSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmaddubsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3282,7 +3282,7 @@ define pcodeop vpmaddubsw_avx512vl ; # PMADDUBSW 4-298 PAGE 1418 LINE 73566 define pcodeop vpmaddubsw_avx512bw ; -:VPMADDUBSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x04; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMADDUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x04; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmaddubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3293,7 +3293,7 @@ define pcodeop vpmaddubsw_avx512bw ; # PMADDWD 4-301 PAGE 1421 LINE 73708 define pcodeop vpmaddwd_avx512vl ; -:VPMADDWD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VPMADDWD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmaddwd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3303,7 +3303,7 @@ define pcodeop vpmaddwd_avx512vl ; } # PMADDWD 4-301 PAGE 1421 LINE 73712 -:VPMADDWD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VPMADDWD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmaddwd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3314,7 +3314,7 @@ define pcodeop vpmaddwd_avx512vl ; # PMADDWD 4-301 PAGE 1421 LINE 73716 define pcodeop vpmaddwd_avx512bw ; -:VPMADDWD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF5; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VPMADDWD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF5; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmaddwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3325,7 +3325,7 @@ define pcodeop vpmaddwd_avx512bw ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73900 define pcodeop vpmaxsb_avx512vl ; -:VPMAXSB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPMAXSB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmaxsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3335,7 +3335,7 @@ define pcodeop vpmaxsb_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73903 -:VPMAXSB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPMAXSB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmaxsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3346,7 +3346,7 @@ define pcodeop vpmaxsb_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73906 define pcodeop vpmaxsb_avx512bw ; -:VPMAXSB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPMAXSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3C; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmaxsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3357,7 +3357,7 @@ define pcodeop vpmaxsb_avx512bw ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73909 define pcodeop vpmaxsw_avx512vl ; -:VPMAXSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMAXSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmaxsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3367,7 +3367,7 @@ define pcodeop vpmaxsw_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73912 -:VPMAXSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMAXSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmaxsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3378,7 +3378,7 @@ define pcodeop vpmaxsw_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73915 define pcodeop vpmaxsw_avx512bw ; -:VPMAXSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEE; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMAXSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEE; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmaxsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3389,7 +3389,7 @@ define pcodeop vpmaxsw_avx512bw ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73918 define pcodeop vpmaxsd_avx512vl ; -:VPMAXSD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPMAXSD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmaxsd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3399,7 +3399,7 @@ define pcodeop vpmaxsd_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73933 -:VPMAXSD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPMAXSD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmaxsd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3410,7 +3410,7 @@ define pcodeop vpmaxsd_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73936 define pcodeop vpmaxsd_avx512f ; -:VPMAXSD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPMAXSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmaxsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3421,7 +3421,7 @@ define pcodeop vpmaxsd_avx512f ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73939 define pcodeop vpmaxsq_avx512vl ; -:VPMAXSQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMAXSQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmaxsq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3431,7 +3431,7 @@ define pcodeop vpmaxsq_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73942 -:VPMAXSQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMAXSQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmaxsq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3442,7 +3442,7 @@ define pcodeop vpmaxsq_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73945 define pcodeop vpmaxsq_avx512f ; -:VPMAXSQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMAXSQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmaxsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3453,7 +3453,7 @@ define pcodeop vpmaxsq_avx512f ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74295 define pcodeop vpmaxub_avx512vl ; -:VPMAXUB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPMAXUB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmaxub_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3463,7 +3463,7 @@ define pcodeop vpmaxub_avx512vl ; } # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74298 -:VPMAXUB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPMAXUB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmaxub_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3474,7 +3474,7 @@ define pcodeop vpmaxub_avx512vl ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74301 define pcodeop vpmaxub_avx512bw ; -:VPMAXUB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDE; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPMAXUB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xDE; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmaxub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3485,7 +3485,7 @@ define pcodeop vpmaxub_avx512bw ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74304 define pcodeop vpmaxuw_avx512vl ; -:VPMAXUW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMAXUW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmaxuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3495,7 +3495,7 @@ define pcodeop vpmaxuw_avx512vl ; } # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74307 -:VPMAXUW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMAXUW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmaxuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3506,7 +3506,7 @@ define pcodeop vpmaxuw_avx512vl ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74310 define pcodeop vpmaxuw_avx512bw ; -:VPMAXUW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3E; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMAXUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x3E; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmaxuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3517,7 +3517,7 @@ define pcodeop vpmaxuw_avx512bw ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74540 define pcodeop vpmaxud_avx512vl ; -:VPMAXUD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPMAXUD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmaxud_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3527,7 +3527,7 @@ define pcodeop vpmaxud_avx512vl ; } # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74543 -:VPMAXUD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPMAXUD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmaxud_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3538,7 +3538,7 @@ define pcodeop vpmaxud_avx512vl ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74546 define pcodeop vpmaxud_avx512f ; -:VPMAXUD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPMAXUD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmaxud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3549,7 +3549,7 @@ define pcodeop vpmaxud_avx512f ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74549 define pcodeop vpmaxuq_avx512vl ; -:VPMAXUQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMAXUQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmaxuq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3559,7 +3559,7 @@ define pcodeop vpmaxuq_avx512vl ; } # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74552 -:VPMAXUQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMAXUQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmaxuq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3570,7 +3570,7 @@ define pcodeop vpmaxuq_avx512vl ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74555 define pcodeop vpmaxuq_avx512f ; -:VPMAXUQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMAXUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmaxuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3581,7 +3581,7 @@ define pcodeop vpmaxuq_avx512f ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74748 define pcodeop vpminsb_avx512vl ; -:VPMINSB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPMINSB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpminsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3591,7 +3591,7 @@ define pcodeop vpminsb_avx512vl ; } # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74751 -:VPMINSB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPMINSB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpminsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3602,7 +3602,7 @@ define pcodeop vpminsb_avx512vl ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74754 define pcodeop vpminsb_avx512bw ; -:VPMINSB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPMINSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpminsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3613,7 +3613,7 @@ define pcodeop vpminsb_avx512bw ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74757 define pcodeop vpminsw_avx512vl ; -:VPMINSW XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPMINSW XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpminsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3623,7 +3623,7 @@ define pcodeop vpminsw_avx512vl ; } # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74760 -:VPMINSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMINSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpminsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3634,7 +3634,7 @@ define pcodeop vpminsw_avx512vl ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74763 define pcodeop vpminsw_avx512bw ; -:VPMINSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEA; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMINSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xEA; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpminsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3645,7 +3645,7 @@ define pcodeop vpminsw_avx512bw ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74995 define pcodeop vpminsd_avx512vl ; -:VPMINSD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPMINSD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpminsd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3655,7 +3655,7 @@ define pcodeop vpminsd_avx512vl ; } # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74998 -:VPMINSD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPMINSD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpminsd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3666,7 +3666,7 @@ define pcodeop vpminsd_avx512vl ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75001 define pcodeop vpminsd_avx512f ; -:VPMINSD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPMINSD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpminsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3677,7 +3677,7 @@ define pcodeop vpminsd_avx512f ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75004 define pcodeop vpminsq_avx512vl ; -:VPMINSQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMINSQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpminsq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3687,7 +3687,7 @@ define pcodeop vpminsq_avx512vl ; } # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75007 -:VPMINSQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMINSQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpminsq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3698,7 +3698,7 @@ define pcodeop vpminsq_avx512vl ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75010 define pcodeop vpminsq_avx512f ; -:VPMINSQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMINSQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x39; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpminsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3709,7 +3709,7 @@ define pcodeop vpminsq_avx512f ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75207 define pcodeop vpminub_avx512vl ; -:VPMINUB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPMINUB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpminub_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3719,7 +3719,7 @@ define pcodeop vpminub_avx512vl ; } # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75210 -:VPMINUB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPMINUB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & vexVVVV_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpminub_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3730,7 +3730,7 @@ define pcodeop vpminub_avx512vl ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75213 define pcodeop vpminub_avx512bw ; -:VPMINUB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_ZmmReg; byte=0xDA; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPMINUB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & evexV5_ZmmReg; byte=0xDA; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpminub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3741,7 +3741,7 @@ define pcodeop vpminub_avx512bw ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75216 define pcodeop vpminuw_avx512vl ; -:VPMINUW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMINUW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpminuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3751,7 +3751,7 @@ define pcodeop vpminuw_avx512vl ; } # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75219 -:VPMINUW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMINUW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & vexVVVV_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpminuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3762,7 +3762,7 @@ define pcodeop vpminuw_avx512vl ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75222 define pcodeop vpminuw_avx512bw ; -:VPMINUW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMINUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpminuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3773,7 +3773,7 @@ define pcodeop vpminuw_avx512bw ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75451 define pcodeop vpminud_avx512vl ; -:VPMINUD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPMINUD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpminud_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3783,7 +3783,7 @@ define pcodeop vpminud_avx512vl ; } # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75454 -:VPMINUD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPMINUD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpminud_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3794,7 +3794,7 @@ define pcodeop vpminud_avx512vl ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75457 define pcodeop vpminud_avx512f ; -:VPMINUD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPMINUD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpminud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3805,7 +3805,7 @@ define pcodeop vpminud_avx512f ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75460 define pcodeop vpminuq_avx512vl ; -:VPMINUQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMINUQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpminuq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3815,7 +3815,7 @@ define pcodeop vpminuq_avx512vl ; } # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75463 -:VPMINUQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMINUQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpminuq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3826,7 +3826,7 @@ define pcodeop vpminuq_avx512vl ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75466 define pcodeop vpminuq_avx512f ; -:VPMINUQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMINUQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpminuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3837,7 +3837,7 @@ define pcodeop vpminuq_avx512f ; # PMOVSX 4-340 PAGE 1460 LINE 75796 define pcodeop vpmovsxbw_avx512vl ; -:VPMOVSXBW XmmReg1 XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64 +:VPMOVSXBW XmmReg1^XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovsxbw_avx512vl( XmmReg2_m64 ); @@ -3847,7 +3847,7 @@ define pcodeop vpmovsxbw_avx512vl ; } # PMOVSX 4-340 PAGE 1460 LINE 75799 -:VPMOVSXBW YmmReg1 YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 +:VPMOVSXBW YmmReg1^YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovsxbw_avx512vl( XmmReg2_m128 ); @@ -3858,7 +3858,7 @@ define pcodeop vpmovsxbw_avx512vl ; # PMOVSX 4-340 PAGE 1460 LINE 75802 define pcodeop vpmovsxbw_avx512bw ; -:VPMOVSXBW ZmmReg1 ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256 +:VPMOVSXBW ZmmReg1^ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x20; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovsxbw_avx512bw( YmmReg2_m256 ); @@ -3869,7 +3869,7 @@ define pcodeop vpmovsxbw_avx512bw ; # PMOVSX 4-340 PAGE 1460 LINE 75805 define pcodeop vpmovsxbd_avx512vl ; -:VPMOVSXBD XmmReg1 XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VPMOVSXBD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovsxbd_avx512vl( XmmReg2_m32 ); @@ -3879,7 +3879,7 @@ define pcodeop vpmovsxbd_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75819 -:VPMOVSXBD YmmReg1 YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 +:VPMOVSXBD YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovsxbd_avx512vl( XmmReg2_m64 ); @@ -3890,7 +3890,7 @@ define pcodeop vpmovsxbd_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75822 define pcodeop vpmovsxbd_avx512f ; -:VPMOVSXBD ZmmReg1 ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 +:VPMOVSXBD ZmmReg1^ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x21; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovsxbd_avx512f( XmmReg2_m128 ); @@ -3901,7 +3901,7 @@ define pcodeop vpmovsxbd_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75825 define pcodeop vpmovsxbq_avx512vl ; -:VPMOVSXBQ XmmReg1 XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16 +:VPMOVSXBQ XmmReg1^XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovsxbq_avx512vl( XmmReg2_m16 ); @@ -3911,7 +3911,7 @@ define pcodeop vpmovsxbq_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75828 -:VPMOVSXBQ YmmReg1 YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32 +:VPMOVSXBQ YmmReg1^YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovsxbq_avx512vl( XmmReg2_m32 ); @@ -3922,7 +3922,7 @@ define pcodeop vpmovsxbq_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75831 define pcodeop vpmovsxbq_avx512f ; -:VPMOVSXBQ ZmmReg1 ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 +:VPMOVSXBQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x22; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovsxbq_avx512f( XmmReg2_m64 ); @@ -3933,7 +3933,7 @@ define pcodeop vpmovsxbq_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75834 define pcodeop vpmovsxwd_avx512vl ; -:VPMOVSXWD XmmReg1 XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 +:VPMOVSXWD XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovsxwd_avx512vl( XmmReg2_m64 ); @@ -3943,7 +3943,7 @@ define pcodeop vpmovsxwd_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75837 -:VPMOVSXWD YmmReg1 YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 +:VPMOVSXWD YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovsxwd_avx512vl( XmmReg2_m128 ); @@ -3954,7 +3954,7 @@ define pcodeop vpmovsxwd_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75840 define pcodeop vpmovsxwd_avx512f ; -:VPMOVSXWD ZmmReg1 ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256 +:VPMOVSXWD ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovsxwd_avx512f( YmmReg2_m256 ); @@ -3965,7 +3965,7 @@ define pcodeop vpmovsxwd_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75843 define pcodeop vpmovsxwq_avx512vl ; -:VPMOVSXWQ XmmReg1 XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32 +:VPMOVSXWQ XmmReg1^XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovsxwq_avx512vl( XmmReg2_m32 ); @@ -3975,7 +3975,7 @@ define pcodeop vpmovsxwq_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75846 -:VPMOVSXWQ YmmReg1 YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 +:VPMOVSXWQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovsxwq_avx512vl( XmmReg2_m64 ); @@ -3986,7 +3986,7 @@ define pcodeop vpmovsxwq_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75849 define pcodeop vpmovsxwq_avx512f ; -:VPMOVSXWQ ZmmReg1 ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 +:VPMOVSXWQ ZmmReg1^ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x24; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovsxwq_avx512f( XmmReg2_m128 ); @@ -3997,7 +3997,7 @@ define pcodeop vpmovsxwq_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75852 define pcodeop vpmovsxdq_avx512vl ; -:VPMOVSXDQ XmmReg1 XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VPMOVSXDQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovsxdq_avx512vl( XmmReg2_m64 ); @@ -4007,7 +4007,7 @@ define pcodeop vpmovsxdq_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75855 -:VPMOVSXDQ YmmReg1 YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 +:VPMOVSXDQ YmmReg1^YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovsxdq_avx512vl( XmmReg2_m128 ); @@ -4018,7 +4018,7 @@ define pcodeop vpmovsxdq_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75858 define pcodeop vpmovsxdq_avx512f ; -:VPMOVSXDQ ZmmReg1 ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256 +:VPMOVSXDQ ZmmReg1^ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovsxdq_avx512f( YmmReg2_m256 ); @@ -4029,7 +4029,7 @@ define pcodeop vpmovsxdq_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76329 define pcodeop vpmovzxbw_avx512vl ; -:VPMOVZXBW XmmReg1 XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64 +:VPMOVZXBW XmmReg1^XmmOpMask16, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovzxbw_avx512vl( XmmReg2_m64 ); @@ -4039,7 +4039,7 @@ define pcodeop vpmovzxbw_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76332 -:VPMOVZXBW YmmReg1 YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 +:VPMOVZXBW YmmReg1^YmmOpMask16, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovzxbw_avx512vl( XmmReg2_m128 ); @@ -4050,7 +4050,7 @@ define pcodeop vpmovzxbw_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76335 define pcodeop vpmovzxbw_avx512bw ; -:VPMOVZXBW ZmmReg1 ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256 +:VPMOVZXBW ZmmReg1^ZmmOpMask16, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x30; (ZmmReg1 & ZmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovzxbw_avx512bw( YmmReg2_m256 ); @@ -4061,7 +4061,7 @@ define pcodeop vpmovzxbw_avx512bw ; # PMOVZX 4-351 PAGE 1471 LINE 76338 define pcodeop vpmovzxbd_avx512vl ; -:VPMOVZXBD XmmReg1 XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VPMOVZXBD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovzxbd_avx512vl( XmmReg2_m32 ); @@ -4071,7 +4071,7 @@ define pcodeop vpmovzxbd_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76341 -:VPMOVZXBD YmmReg1 YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 +:VPMOVZXBD YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovzxbd_avx512vl( XmmReg2_m64 ); @@ -4082,7 +4082,7 @@ define pcodeop vpmovzxbd_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76344 define pcodeop vpmovzxbd_avx512f ; -:VPMOVZXBD ZmmReg1 ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 +:VPMOVZXBD ZmmReg1^ZmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x31; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovzxbd_avx512f( XmmReg2_m128 ); @@ -4093,7 +4093,7 @@ define pcodeop vpmovzxbd_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76347 define pcodeop vpmovzxbq_avx512vl ; -:VPMOVZXBQ XmmReg1 XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16 +:VPMOVZXBQ XmmReg1^XmmOpMask64, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovzxbq_avx512vl( XmmReg2_m16 ); @@ -4103,7 +4103,7 @@ define pcodeop vpmovzxbq_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76350 -:VPMOVZXBQ YmmReg1 YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32 +:VPMOVZXBQ YmmReg1^YmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovzxbq_avx512vl( XmmReg2_m32 ); @@ -4114,7 +4114,7 @@ define pcodeop vpmovzxbq_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76353 define pcodeop vpmovzxbq_avx512f ; -:VPMOVZXBQ ZmmReg1 ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 +:VPMOVZXBQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x32; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovzxbq_avx512f( XmmReg2_m64 ); @@ -4125,7 +4125,7 @@ define pcodeop vpmovzxbq_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76356 define pcodeop vpmovzxwd_avx512vl ; -:VPMOVZXWD XmmReg1 XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 +:VPMOVZXWD XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovzxwd_avx512vl( XmmReg2_m64 ); @@ -4135,7 +4135,7 @@ define pcodeop vpmovzxwd_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76359 -:VPMOVZXWD YmmReg1 YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 +:VPMOVZXWD YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovzxwd_avx512vl( XmmReg2_m128 ); @@ -4146,7 +4146,7 @@ define pcodeop vpmovzxwd_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76362 define pcodeop vpmovzxwd_avx512f ; -:VPMOVZXWD ZmmReg1 ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256 +:VPMOVZXWD ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x33; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovzxwd_avx512f( YmmReg2_m256 ); @@ -4157,7 +4157,7 @@ define pcodeop vpmovzxwd_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76365 define pcodeop vpmovzxwq_avx512vl ; -:VPMOVZXWQ XmmReg1 XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32 +:VPMOVZXWQ XmmReg1^XmmOpMask64, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovzxwq_avx512vl( XmmReg2_m32 ); @@ -4167,7 +4167,7 @@ define pcodeop vpmovzxwq_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76368 -:VPMOVZXWQ YmmReg1 YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 +:VPMOVZXWQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovzxwq_avx512vl( XmmReg2_m64 ); @@ -4178,7 +4178,7 @@ define pcodeop vpmovzxwq_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76371 define pcodeop vpmovzxwq_avx512f ; -:VPMOVZXWQ ZmmReg1 ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 +:VPMOVZXWQ ZmmReg1^ZmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) ; byte=0x34; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovzxwq_avx512f( XmmReg2_m128 ); @@ -4189,7 +4189,7 @@ define pcodeop vpmovzxwq_avx512f ; # PMOVZX 4-352 PAGE 1472 LINE 76386 define pcodeop vpmovzxdq_avx512vl ; -:VPMOVZXDQ XmmReg1 XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VPMOVZXDQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { XmmResult = vpmovzxdq_avx512vl( XmmReg2_m64 ); @@ -4199,7 +4199,7 @@ define pcodeop vpmovzxdq_avx512vl ; } # PMOVZX 4-352 PAGE 1472 LINE 76389 -:VPMOVZXDQ YmmReg1 YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 +:VPMOVZXDQ YmmReg1^YmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { YmmResult = vpmovzxdq_avx512vl( XmmReg2_m128 ); @@ -4210,7 +4210,7 @@ define pcodeop vpmovzxdq_avx512vl ; # PMOVZX 4-352 PAGE 1472 LINE 76392 define pcodeop vpmovzxdq_avx512f ; -:VPMOVZXDQ ZmmReg1 ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256 +:VPMOVZXDQ ZmmReg1^ZmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x35; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmResult = vpmovzxdq_avx512f( YmmReg2_m256 ); @@ -4221,7 +4221,7 @@ define pcodeop vpmovzxdq_avx512f ; # PMULDQ 4-359 PAGE 1479 LINE 76794 define pcodeop vpmuldq_avx512vl ; -:VPMULDQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMULDQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmuldq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4231,7 +4231,7 @@ define pcodeop vpmuldq_avx512vl ; } # PMULDQ 4-359 PAGE 1479 LINE 76798 -:VPMULDQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMULDQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmuldq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4242,7 +4242,7 @@ define pcodeop vpmuldq_avx512vl ; # PMULDQ 4-359 PAGE 1479 LINE 76802 define pcodeop vpmuldq_avx512f ; -:VPMULDQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMULDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x28; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmuldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4253,7 +4253,7 @@ define pcodeop vpmuldq_avx512f ; # PMULHRSW 4-362 PAGE 1482 LINE 76934 define pcodeop vpmulhrsw_avx512vl ; -:VPMULHRSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMULHRSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmulhrsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4263,7 +4263,7 @@ define pcodeop vpmulhrsw_avx512vl ; } # PMULHRSW 4-362 PAGE 1482 LINE 76937 -:VPMULHRSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMULHRSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmulhrsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4274,7 +4274,7 @@ define pcodeop vpmulhrsw_avx512vl ; # PMULHRSW 4-362 PAGE 1482 LINE 76940 define pcodeop vpmulhrsw_avx512bw ; -:VPMULHRSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0B; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMULHRSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x0B; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmulhrsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4285,7 +4285,7 @@ define pcodeop vpmulhrsw_avx512bw ; # PMULHUW 4-366 PAGE 1486 LINE 77147 define pcodeop vpmulhuw_avx512vl ; -:VPMULHUW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMULHUW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmulhuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4295,7 +4295,7 @@ define pcodeop vpmulhuw_avx512vl ; } # PMULHUW 4-366 PAGE 1486 LINE 77151 -:VPMULHUW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMULHUW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmulhuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4306,7 +4306,7 @@ define pcodeop vpmulhuw_avx512vl ; # PMULHUW 4-366 PAGE 1486 LINE 77155 define pcodeop vpmulhuw_avx512bw ; -:VPMULHUW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE4; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMULHUW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE4; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmulhuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4317,7 +4317,7 @@ define pcodeop vpmulhuw_avx512bw ; # PMULHW 4-370 PAGE 1490 LINE 77376 define pcodeop vpmulhw_avx512vl ; -:VPMULHW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMULHW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmulhw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4327,7 +4327,7 @@ define pcodeop vpmulhw_avx512vl ; } # PMULHW 4-370 PAGE 1490 LINE 77379 -:VPMULHW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMULHW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmulhw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4338,7 +4338,7 @@ define pcodeop vpmulhw_avx512vl ; # PMULHW 4-370 PAGE 1490 LINE 77382 define pcodeop vpmulhw_avx512bw ; -:VPMULHW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMULHW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmulhw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4349,7 +4349,7 @@ define pcodeop vpmulhw_avx512bw ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77582 define pcodeop vpmulld_avx512vl ; -:VPMULLD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPMULLD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmulld_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -4359,7 +4359,7 @@ define pcodeop vpmulld_avx512vl ; } # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77585 -:VPMULLD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPMULLD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmulld_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -4370,7 +4370,7 @@ define pcodeop vpmulld_avx512vl ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77588 define pcodeop vpmulld_avx512f ; -:VPMULLD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPMULLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmulld_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -4381,7 +4381,7 @@ define pcodeop vpmulld_avx512f ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77591 define pcodeop vpmullq_avx512vl ; -:VPMULLQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMULLQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmullq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4391,7 +4391,7 @@ define pcodeop vpmullq_avx512vl ; } # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77594 -:VPMULLQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMULLQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmullq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4402,7 +4402,7 @@ define pcodeop vpmullq_avx512vl ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77597 define pcodeop vpmullq_avx512dq ; -:VPMULLQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMULLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x40; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmullq_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4413,7 +4413,7 @@ define pcodeop vpmullq_avx512dq ; # PMULLW 4-378 PAGE 1498 LINE 77781 define pcodeop vpmullw_avx512vl ; -:VPMULLW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPMULLW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpmullw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4423,7 +4423,7 @@ define pcodeop vpmullw_avx512vl ; } # PMULLW 4-378 PAGE 1498 LINE 77784 -:VPMULLW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPMULLW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpmullw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4434,7 +4434,7 @@ define pcodeop vpmullw_avx512vl ; # PMULLW 4-378 PAGE 1498 LINE 77787 define pcodeop vpmullw_avx512bw ; -:VPMULLW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPMULLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD5; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpmullw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4445,7 +4445,7 @@ define pcodeop vpmullw_avx512bw ; # PMULUDQ 4-382 PAGE 1502 LINE 77977 define pcodeop vpmuludq_avx512vl ; -:VPMULUDQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPMULUDQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpmuludq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4455,7 +4455,7 @@ define pcodeop vpmuludq_avx512vl ; } # PMULUDQ 4-382 PAGE 1502 LINE 77981 -:VPMULUDQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPMULUDQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpmuludq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4466,7 +4466,7 @@ define pcodeop vpmuludq_avx512vl ; # PMULUDQ 4-382 PAGE 1502 LINE 77985 define pcodeop vpmuludq_avx512f ; -:VPMULUDQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPMULUDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpmuludq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4477,7 +4477,7 @@ define pcodeop vpmuludq_avx512f ; # POR 4-399 PAGE 1519 LINE 78854 define pcodeop vpord_avx512vl ; -:VPORD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPORD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpord_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -4487,7 +4487,7 @@ define pcodeop vpord_avx512vl ; } # POR 4-399 PAGE 1519 LINE 78857 -:VPORD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPORD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpord_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -4498,7 +4498,7 @@ define pcodeop vpord_avx512vl ; # POR 4-399 PAGE 1519 LINE 78860 define pcodeop vpord_avx512f ; -:VPORD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -4509,7 +4509,7 @@ define pcodeop vpord_avx512f ; # POR 4-399 PAGE 1519 LINE 78863 define pcodeop vporq_avx512vl ; -:VPORQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPORQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vporq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4519,7 +4519,7 @@ define pcodeop vporq_avx512vl ; } # POR 4-399 PAGE 1519 LINE 78866 -:VPORQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPORQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vporq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4530,7 +4530,7 @@ define pcodeop vporq_avx512vl ; # POR 4-399 PAGE 1519 LINE 78869 define pcodeop vporq_avx512f ; -:VPORQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vporq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4569,7 +4569,7 @@ define pcodeop vpsadbw_avx512bw ; # PSHUFB 4-412 PAGE 1532 LINE 79466 define pcodeop vpshufb_avx512vl ; -:VPSHUFB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPSHUFB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpshufb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4579,7 +4579,7 @@ define pcodeop vpshufb_avx512vl ; } # PSHUFB 4-412 PAGE 1532 LINE 79468 -:VPSHUFB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPSHUFB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpshufb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4590,7 +4590,7 @@ define pcodeop vpshufb_avx512vl ; # PSHUFB 4-412 PAGE 1532 LINE 79470 define pcodeop vpshufb_avx512bw ; -:VPSHUFB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x00; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPSHUFB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x00; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpshufb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4601,7 +4601,7 @@ define pcodeop vpshufb_avx512bw ; # PSHUFD 4-416 PAGE 1536 LINE 79656 define pcodeop vpshufd_avx512vl ; -:VPSHUFD XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VPSHUFD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpshufd_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -4611,7 +4611,7 @@ define pcodeop vpshufd_avx512vl ; } # PSHUFD 4-416 PAGE 1536 LINE 79659 -:VPSHUFD YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VPSHUFD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpshufd_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -4622,7 +4622,7 @@ define pcodeop vpshufd_avx512vl ; # PSHUFD 4-416 PAGE 1536 LINE 79662 define pcodeop vpshufd_avx512f ; -:VPSHUFD ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VPSHUFD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x70; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpshufd_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -4633,7 +4633,7 @@ define pcodeop vpshufd_avx512f ; # PSHUFHW 4-420 PAGE 1540 LINE 79863 define pcodeop vpshufhw_avx512vl ; -:VPSHUFHW XmmReg1 XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8 +:VPSHUFHW XmmReg1^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpshufhw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4643,7 +4643,7 @@ define pcodeop vpshufhw_avx512vl ; } # PSHUFHW 4-420 PAGE 1540 LINE 79866 -:VPSHUFHW YmmReg1 YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8 +:VPSHUFHW YmmReg1^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpshufhw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4654,7 +4654,7 @@ define pcodeop vpshufhw_avx512vl ; # PSHUFHW 4-420 PAGE 1540 LINE 79869 define pcodeop vpshufhw_avx512bw ; -:VPSHUFHW ZmmReg1 ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8 +:VPSHUFHW ZmmReg1^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpshufhw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4665,7 +4665,7 @@ define pcodeop vpshufhw_avx512bw ; # PSHUFLW 4-423 PAGE 1543 LINE 80038 define pcodeop vpshuflw_avx512vl ; -:VPSHUFLW XmmReg1 XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8 +:VPSHUFLW XmmReg1^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpshuflw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4675,7 +4675,7 @@ define pcodeop vpshuflw_avx512vl ; } # PSHUFLW 4-423 PAGE 1543 LINE 80041 -:VPSHUFLW YmmReg1 YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8 +:VPSHUFLW YmmReg1^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpshuflw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4686,7 +4686,7 @@ define pcodeop vpshuflw_avx512vl ; # PSHUFLW 4-423 PAGE 1543 LINE 80044 define pcodeop vpshuflw_avx512bw ; -:VPSHUFLW ZmmReg1 ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8 +:VPSHUFLW ZmmReg1^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) ; byte=0x70; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpshuflw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4722,7 +4722,7 @@ define pcodeop vpslldq_avx512bw ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80667 define pcodeop vpsllw_avx512vl ; -:VPSLLW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSLLW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsllw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4732,7 +4732,7 @@ define pcodeop vpsllw_avx512vl ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80670 -:VPSLLW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 +:VPSLLW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsllw_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4743,7 +4743,7 @@ define pcodeop vpsllw_avx512vl ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80673 define pcodeop vpsllw_avx512bw ; -:VPSLLW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128 +:VPSLLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsllw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 ); @@ -4753,7 +4753,7 @@ define pcodeop vpsllw_avx512bw ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80676 -:VPSLLW vexVVVV_XmmReg XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=6 ... & XmmReg2_m128; imm8 +:VPSLLW vexVVVV_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=6 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { XmmResult = vpsllw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4763,7 +4763,7 @@ define pcodeop vpsllw_avx512bw ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80678 -:VPSLLW vexVVVV_YmmReg YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=6 ... & YmmReg2_m256; imm8 +:VPSLLW vexVVVV_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=6 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { YmmResult = vpsllw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4773,7 +4773,7 @@ define pcodeop vpsllw_avx512bw ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80680 -:VPSLLW evexV5_ZmmReg ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=6 ... & ZmmReg2_m512; imm8 +:VPSLLW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=6 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { ZmmResult = vpsllw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4784,7 +4784,7 @@ define pcodeop vpsllw_avx512bw ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80682 define pcodeop vpslld_avx512vl ; -:VPSLLD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VPSLLD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpslld_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4794,7 +4794,7 @@ define pcodeop vpslld_avx512vl ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80685 -:VPSLLD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 +:VPSLLD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpslld_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4805,7 +4805,7 @@ define pcodeop vpslld_avx512vl ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80688 define pcodeop vpslld_avx512f ; -:VPSLLD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xF2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 +:VPSLLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xF2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpslld_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); @@ -4815,7 +4815,7 @@ define pcodeop vpslld_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80691 -:VPSLLD vexVVVV_XmmReg XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=6 ... & XmmReg2_m128_m32bcst; imm8 +:VPSLLD vexVVVV_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=6 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vpslld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -4825,7 +4825,7 @@ define pcodeop vpslld_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80694 -:VPSLLD vexVVVV_YmmReg YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=6 ... & YmmReg2_m256_m32bcst; imm8 +:VPSLLD vexVVVV_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=6 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vpslld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -4835,7 +4835,7 @@ define pcodeop vpslld_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80697 -:VPSLLD evexV5_ZmmReg ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=6 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSLLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=6 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vpslld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -4846,7 +4846,7 @@ define pcodeop vpslld_avx512f ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80700 define pcodeop vpsllq_avx512vl ; -:VPSLLQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VPSLLQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsllq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4856,7 +4856,7 @@ define pcodeop vpsllq_avx512vl ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80703 -:VPSLLQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 +:VPSLLQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsllq_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4867,7 +4867,7 @@ define pcodeop vpsllq_avx512vl ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80706 define pcodeop vpsllq_avx512f ; -:VPSLLQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 +:VPSLLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xF3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsllq_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); @@ -4877,7 +4877,7 @@ define pcodeop vpsllq_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80721 -:VPSLLQ vexVVVV_XmmReg XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=6 ... & XmmReg2_m128_m64bcst; imm8 +:VPSLLQ vexVVVV_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=6 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vpsllq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -4887,7 +4887,7 @@ define pcodeop vpsllq_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80724 -:VPSLLQ vexVVVV_YmmReg YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=6 ... & YmmReg2_m256_m64bcst; imm8 +:VPSLLQ vexVVVV_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=6 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vpsllq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -4897,7 +4897,7 @@ define pcodeop vpsllq_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80727 -:VPSLLQ evexV5_ZmmReg ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=6 ... & ZmmReg2_m512_m64bcst; imm8 +:VPSLLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=6 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vpsllq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -4908,7 +4908,7 @@ define pcodeop vpsllq_avx512f ; # PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81329 define pcodeop vpsraw_avx512vl ; -:VPSRAW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSRAW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsraw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4918,7 +4918,7 @@ define pcodeop vpsraw_avx512vl ; } # PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81332 -:VPSRAW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 +:VPSRAW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsraw_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4929,7 +4929,7 @@ define pcodeop vpsraw_avx512vl ; # PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81335 define pcodeop vpsraw_avx512bw ; -:VPSRAW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128 +:VPSRAW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsraw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 ); @@ -4939,7 +4939,7 @@ define pcodeop vpsraw_avx512bw ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81350 -:VPSRAW vexVVVV_XmmReg XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=4 ... & XmmReg2_m128; imm8 +:VPSRAW vexVVVV_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=4 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { XmmResult = vpsraw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4949,7 +4949,7 @@ define pcodeop vpsraw_avx512bw ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81352 -:VPSRAW vexVVVV_YmmReg YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=4 ... & YmmReg2_m256; imm8 +:VPSRAW vexVVVV_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=4 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { YmmResult = vpsraw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4959,7 +4959,7 @@ define pcodeop vpsraw_avx512bw ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81354 -:VPSRAW evexV5_ZmmReg ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=4 ... & ZmmReg2_m512; imm8 +:VPSRAW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=4 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { ZmmResult = vpsraw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4970,7 +4970,7 @@ define pcodeop vpsraw_avx512bw ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81356 define pcodeop vpsrad_avx512vl ; -:VPSRAD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VPSRAD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsrad_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4980,7 +4980,7 @@ define pcodeop vpsrad_avx512vl ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81359 -:VPSRAD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 +:VPSRAD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsrad_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4991,7 +4991,7 @@ define pcodeop vpsrad_avx512vl ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81362 define pcodeop vpsrad_avx512f ; -:VPSRAD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 +:VPSRAD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsrad_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); @@ -5001,7 +5001,7 @@ define pcodeop vpsrad_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81365 -:VPSRAD vexVVVV_XmmReg XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m32bcst; imm8 +:VPSRAD vexVVVV_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vpsrad_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -5011,7 +5011,7 @@ define pcodeop vpsrad_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81368 -:VPSRAD vexVVVV_YmmReg YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m32bcst; imm8 +:VPSRAD vexVVVV_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vpsrad_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -5022,7 +5022,7 @@ define pcodeop vpsrad_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81371 -:VPSRAD evexV5_ZmmReg ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSRAD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vpsrad_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -5033,7 +5033,7 @@ define pcodeop vpsrad_avx512f ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81374 define pcodeop vpsraq_avx512vl ; -:VPSRAQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VPSRAQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsraq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5043,7 +5043,7 @@ define pcodeop vpsraq_avx512vl ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81377 -:VPSRAQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 +:VPSRAQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsraq_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -5054,7 +5054,7 @@ define pcodeop vpsraq_avx512vl ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81380 define pcodeop vpsraq_avx512f ; -:VPSRAQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 +:VPSRAQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xE2; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsraq_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); @@ -5064,7 +5064,7 @@ define pcodeop vpsraq_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81383 -:VPSRAQ vexVVVV_XmmReg XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m64bcst; imm8 +:VPSRAQ vexVVVV_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vpsraq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -5074,7 +5074,7 @@ define pcodeop vpsraq_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81386 -:VPSRAQ vexVVVV_YmmReg YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m64bcst; imm8 +:VPSRAQ vexVVVV_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vpsraq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -5084,7 +5084,7 @@ define pcodeop vpsraq_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81389 -:VPSRAQ evexV5_ZmmReg ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m64bcst; imm8 +:VPSRAQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vpsraq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -5120,7 +5120,7 @@ define pcodeop vpsrldq_avx512bw ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82059 define pcodeop vpsrlw_avx512vl ; -:VPSRLW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSRLW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsrlw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5130,7 +5130,7 @@ define pcodeop vpsrlw_avx512vl ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82062 -:VPSRLW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 +:VPSRLW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsrlw_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -5141,7 +5141,7 @@ define pcodeop vpsrlw_avx512vl ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82065 define pcodeop vpsrlw_avx512bw ; -:VPSRLW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128 +:VPSRLW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD1; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsrlw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 ); @@ -5151,7 +5151,7 @@ define pcodeop vpsrlw_avx512bw ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82068 -:VPSRLW vexVVVV_XmmReg XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=2 ... & XmmReg2_m128; imm8 +:VPSRLW vexVVVV_XmmReg^XmmOpMask16, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask16; byte=0x71; reg_opcode=2 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsrlw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -5161,7 +5161,7 @@ define pcodeop vpsrlw_avx512bw ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82070 -:VPSRLW vexVVVV_YmmReg YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=2 ... & YmmReg2_m256; imm8 +:VPSRLW vexVVVV_YmmReg^YmmOpMask16, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask16; byte=0x71; reg_opcode=2 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsrlw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -5171,7 +5171,7 @@ define pcodeop vpsrlw_avx512bw ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82072 -:VPSRLW evexV5_ZmmReg ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=2 ... & ZmmReg2_m512; imm8 +:VPSRLW evexV5_ZmmReg^ZmmOpMask16, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & ZmmOpMask16; byte=0x71; reg_opcode=2 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsrlw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -5182,7 +5182,7 @@ define pcodeop vpsrlw_avx512bw ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82074 define pcodeop vpsrld_avx512vl ; -:VPSRLD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VPSRLD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsrld_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5192,7 +5192,7 @@ define pcodeop vpsrld_avx512vl ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82077 -:VPSRLD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 +:VPSRLD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsrld_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -5203,7 +5203,7 @@ define pcodeop vpsrld_avx512vl ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82080 define pcodeop vpsrld_avx512f ; -:VPSRLD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xD2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 +:VPSRLD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xD2; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsrld_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); @@ -5213,7 +5213,7 @@ define pcodeop vpsrld_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82084 -:VPSRLD vexVVVV_XmmReg XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=2 ... & XmmReg2_m128_m32bcst; imm8 +:VPSRLD vexVVVV_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=2 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vpsrld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -5223,7 +5223,7 @@ define pcodeop vpsrld_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82088 -:VPSRLD vexVVVV_YmmReg YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=2 ... & YmmReg2_m256_m32bcst; imm8 +:VPSRLD vexVVVV_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=2 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vpsrld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -5233,7 +5233,7 @@ define pcodeop vpsrld_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82091 -:VPSRLD evexV5_ZmmReg ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=2 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSRLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=2 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vpsrld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -5244,7 +5244,7 @@ define pcodeop vpsrld_avx512f ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82094 define pcodeop vpsrlq_avx512vl ; -:VPSRLQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VPSRLQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { XmmResult = vpsrlq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5254,7 +5254,7 @@ define pcodeop vpsrlq_avx512vl ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82097 -:VPSRLQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 +:VPSRLQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { YmmResult = vpsrlq_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -5265,7 +5265,7 @@ define pcodeop vpsrlq_avx512vl ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82100 define pcodeop vpsrlq_avx512f ; -:VPSRLQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 +:VPSRLQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xD3; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmResult = vpsrlq_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); @@ -5275,7 +5275,7 @@ define pcodeop vpsrlq_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82115 -:VPSRLQ vexVVVV_XmmReg XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=2 ... & XmmReg2_m128_m64bcst; imm8 +:VPSRLQ vexVVVV_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x73; reg_opcode=2 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vpsrlq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -5285,7 +5285,7 @@ define pcodeop vpsrlq_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82119 -:VPSRLQ vexVVVV_YmmReg YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=2 ... & YmmReg2_m256_m64bcst; imm8 +:VPSRLQ vexVVVV_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x73; reg_opcode=2 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vpsrlq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -5295,7 +5295,7 @@ define pcodeop vpsrlq_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82122 -:VPSRLQ evexV5_ZmmReg ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=2 ... & ZmmReg2_m512_m64bcst; imm8 +:VPSRLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x73; reg_opcode=2 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vpsrlq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -5306,7 +5306,7 @@ define pcodeop vpsrlq_avx512f ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82702 define pcodeop vpsubb_avx512vl ; -:VPSUBB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPSUBB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsubb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5316,7 +5316,7 @@ define pcodeop vpsubb_avx512vl ; } # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82705 -:VPSUBB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPSUBB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsubb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5327,7 +5327,7 @@ define pcodeop vpsubb_avx512vl ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82708 define pcodeop vpsubb_avx512bw ; -:VPSUBB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPSUBB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsubb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5338,7 +5338,7 @@ define pcodeop vpsubb_avx512bw ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82711 define pcodeop vpsubw_avx512vl ; -:VPSUBW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSUBW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsubw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5348,7 +5348,7 @@ define pcodeop vpsubw_avx512vl ; } # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82714 -:VPSUBW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPSUBW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsubw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5359,7 +5359,7 @@ define pcodeop vpsubw_avx512vl ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82717 define pcodeop vpsubw_avx512bw ; -:VPSUBW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPSUBW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xF9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsubw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5370,7 +5370,7 @@ define pcodeop vpsubw_avx512bw ; # PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82733 define pcodeop vpsubd_avx512vl ; -:VPSUBD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPSUBD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsubd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5380,7 +5380,7 @@ define pcodeop vpsubd_avx512vl ; } # PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82736 -:VPSUBD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPSUBD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsubd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5391,7 +5391,7 @@ define pcodeop vpsubd_avx512vl ; # PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82743 define pcodeop vpsubd_avx512f ; -:VPSUBD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPSUBD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xFA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsubd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5402,7 +5402,7 @@ define pcodeop vpsubd_avx512f ; # PSUBQ 4-476 PAGE 1596 LINE 83111 define pcodeop vpsubq_avx512vl ; -:VPSUBQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPSUBQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsubq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5412,7 +5412,7 @@ define pcodeop vpsubq_avx512vl ; } # PSUBQ 4-476 PAGE 1596 LINE 83114 -:VPSUBQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPSUBQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsubq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5423,7 +5423,7 @@ define pcodeop vpsubq_avx512vl ; # PSUBQ 4-476 PAGE 1596 LINE 83117 define pcodeop vpsubq_avx512f ; -:VPSUBQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xFB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPSUBQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xFB; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsubq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5434,7 +5434,7 @@ define pcodeop vpsubq_avx512f ; # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83270 define pcodeop vpsubsb_avx512vl ; -:VPSUBSB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPSUBSB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsubsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5444,7 +5444,7 @@ define pcodeop vpsubsb_avx512vl ; } # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83274 -:VPSUBSB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPSUBSB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsubsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5455,7 +5455,7 @@ define pcodeop vpsubsb_avx512vl ; # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83278 define pcodeop vpsubsb_avx512bw ; -:VPSUBSB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPSUBSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsubsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5466,7 +5466,7 @@ define pcodeop vpsubsb_avx512bw ; # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83282 define pcodeop vpsubsw_avx512vl ; -:VPSUBSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSUBSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsubsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5476,7 +5476,7 @@ define pcodeop vpsubsw_avx512vl ; } # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83286 -:VPSUBSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPSUBSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsubsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5487,7 +5487,7 @@ define pcodeop vpsubsw_avx512vl ; # PSUBSB/PSUBSW 4-480 PAGE 1600 LINE 83302 define pcodeop psubsw_avx512bw ; -:PSUBSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:PSUBSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xE9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 { ZmmReg1 = psubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); build ZmmOpMask16; @@ -5496,7 +5496,7 @@ define pcodeop psubsw_avx512bw ; # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83510 define pcodeop vpsubusb_avx512vl ; -:VPSUBUSB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPSUBUSB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsubusb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5506,7 +5506,7 @@ define pcodeop vpsubusb_avx512vl ; } # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83514 -:VPSUBUSB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPSUBUSB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsubusb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5517,7 +5517,7 @@ define pcodeop vpsubusb_avx512vl ; # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83518 define pcodeop vpsubusb_avx512bw ; -:VPSUBUSB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPSUBUSB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD8; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsubusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5528,7 +5528,7 @@ define pcodeop vpsubusb_avx512bw ; # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83522 define pcodeop vpsubusw_avx512vl ; -:VPSUBUSW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSUBUSW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsubusw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5538,7 +5538,7 @@ define pcodeop vpsubusw_avx512vl ; } # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83526 -:VPSUBUSW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPSUBUSW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsubusw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5549,7 +5549,7 @@ define pcodeop vpsubusw_avx512vl ; # PSUBUSB/PSUBUSW 4-484 PAGE 1604 LINE 83543 define pcodeop vpsubusw_avx512bw ; -:VPSUBUSW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPSUBUSW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0xD9; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsubusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5560,7 +5560,7 @@ define pcodeop vpsubusw_avx512bw ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83948 define pcodeop vpunpckhbw_avx512vl ; -:VPUNPCKHBW XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPUNPCKHBW XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpunpckhbw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5571,7 +5571,7 @@ define pcodeop vpunpckhbw_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83952 define pcodeop vpunpckhwd_avx512vl ; -:VPUNPCKHWD XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPUNPCKHWD XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpunpckhwd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5582,7 +5582,7 @@ define pcodeop vpunpckhwd_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83955 define pcodeop vpunpckhdq_avx512vl ; -:VPUNPCKHDQ XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPUNPCKHDQ XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpunpckhdq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5593,7 +5593,7 @@ define pcodeop vpunpckhdq_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83958 define pcodeop vpunpckhqdq_avx512vl ; -:VPUNPCKHQDQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPUNPCKHQDQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpunpckhqdq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5603,7 +5603,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83974 -:VPUNPCKHBW YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPUNPCKHBW YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpunpckhbw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5613,7 +5613,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83977 -:VPUNPCKHWD YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPUNPCKHWD YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpunpckhwd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5623,7 +5623,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83980 -:VPUNPCKHDQ YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPUNPCKHDQ YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpunpckhdq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5633,7 +5633,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83984 -:VPUNPCKHQDQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPUNPCKHQDQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpunpckhqdq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5644,7 +5644,7 @@ define pcodeop vpunpckhqdq_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83988 define pcodeop vpunpckhbw_avx512bw ; -:VPUNPCKHBW ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x68; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPUNPCKHBW ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x68; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpunpckhbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5655,7 +5655,7 @@ define pcodeop vpunpckhbw_avx512bw ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83991 define pcodeop vpunpckhwd_avx512bw ; -:VPUNPCKHWD ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x69; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPUNPCKHWD ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x69; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpunpckhwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5666,7 +5666,7 @@ define pcodeop vpunpckhwd_avx512bw ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83994 define pcodeop vpunpckhdq_avx512f ; -:VPUNPCKHDQ ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPUNPCKHDQ ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x6A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpunpckhdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5677,7 +5677,7 @@ define pcodeop vpunpckhdq_avx512f ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83997 define pcodeop vpunpckhqdq_avx512f ; -:VPUNPCKHQDQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPUNPCKHQDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpunpckhqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5688,7 +5688,7 @@ define pcodeop vpunpckhqdq_avx512f ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84553 define pcodeop vpunpcklbw_avx512vl ; -:VPUNPCKLBW XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPUNPCKLBW XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpunpcklbw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5699,7 +5699,7 @@ define pcodeop vpunpcklbw_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84556 define pcodeop vpunpcklwd_avx512vl ; -:VPUNPCKLWD XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPUNPCKLWD XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpunpcklwd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -5710,7 +5710,7 @@ define pcodeop vpunpcklwd_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84559 define pcodeop vpunpckldq_avx512vl ; -:VPUNPCKLDQ XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPUNPCKLDQ XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpunpckldq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5721,7 +5721,7 @@ define pcodeop vpunpckldq_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84562 define pcodeop vpunpcklqdq_avx512vl ; -:VPUNPCKLQDQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPUNPCKLQDQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpunpcklqdq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5731,7 +5731,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84578 -:VPUNPCKLBW YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPUNPCKLBW YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpunpcklbw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5741,7 +5741,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84581 -:VPUNPCKLWD YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPUNPCKLWD YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpunpcklwd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -5751,7 +5751,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84584 -:VPUNPCKLDQ YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPUNPCKLDQ YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpunpckldq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5761,7 +5761,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84587 -:VPUNPCKLQDQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPUNPCKLQDQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpunpcklqdq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5772,7 +5772,7 @@ define pcodeop vpunpcklqdq_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84590 define pcodeop vpunpcklbw_avx512bw ; -:VPUNPCKLBW ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x60; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPUNPCKLBW ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x60; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpunpcklbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5783,7 +5783,7 @@ define pcodeop vpunpcklbw_avx512bw ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84593 define pcodeop vpunpcklwd_avx512bw ; -:VPUNPCKLWD ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x61; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPUNPCKLWD ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg; byte=0x61; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpunpcklwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -5794,7 +5794,7 @@ define pcodeop vpunpcklwd_avx512bw ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84596 define pcodeop vpunpckldq_avx512f ; -:VPUNPCKLDQ ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x62; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPUNPCKLDQ ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x62; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpunpckldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5805,7 +5805,7 @@ define pcodeop vpunpckldq_avx512f ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84599 define pcodeop vpunpcklqdq_avx512f ; -:VPUNPCKLQDQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPUNPCKLQDQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x6C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpunpcklqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5816,7 +5816,7 @@ define pcodeop vpunpcklqdq_avx512f ; # PXOR 4-518 PAGE 1638 LINE 85503 define pcodeop vpxord_avx512vl ; -:VPXORD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPXORD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpxord_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5826,7 +5826,7 @@ define pcodeop vpxord_avx512vl ; } # PXOR 4-518 PAGE 1638 LINE 85505 -:VPXORD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPXORD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpxord_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5837,7 +5837,7 @@ define pcodeop vpxord_avx512vl ; # PXOR 4-518 PAGE 1638 LINE 85507 define pcodeop vpxord_avx512f ; -:VPXORD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPXORD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpxord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5848,7 +5848,7 @@ define pcodeop vpxord_avx512f ; # PXOR 4-518 PAGE 1638 LINE 85514 define pcodeop vpxorq_avx512vl ; -:VPXORQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPXORQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpxorq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5858,7 +5858,7 @@ define pcodeop vpxorq_avx512vl ; } # PXOR 4-518 PAGE 1638 LINE 85521 -:VPXORQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPXORQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpxorq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5869,7 +5869,7 @@ define pcodeop vpxorq_avx512vl ; # PXOR 4-518 PAGE 1638 LINE 85523 define pcodeop vpxorq_avx512f ; -:VPXORQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPXORQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xEF; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpxorq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5880,7 +5880,7 @@ define pcodeop vpxorq_avx512f ; # SHUFPD 4-617 PAGE 1737 LINE 90231 define pcodeop vshufpd_avx512vl ; -:VSHUFPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VSHUFPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vshufpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -5890,7 +5890,7 @@ define pcodeop vshufpd_avx512vl ; } # SHUFPD 4-617 PAGE 1737 LINE 90235 -:VSHUFPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VSHUFPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vshufpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -5901,7 +5901,7 @@ define pcodeop vshufpd_avx512vl ; # SHUFPD 4-617 PAGE 1737 LINE 90239 define pcodeop vshufpd_avx512f ; -:VSHUFPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VSHUFPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vshufpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -5912,7 +5912,7 @@ define pcodeop vshufpd_avx512f ; # SHUFPS 4-622 PAGE 1742 LINE 90489 define pcodeop vshufps_avx512vl ; -:VSHUFPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VSHUFPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vshufps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -5922,7 +5922,7 @@ define pcodeop vshufps_avx512vl ; } # SHUFPS 4-622 PAGE 1742 LINE 90493 -:VSHUFPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VSHUFPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vshufps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -5933,7 +5933,7 @@ define pcodeop vshufps_avx512vl ; # SHUFPS 4-622 PAGE 1742 LINE 90497 define pcodeop vshufps_avx512f ; -:VSHUFPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VSHUFPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0xC6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vshufps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -5944,7 +5944,7 @@ define pcodeop vshufps_avx512f ; # SQRTPD 4-632 PAGE 1752 LINE 91007 define pcodeop vsqrtpd_avx512vl ; -:VSQRTPD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VSQRTPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vsqrtpd_avx512vl( XmmReg2_m128_m64bcst ); @@ -5954,7 +5954,7 @@ define pcodeop vsqrtpd_avx512vl ; } # SQRTPD 4-632 PAGE 1752 LINE 91010 -:VSQRTPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VSQRTPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vsqrtpd_avx512vl( YmmReg2_m256_m64bcst ); @@ -5965,7 +5965,7 @@ define pcodeop vsqrtpd_avx512vl ; # SQRTPD 4-632 PAGE 1752 LINE 91013 define pcodeop vsqrtpd_avx512f ; -:VSQRTPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VSQRTPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x51; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vsqrtpd_avx512f( ZmmReg2_m512_m64bcst ); @@ -5976,7 +5976,7 @@ define pcodeop vsqrtpd_avx512f ; # SQRTPS 4-635 PAGE 1755 LINE 91139 define pcodeop vsqrtps_avx512vl ; -:VSQRTPS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VSQRTPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vsqrtps_avx512vl( XmmReg2_m128_m32bcst ); @@ -5986,7 +5986,7 @@ define pcodeop vsqrtps_avx512vl ; } # SQRTPS 4-635 PAGE 1755 LINE 91142 -:VSQRTPS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VSQRTPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vsqrtps_avx512vl( YmmReg2_m256_m32bcst ); @@ -5997,7 +5997,7 @@ define pcodeop vsqrtps_avx512vl ; # SQRTPS 4-635 PAGE 1755 LINE 91145 define pcodeop vsqrtps_avx512f ; -:VSQRTPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VSQRTPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x51; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vsqrtps_avx512f( ZmmReg2_m512_m32bcst ); @@ -6008,7 +6008,7 @@ define pcodeop vsqrtps_avx512f ; # SQRTSD 4-638 PAGE 1758 LINE 91276 define pcodeop vsqrtsd_avx512f ; -:VSQRTSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VSQRTSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vsqrtsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -6019,7 +6019,7 @@ define pcodeop vsqrtsd_avx512f ; # SQRTSS 4-640 PAGE 1760 LINE 91371 define pcodeop vsqrtss_avx512f ; -:VSQRTSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VSQRTSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vsqrtss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -6030,7 +6030,7 @@ define pcodeop vsqrtss_avx512f ; # SUBPD 4-656 PAGE 1776 LINE 92120 define pcodeop vsubpd_avx512vl ; -:VSUBPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VSUBPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vsubpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6040,7 +6040,7 @@ define pcodeop vsubpd_avx512vl ; } # SUBPD 4-656 PAGE 1776 LINE 92123 -:VSUBPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VSUBPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vsubpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6051,7 +6051,7 @@ define pcodeop vsubpd_avx512vl ; # SUBPD 4-656 PAGE 1776 LINE 92126 define pcodeop vsubpd_avx512f ; -:VSUBPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VSUBPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vsubpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6062,7 +6062,7 @@ define pcodeop vsubpd_avx512f ; # SUBPS 4-659 PAGE 1779 LINE 92269 define pcodeop vsubps_avx512vl ; -:VSUBPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VSUBPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vsubps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6072,7 +6072,7 @@ define pcodeop vsubps_avx512vl ; } # SUBPS 4-659 PAGE 1779 LINE 92272 -:VSUBPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VSUBPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vsubps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6083,7 +6083,7 @@ define pcodeop vsubps_avx512vl ; # SUBPS 4-659 PAGE 1779 LINE 92275 define pcodeop vsubps_avx512f ; -:VSUBPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VSUBPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x5C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vsubps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6094,7 +6094,7 @@ define pcodeop vsubps_avx512f ; # SUBSD 4-662 PAGE 1782 LINE 92421 define pcodeop vsubsd_avx512f ; -:VSUBSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VSUBSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vsubsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -6105,7 +6105,7 @@ define pcodeop vsubsd_avx512f ; # SUBSS 4-664 PAGE 1784 LINE 92514 define pcodeop vsubss_avx512f ; -:VSUBSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VSUBSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vsubss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -6136,7 +6136,7 @@ define pcodeop vucomiss_avx512f ; # UNPCKHPD 4-688 PAGE 1808 LINE 93629 define pcodeop vunpckhpd_avx512vl ; -:VUNPCKHPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VUNPCKHPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vunpckhpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6146,7 +6146,7 @@ define pcodeop vunpckhpd_avx512vl ; } # UNPCKHPD 4-688 PAGE 1808 LINE 93632 -:VUNPCKHPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VUNPCKHPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vunpckhpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6157,7 +6157,7 @@ define pcodeop vunpckhpd_avx512vl ; # UNPCKHPD 4-688 PAGE 1808 LINE 93635 define pcodeop vunpckhpd_avx512f ; -:VUNPCKHPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VUNPCKHPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vunpckhpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6168,7 +6168,7 @@ define pcodeop vunpckhpd_avx512f ; # UNPCKHPS 4-692 PAGE 1812 LINE 93813 define pcodeop vunpckhps_avx512vl ; -:VUNPCKHPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VUNPCKHPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vunpckhps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6178,7 +6178,7 @@ define pcodeop vunpckhps_avx512vl ; } # UNPCKHPS 4-692 PAGE 1812 LINE 93817 -:VUNPCKHPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VUNPCKHPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vunpckhps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6189,7 +6189,7 @@ define pcodeop vunpckhps_avx512vl ; # UNPCKHPS 4-692 PAGE 1812 LINE 93821 define pcodeop vunpckhps_avx512f ; -:VUNPCKHPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VUNPCKHPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vunpckhps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6200,7 +6200,7 @@ define pcodeop vunpckhps_avx512f ; # UNPCKLPD 4-696 PAGE 1816 LINE 94045 define pcodeop vunpcklpd_avx512vl ; -:VUNPCKLPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VUNPCKLPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vunpcklpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6210,7 +6210,7 @@ define pcodeop vunpcklpd_avx512vl ; } # UNPCKLPD 4-696 PAGE 1816 LINE 94048 -:VUNPCKLPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VUNPCKLPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vunpcklpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6221,7 +6221,7 @@ define pcodeop vunpcklpd_avx512vl ; # UNPCKLPD 4-696 PAGE 1816 LINE 94051 define pcodeop vunpcklpd_avx512f ; -:VUNPCKLPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VUNPCKLPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vunpcklpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6232,7 +6232,7 @@ define pcodeop vunpcklpd_avx512f ; # UNPCKLPS 4-700 PAGE 1820 LINE 94231 define pcodeop vunpcklps_avx512vl ; -:VUNPCKLPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VUNPCKLPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vunpcklps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6242,7 +6242,7 @@ define pcodeop vunpcklps_avx512vl ; } # UNPCKLPS 4-700 PAGE 1820 LINE 94234 -:VUNPCKLPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VUNPCKLPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vunpcklps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6253,7 +6253,7 @@ define pcodeop vunpcklps_avx512vl ; # UNPCKLPS 4-700 PAGE 1820 LINE 94237 define pcodeop vunpcklps_avx512f ; -:VUNPCKLPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VUNPCKLPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vunpcklps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6264,7 +6264,7 @@ define pcodeop vunpcklps_avx512f ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94615 define pcodeop valignd_avx512vl ; -:VALIGND XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VALIGND XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = valignd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6275,7 +6275,7 @@ define pcodeop valignd_avx512vl ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94619 define pcodeop valignq_avx512vl ; -:VALIGNQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VALIGNQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = valignq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6285,7 +6285,7 @@ define pcodeop valignq_avx512vl ; } # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94623 -:VALIGND YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VALIGND YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = valignd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6295,7 +6295,7 @@ define pcodeop valignq_avx512vl ; } # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94627 -:VALIGNQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VALIGNQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = valignq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6306,7 +6306,7 @@ define pcodeop valignq_avx512vl ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94631 define pcodeop valignd_avx512f ; -:VALIGND ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x03; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VALIGND ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x03; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = valignd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6317,7 +6317,7 @@ define pcodeop valignd_avx512f ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94635 define pcodeop valignq_avx512f ; -:VALIGNQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x03; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VALIGNQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x03; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = valignq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6328,7 +6328,7 @@ define pcodeop valignq_avx512f ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94787 define pcodeop vblendmpd_avx512vl ; -:VBLENDMPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VBLENDMPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vblendmpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6338,7 +6338,7 @@ define pcodeop vblendmpd_avx512vl ; } # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94790 -:VBLENDMPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VBLENDMPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vblendmpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6349,7 +6349,7 @@ define pcodeop vblendmpd_avx512vl ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94793 define pcodeop vblendmpd_avx512f ; -:VBLENDMPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VBLENDMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vblendmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6360,7 +6360,7 @@ define pcodeop vblendmpd_avx512f ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94796 define pcodeop vblendmps_avx512vl ; -:VBLENDMPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VBLENDMPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vblendmps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6370,7 +6370,7 @@ define pcodeop vblendmps_avx512vl ; } # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94799 -:VBLENDMPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VBLENDMPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vblendmps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6381,7 +6381,7 @@ define pcodeop vblendmps_avx512vl ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94802 define pcodeop vblendmps_avx512f ; -:VBLENDMPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VBLENDMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x65; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vblendmps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6392,7 +6392,7 @@ define pcodeop vblendmps_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94917 define pcodeop vbroadcastsd_avx512vl ; -:VBROADCASTSD YmmReg1 YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 +:VBROADCASTSD YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcastsd_avx512vl( XmmReg2_m64 ); @@ -6403,7 +6403,7 @@ define pcodeop vbroadcastsd_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94920 define pcodeop vbroadcastsd_avx512f ; -:VBROADCASTSD ZmmReg1 ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 +:VBROADCASTSD ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x19; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastsd_avx512f( XmmReg2_m64 ); @@ -6414,7 +6414,7 @@ define pcodeop vbroadcastsd_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94923 define pcodeop vbroadcastf32x2_avx512vl ; -:VBROADCASTF32X2 YmmReg1 YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 +:VBROADCASTF32X2 YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcastf32x2_avx512vl( XmmReg2_m64 ); @@ -6425,7 +6425,7 @@ define pcodeop vbroadcastf32x2_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94926 define pcodeop vbroadcastf32x2_avx512dq ; -:VBROADCASTF32X2 ZmmReg1 ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64 +:VBROADCASTF32X2 ZmmReg1^ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x19; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastf32x2_avx512dq( XmmReg2_m64 ); @@ -6436,7 +6436,7 @@ define pcodeop vbroadcastf32x2_avx512dq ; # VBROADCAST 5-12 PAGE 1836 LINE 94929 define pcodeop vbroadcastss_avx512vl ; -:VBROADCASTSS XmmReg1 XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VBROADCASTSS XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { XmmResult = vbroadcastss_avx512vl( XmmReg2_m32 ); @@ -6446,7 +6446,7 @@ define pcodeop vbroadcastss_avx512vl ; } # VBROADCAST 5-12 PAGE 1836 LINE 94932 -:VBROADCASTSS YmmReg1 YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32 +:VBROADCASTSS YmmReg1^YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcastss_avx512vl( XmmReg2_m32 ); @@ -6457,7 +6457,7 @@ define pcodeop vbroadcastss_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94935 define pcodeop vbroadcastss_avx512f ; -:VBROADCASTSS ZmmReg1 ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32 +:VBROADCASTSS ZmmReg1^ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastss_avx512f( XmmReg2_m32 ); @@ -6468,7 +6468,7 @@ define pcodeop vbroadcastss_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94938 define pcodeop vbroadcastf32x4_avx512vl ; -:VBROADCASTF32X4 YmmReg1 YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128 +:VBROADCASTF32X4 YmmReg1^YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcastf32x4_avx512vl( m128 ); @@ -6479,7 +6479,7 @@ define pcodeop vbroadcastf32x4_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94941 define pcodeop vbroadcastf32x4_avx512f ; -:VBROADCASTF32X4 ZmmReg1 ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & m128 +:VBROADCASTF32X4 ZmmReg1^ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastf32x4_avx512f( m128 ); @@ -6490,7 +6490,7 @@ define pcodeop vbroadcastf32x4_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94944 define pcodeop vbroadcastf64x2_avx512vl ; -:VBROADCASTF64X2 YmmReg1 YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128 +:VBROADCASTF64X2 YmmReg1^YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcastf64x2_avx512vl( m128 ); @@ -6501,7 +6501,7 @@ define pcodeop vbroadcastf64x2_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94947 define pcodeop vbroadcastf64x2_avx512dq ; -:VBROADCASTF64X2 ZmmReg1 ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & m128 +:VBROADCASTF64X2 ZmmReg1^ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastf64x2_avx512dq( m128 ); @@ -6512,7 +6512,7 @@ define pcodeop vbroadcastf64x2_avx512dq ; # VBROADCAST 5-12 PAGE 1836 LINE 94950 define pcodeop vbroadcastf32x8_avx512dq ; -:VBROADCASTF32X8 ZmmReg1 ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1B; (ZmmReg1 & ZmmOpMask32) ... & m256 +:VBROADCASTF32X8 ZmmReg1^ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x1B; (ZmmReg1 & ZmmOpMask32) ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastf32x8_avx512dq( m256 ); @@ -6523,7 +6523,7 @@ define pcodeop vbroadcastf32x8_avx512dq ; # VBROADCAST 5-12 PAGE 1836 LINE 94953 define pcodeop vbroadcastf64x4_avx512f ; -:VBROADCASTF64X4 ZmmReg1 ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1B; (ZmmReg1 & ZmmOpMask64) ... & m256 +:VBROADCASTF64X4 ZmmReg1^ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x1B; (ZmmReg1 & ZmmOpMask64) ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcastf64x4_avx512f( m256 ); @@ -6578,7 +6578,7 @@ define pcodeop vpbroadcastmw2d_avx512cd ; # VCOMPRESSPD 5-21 PAGE 1845 LINE 95380 define pcodeop vcompresspd_avx512vl ; -:VCOMPRESSPD XmmReg2 XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VCOMPRESSPD XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmMask = XmmReg2; @@ -6587,7 +6587,7 @@ define pcodeop vcompresspd_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VCOMPRESSPD m128 XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128 +:VCOMPRESSPD m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmMask = m128; @@ -6597,7 +6597,7 @@ define pcodeop vcompresspd_avx512vl ; } # VCOMPRESSPD 5-21 PAGE 1845 LINE 95383 -:VCOMPRESSPD YmmReg2 YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VCOMPRESSPD YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmMask = YmmReg2; @@ -6606,7 +6606,7 @@ define pcodeop vcompresspd_avx512vl ; ZmmReg2 = zext(YmmResult); } -:VCOMPRESSPD m256 YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256 +:VCOMPRESSPD m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmMask = m256; @@ -6617,7 +6617,7 @@ define pcodeop vcompresspd_avx512vl ; # VCOMPRESSPD 5-21 PAGE 1845 LINE 95386 define pcodeop vcompresspd_avx512f ; -:VCOMPRESSPD ZmmReg2 ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2 +:VCOMPRESSPD ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmMask = ZmmReg2; @@ -6626,7 +6626,7 @@ define pcodeop vcompresspd_avx512f ; ZmmReg2 = ZmmResult; } -:VCOMPRESSPD m512 ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512 +:VCOMPRESSPD m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmMask = m512; @@ -6637,7 +6637,7 @@ define pcodeop vcompresspd_avx512f ; # VCOMPRESSPS 5-23 PAGE 1847 LINE 95481 define pcodeop vcompressps_avx512vl ; -:VCOMPRESSPS XmmReg2 XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VCOMPRESSPS XmmReg2^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmMask = XmmReg2; @@ -6646,7 +6646,7 @@ define pcodeop vcompressps_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VCOMPRESSPS m128 XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128 +:VCOMPRESSPS m128^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0x8A; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmMask = m128; @@ -6656,7 +6656,7 @@ define pcodeop vcompressps_avx512vl ; } # VCOMPRESSPS 5-23 PAGE 1847 LINE 95484 -:VCOMPRESSPS YmmReg2 YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VCOMPRESSPS YmmReg2^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmMask = YmmReg2; @@ -6665,7 +6665,7 @@ define pcodeop vcompressps_avx512vl ; ZmmReg2 = zext(YmmResult); } -:VCOMPRESSPS m256 YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256 +:VCOMPRESSPS m256^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0x8A; YmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmMask = m256; @@ -6676,7 +6676,7 @@ define pcodeop vcompressps_avx512vl ; # VCOMPRESSPS 5-23 PAGE 1847 LINE 95487 define pcodeop vcompressps_avx512f ; -:VCOMPRESSPS ZmmReg2 ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2 +:VCOMPRESSPS ZmmReg2^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 & mod=3 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmMask = ZmmReg2; @@ -6685,7 +6685,7 @@ define pcodeop vcompressps_avx512f ; ZmmReg2 = ZmmResult; } -:VCOMPRESSPS m512 ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512 +:VCOMPRESSPS m512^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0x8A; ZmmReg1 ... & m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmMask = m512; @@ -6696,7 +6696,7 @@ define pcodeop vcompressps_avx512f ; # VCVTPD2QQ 5-25 PAGE 1849 LINE 95583 define pcodeop vcvtpd2qq_avx512vl ; -:VCVTPD2QQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTPD2QQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2qq_avx512vl( XmmReg2_m128_m64bcst ); @@ -6706,7 +6706,7 @@ define pcodeop vcvtpd2qq_avx512vl ; } # VCVTPD2QQ 5-25 PAGE 1849 LINE 95586 -:VCVTPD2QQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTPD2QQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtpd2qq_avx512vl( YmmReg2_m256_m64bcst ); @@ -6717,7 +6717,7 @@ define pcodeop vcvtpd2qq_avx512vl ; # VCVTPD2QQ 5-25 PAGE 1849 LINE 95589 define pcodeop vcvtpd2qq_avx512dq ; -:VCVTPD2QQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTPD2QQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtpd2qq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -6728,7 +6728,7 @@ define pcodeop vcvtpd2qq_avx512dq ; # VCVTPD2UDQ 5-28 PAGE 1852 LINE 95706 define pcodeop vcvtpd2udq_avx512vl ; -:VCVTPD2UDQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTPD2UDQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2udq_avx512vl( XmmReg2_m128_m64bcst ); @@ -6738,7 +6738,7 @@ define pcodeop vcvtpd2udq_avx512vl ; } # VCVTPD2UDQ 5-28 PAGE 1852 LINE 95709 -:VCVTPD2UDQ XmmReg1 XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTPD2UDQ XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2udq_avx512vl( YmmReg2_m256_m64bcst ); @@ -6749,7 +6749,7 @@ define pcodeop vcvtpd2udq_avx512vl ; # VCVTPD2UDQ 5-28 PAGE 1852 LINE 95712 define pcodeop vcvtpd2udq_avx512f ; -:VCVTPD2UDQ YmmReg1 YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTPD2UDQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtpd2udq_avx512f( ZmmReg2_m512_m64bcst ); @@ -6760,7 +6760,7 @@ define pcodeop vcvtpd2udq_avx512f ; # VCVTPD2UQQ 5-31 PAGE 1855 LINE 95833 define pcodeop vcvtpd2uqq_avx512vl ; -:VCVTPD2UQQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTPD2UQQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtpd2uqq_avx512vl( XmmReg2_m128_m64bcst ); @@ -6770,7 +6770,7 @@ define pcodeop vcvtpd2uqq_avx512vl ; } # VCVTPD2UQQ 5-31 PAGE 1855 LINE 95836 -:VCVTPD2UQQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTPD2UQQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtpd2uqq_avx512vl( YmmReg2_m256_m64bcst ); @@ -6781,7 +6781,7 @@ define pcodeop vcvtpd2uqq_avx512vl ; # VCVTPD2UQQ 5-31 PAGE 1855 LINE 95839 define pcodeop vcvtpd2uqq_avx512dq ; -:VCVTPD2UQQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTPD2UQQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtpd2uqq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -6792,7 +6792,7 @@ define pcodeop vcvtpd2uqq_avx512dq ; # VCVTPH2PS 5-34 PAGE 1858 LINE 95963 define pcodeop vcvtph2ps_avx512vl ; -:VCVTPH2PS XmmReg1 XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 +:VCVTPH2PS XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vcvtph2ps_avx512vl( XmmReg2_m64 ); @@ -6802,7 +6802,7 @@ define pcodeop vcvtph2ps_avx512vl ; } # VCVTPH2PS 5-34 PAGE 1858 LINE 95966 -:VCVTPH2PS YmmReg1 YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 +:VCVTPH2PS YmmReg1^YmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vcvtph2ps_avx512vl( XmmReg2_m128 ); @@ -6813,7 +6813,7 @@ define pcodeop vcvtph2ps_avx512vl ; # VCVTPH2PS 5-34 PAGE 1858 LINE 95969 define pcodeop vcvtph2ps_avx512f ; -:VCVTPH2PS ZmmReg1 ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256 +:VCVTPH2PS ZmmReg1^ZmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x13; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { ZmmResult = vcvtph2ps_avx512f( YmmReg2_m256 ); @@ -6833,7 +6833,7 @@ define pcodeop vcvtph2ps_avx512f ; # VCVTPS2UDQ 5-41 PAGE 1865 LINE 96305 define pcodeop vcvtps2udq_avx512vl ; -:VCVTPS2UDQ XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTPS2UDQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtps2udq_avx512vl( XmmReg2_m128_m32bcst ); @@ -6843,7 +6843,7 @@ define pcodeop vcvtps2udq_avx512vl ; } # VCVTPS2UDQ 5-41 PAGE 1865 LINE 96309 -:VCVTPS2UDQ YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTPS2UDQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtps2udq_avx512vl( YmmReg2_m256_m32bcst ); @@ -6854,7 +6854,7 @@ define pcodeop vcvtps2udq_avx512vl ; # VCVTPS2UDQ 5-41 PAGE 1865 LINE 96313 define pcodeop vcvtps2udq_avx512f ; -:VCVTPS2UDQ ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VCVTPS2UDQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtps2udq_avx512f( ZmmReg2_m512_m32bcst ); @@ -6865,7 +6865,7 @@ define pcodeop vcvtps2udq_avx512f ; # VCVTPS2QQ 5-44 PAGE 1868 LINE 96434 define pcodeop vcvtps2qq_avx512vl ; -:VCVTPS2QQ XmmReg1 XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst +:VCVTPS2QQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvtps2qq_avx512vl( XmmReg2_m64_m32bcst ); @@ -6875,7 +6875,7 @@ define pcodeop vcvtps2qq_avx512vl ; } # VCVTPS2QQ 5-44 PAGE 1868 LINE 96437 -:VCVTPS2QQ YmmReg1 YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst +:VCVTPS2QQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvtps2qq_avx512vl( XmmReg2_m128_m32bcst ); @@ -6886,7 +6886,7 @@ define pcodeop vcvtps2qq_avx512vl ; # VCVTPS2QQ 5-44 PAGE 1868 LINE 96440 define pcodeop vcvtps2qq_avx512dq ; -:VCVTPS2QQ ZmmReg1 ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst +:VCVTPS2QQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7B; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvtps2qq_avx512dq( YmmReg2_m256_m32bcst ); @@ -6897,7 +6897,7 @@ define pcodeop vcvtps2qq_avx512dq ; # VCVTPS2UQQ 5-47 PAGE 1871 LINE 96560 define pcodeop vcvtps2uqq_avx512vl ; -:VCVTPS2UQQ XmmReg1 XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst +:VCVTPS2UQQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvtps2uqq_avx512vl( XmmReg2_m64_m32bcst ); @@ -6907,7 +6907,7 @@ define pcodeop vcvtps2uqq_avx512vl ; } # VCVTPS2UQQ 5-47 PAGE 1871 LINE 96563 -:VCVTPS2UQQ YmmReg1 YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst +:VCVTPS2UQQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvtps2uqq_avx512vl( XmmReg2_m128_m32bcst ); @@ -6918,7 +6918,7 @@ define pcodeop vcvtps2uqq_avx512vl ; # VCVTPS2UQQ 5-47 PAGE 1871 LINE 96566 define pcodeop vcvtps2uqq_avx512dq ; -:VCVTPS2UQQ ZmmReg1 ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst +:VCVTPS2UQQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvtps2uqq_avx512dq( YmmReg2_m256_m32bcst ); @@ -6929,7 +6929,7 @@ define pcodeop vcvtps2uqq_avx512dq ; # VCVTQQ2PD 5-50 PAGE 1874 LINE 96686 define pcodeop vcvtqq2pd_avx512vl ; -:VCVTQQ2PD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTQQ2PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtqq2pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -6939,7 +6939,7 @@ define pcodeop vcvtqq2pd_avx512vl ; } # VCVTQQ2PD 5-50 PAGE 1874 LINE 96689 -:VCVTQQ2PD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTQQ2PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtqq2pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -6950,7 +6950,7 @@ define pcodeop vcvtqq2pd_avx512vl ; # VCVTQQ2PD 5-50 PAGE 1874 LINE 96692 define pcodeop vcvtqq2pd_avx512dq ; -:VCVTQQ2PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTQQ2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0xE6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtqq2pd_avx512dq( ZmmReg2_m512_m64bcst ); @@ -6961,7 +6961,7 @@ define pcodeop vcvtqq2pd_avx512dq ; # VCVTQQ2PS 5-52 PAGE 1876 LINE 96797 define pcodeop vcvtqq2ps_avx512vl ; -:VCVTQQ2PS XmmReg1 XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst +:VCVTQQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtqq2ps_avx512vl( XmmReg2_m128_m64bcst ); @@ -6971,7 +6971,7 @@ define pcodeop vcvtqq2ps_avx512vl ; } # VCVTQQ2PS 5-52 PAGE 1876 LINE 96800 -:VCVTQQ2PS XmmReg1 XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst +:VCVTQQ2PS XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtqq2ps_avx512vl( YmmReg2_m256_m64bcst ); @@ -6982,7 +6982,7 @@ define pcodeop vcvtqq2ps_avx512vl ; # VCVTQQ2PS 5-52 PAGE 1876 LINE 96803 define pcodeop vcvtqq2ps_avx512dq ; -:VCVTQQ2PS YmmReg1 YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst +:VCVTQQ2PS YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x5B; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtqq2ps_avx512dq( ZmmReg2_m512_m64bcst ); @@ -7029,7 +7029,7 @@ define pcodeop vcvtss2usi_avx512f ; # VCVTTPD2QQ 5-57 PAGE 1881 LINE 97040 define pcodeop vcvttpd2qq_avx512vl ; -:VCVTTPD2QQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTTPD2QQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttpd2qq_avx512vl( XmmReg2_m128_m64bcst ); @@ -7039,7 +7039,7 @@ define pcodeop vcvttpd2qq_avx512vl ; } # VCVTTPD2QQ 5-57 PAGE 1881 LINE 97043 -:VCVTTPD2QQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTTPD2QQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvttpd2qq_avx512vl( YmmReg2_m256_m64bcst ); @@ -7050,7 +7050,7 @@ define pcodeop vcvttpd2qq_avx512vl ; # VCVTTPD2QQ 5-57 PAGE 1881 LINE 97046 define pcodeop vcvttpd2qq_avx512dq ; -:VCVTTPD2QQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTTPD2QQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvttpd2qq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -7061,7 +7061,7 @@ define pcodeop vcvttpd2qq_avx512dq ; # VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97147 define pcodeop vcvttpd2udq_avx512vl ; -:VCVTTPD2UDQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTTPD2UDQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttpd2udq_avx512vl( XmmReg2_m128_m64bcst ); @@ -7071,7 +7071,7 @@ define pcodeop vcvttpd2udq_avx512vl ; } # VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97152 -:VCVTTPD2UDQ XmmReg1 XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTTPD2UDQ XmmReg1^XmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttpd2udq_avx512vl( YmmReg2_m256_m64bcst ); @@ -7082,7 +7082,7 @@ define pcodeop vcvttpd2udq_avx512vl ; # VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97156 define pcodeop vcvttpd2udq_avx512f ; -:VCVTTPD2UDQ YmmReg1 YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTTPD2UDQ YmmReg1^YmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvttpd2udq_avx512f( ZmmReg2_m512_m64bcst ); @@ -7093,7 +7093,7 @@ define pcodeop vcvttpd2udq_avx512f ; # VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97272 define pcodeop vcvttpd2uqq_avx512vl ; -:VCVTTPD2UQQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTTPD2UQQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttpd2uqq_avx512vl( XmmReg2_m128_m64bcst ); @@ -7103,7 +7103,7 @@ define pcodeop vcvttpd2uqq_avx512vl ; } # VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97276 -:VCVTTPD2UQQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTTPD2UQQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvttpd2uqq_avx512vl( YmmReg2_m256_m64bcst ); @@ -7114,7 +7114,7 @@ define pcodeop vcvttpd2uqq_avx512vl ; # VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97280 define pcodeop vcvttpd2uqq_avx512dq ; -:VCVTTPD2UQQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTTPD2UQQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) ; byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvttpd2uqq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -7125,7 +7125,7 @@ define pcodeop vcvttpd2uqq_avx512dq ; # VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97385 define pcodeop vcvttps2udq_avx512vl ; -:VCVTTPS2UDQ XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTTPS2UDQ XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvttps2udq_avx512vl( XmmReg2_m128_m32bcst ); @@ -7135,7 +7135,7 @@ define pcodeop vcvttps2udq_avx512vl ; } # VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97389 -:VCVTTPS2UDQ YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTTPS2UDQ YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvttps2udq_avx512vl( YmmReg2_m256_m32bcst ); @@ -7146,7 +7146,7 @@ define pcodeop vcvttps2udq_avx512vl ; # VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97393 define pcodeop vcvttps2udq_avx512f ; -:VCVTTPS2UDQ ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VCVTTPS2UDQ ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvttps2udq_avx512f( ZmmReg2_m512_m32bcst ); @@ -7157,7 +7157,7 @@ define pcodeop vcvttps2udq_avx512f ; # VCVTTPS2QQ 5-66 PAGE 1890 LINE 97497 define pcodeop vcvttps2qq_avx512vl ; -:VCVTTPS2QQ XmmReg1 XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst +:VCVTTPS2QQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvttps2qq_avx512vl( XmmReg2_m64_m32bcst ); @@ -7167,7 +7167,7 @@ define pcodeop vcvttps2qq_avx512vl ; } # VCVTTPS2QQ 5-66 PAGE 1890 LINE 97500 -:VCVTTPS2QQ YmmReg1 YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst +:VCVTTPS2QQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvttps2qq_avx512vl( XmmReg2_m128_m32bcst ); @@ -7178,7 +7178,7 @@ define pcodeop vcvttps2qq_avx512vl ; # VCVTTPS2QQ 5-66 PAGE 1890 LINE 97503 define pcodeop vcvttps2qq_avx512dq ; -:VCVTTPS2QQ ZmmReg1 ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst +:VCVTTPS2QQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvttps2qq_avx512dq( YmmReg2_m256_m32bcst ); @@ -7189,7 +7189,7 @@ define pcodeop vcvttps2qq_avx512dq ; # VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97608 define pcodeop vcvttps2uqq_avx512vl ; -:VCVTTPS2UQQ XmmReg1 XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst +:VCVTTPS2UQQ XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvttps2uqq_avx512vl( XmmReg2_m64_m32bcst ); @@ -7199,7 +7199,7 @@ define pcodeop vcvttps2uqq_avx512vl ; } # VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97611 -:VCVTTPS2UQQ YmmReg1 YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst +:VCVTTPS2UQQ YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvttps2uqq_avx512vl( XmmReg2_m128_m32bcst ); @@ -7210,7 +7210,7 @@ define pcodeop vcvttps2uqq_avx512vl ; # VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97615 define pcodeop vcvttps2uqq_avx512dq ; -:VCVTTPS2UQQ ZmmReg1 ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst +:VCVTTPS2UQQ ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvttps2uqq_avx512dq( YmmReg2_m256_m32bcst ); @@ -7257,7 +7257,7 @@ define pcodeop vcvttss2usi_avx512f ; # VCVTUDQ2PD 5-73 PAGE 1897 LINE 97852 define pcodeop vcvtudq2pd_avx512vl ; -:VCVTUDQ2PD XmmReg1 XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst +:VCVTUDQ2PD XmmReg1^XmmOpMask64, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { XmmResult = vcvtudq2pd_avx512vl( XmmReg2_m64_m32bcst ); @@ -7267,7 +7267,7 @@ define pcodeop vcvtudq2pd_avx512vl ; } # VCVTUDQ2PD 5-73 PAGE 1897 LINE 97855 -:VCVTUDQ2PD YmmReg1 YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst +:VCVTUDQ2PD YmmReg1^YmmOpMask64, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { YmmResult = vcvtudq2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -7278,7 +7278,7 @@ define pcodeop vcvtudq2pd_avx512vl ; # VCVTUDQ2PD 5-73 PAGE 1897 LINE 97859 define pcodeop vcvtudq2pd_avx512f ; -:VCVTUDQ2PD ZmmReg1 ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst +:VCVTUDQ2PD ZmmReg1^ZmmOpMask64, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmResult = vcvtudq2pd_avx512f( YmmReg2_m256_m32bcst ); @@ -7289,7 +7289,7 @@ define pcodeop vcvtudq2pd_avx512f ; # VCVTUDQ2PS 5-75 PAGE 1899 LINE 97962 define pcodeop vcvtudq2ps_avx512vl ; -:VCVTUDQ2PS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VCVTUDQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtudq2ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -7299,7 +7299,7 @@ define pcodeop vcvtudq2ps_avx512vl ; } # VCVTUDQ2PS 5-75 PAGE 1899 LINE 97965 -:VCVTUDQ2PS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VCVTUDQ2PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtudq2ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -7310,7 +7310,7 @@ define pcodeop vcvtudq2ps_avx512vl ; # VCVTUDQ2PS 5-75 PAGE 1899 LINE 97968 define pcodeop vcvtudq2ps_avx512f ; -:VCVTUDQ2PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VCVTUDQ2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0); byte=0x7A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtudq2ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -7321,7 +7321,7 @@ define pcodeop vcvtudq2ps_avx512f ; # VCVTUQQ2PD 5-77 PAGE 1901 LINE 98078 define pcodeop vcvtuqq2pd_avx512vl ; -:VCVTUQQ2PD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VCVTUQQ2PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtuqq2pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -7331,7 +7331,7 @@ define pcodeop vcvtuqq2pd_avx512vl ; } # VCVTUQQ2PD 5-77 PAGE 1901 LINE 98081 -:VCVTUQQ2PD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VCVTUQQ2PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtuqq2pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -7342,7 +7342,7 @@ define pcodeop vcvtuqq2pd_avx512vl ; # VCVTUQQ2PD 5-77 PAGE 1901 LINE 98084 define pcodeop vcvtuqq2pd_avx512dq ; -:VCVTUQQ2PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VCVTUQQ2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vcvtuqq2pd_avx512dq( ZmmReg2_m512_m64bcst ); @@ -7353,7 +7353,7 @@ define pcodeop vcvtuqq2pd_avx512dq ; # VCVTUQQ2PS 5-79 PAGE 1903 LINE 98193 define pcodeop vcvtuqq2ps_avx512vl ; -:VCVTUQQ2PS XmmReg1 XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst +:VCVTUQQ2PS XmmReg1^XmmOpMask32, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtuqq2ps_avx512vl( XmmReg2_m128_m64bcst ); @@ -7363,7 +7363,7 @@ define pcodeop vcvtuqq2ps_avx512vl ; } # VCVTUQQ2PS 5-79 PAGE 1903 LINE 98196 -:VCVTUQQ2PS XmmReg1 XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst +:VCVTUQQ2PS XmmReg1^XmmOpMask32, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vcvtuqq2ps_avx512vl( YmmReg2_m256_m64bcst ); @@ -7374,7 +7374,7 @@ define pcodeop vcvtuqq2ps_avx512vl ; # VCVTUQQ2PS 5-79 PAGE 1903 LINE 98199 define pcodeop vcvtuqq2ps_avx512dq ; -:VCVTUQQ2PS YmmReg1 YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst +:VCVTUQQ2PS YmmReg1^YmmOpMask32, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) ; byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vcvtuqq2ps_avx512dq( ZmmReg2_m512_m64bcst ); @@ -7423,7 +7423,7 @@ define pcodeop vcvtusi2ss_avx512f ; # VDBPSADBW 5-85 PAGE 1909 LINE 98455 define pcodeop vdbpsadbw_avx512vl ; -:VDBPSADBW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8 +:VDBPSADBW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vdbpsadbw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); @@ -7433,7 +7433,7 @@ define pcodeop vdbpsadbw_avx512vl ; } # VDBPSADBW 5-85 PAGE 1909 LINE 98460 -:VDBPSADBW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8 +:VDBPSADBW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vdbpsadbw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); @@ -7444,7 +7444,7 @@ define pcodeop vdbpsadbw_avx512vl ; # VDBPSADBW 5-85 PAGE 1909 LINE 98465 define pcodeop vdbpsadbw_avx512bw ; -:VDBPSADBW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x42; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8 +:VDBPSADBW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x42; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vdbpsadbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 ); @@ -7455,7 +7455,7 @@ define pcodeop vdbpsadbw_avx512bw ; # VEXPANDPD 5-89 PAGE 1913 LINE 98660 define pcodeop vexpandpd_avx512vl ; -:VEXPANDPD XmmReg1 XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128 +:VEXPANDPD XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmMask = XmmReg1; @@ -7465,7 +7465,7 @@ define pcodeop vexpandpd_avx512vl ; } # VEXPANDPD 5-89 PAGE 1913 LINE 98663 -:VEXPANDPD YmmReg1 YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256 +:VEXPANDPD YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmMask = YmmReg1; @@ -7476,7 +7476,7 @@ define pcodeop vexpandpd_avx512vl ; # VEXPANDPD 5-89 PAGE 1913 LINE 98665 define pcodeop vexpandpd_avx512f ; -:VEXPANDPD ZmmReg1 ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512 +:VEXPANDPD ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmMask = ZmmReg1; @@ -7487,7 +7487,7 @@ define pcodeop vexpandpd_avx512f ; # VEXPANDPS 5-91 PAGE 1915 LINE 98748 define pcodeop vexpandps_avx512vl ; -:VEXPANDPS XmmReg1 XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128 +:VEXPANDPS XmmReg1^XmmOpMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (XmmReg1 & ZmmReg1 & XmmOpMask) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmMask = XmmReg1; @@ -7497,7 +7497,7 @@ define pcodeop vexpandps_avx512vl ; } # VEXPANDPS 5-91 PAGE 1915 LINE 98750 -:VEXPANDPS YmmReg1 YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256 +:VEXPANDPS YmmReg1^YmmOpMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (YmmReg1 & ZmmReg1 & YmmOpMask) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmMask = YmmReg1; @@ -7508,7 +7508,7 @@ define pcodeop vexpandps_avx512vl ; # VEXPANDPS 5-91 PAGE 1915 LINE 98752 define pcodeop vexpandps_avx512f ; -:VEXPANDPS ZmmReg1 ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512 +:VEXPANDPS ZmmReg1^ZmmOpMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x88; (ZmmReg1 & ZmmOpMask) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmMask = ZmmReg1; @@ -7519,7 +7519,7 @@ define pcodeop vexpandps_avx512f ; # VEXP2PD 5-95 PAGE 1919 LINE 98936 define pcodeop vexp2pd_avx512er ; -:VEXP2PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VEXP2PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vexp2pd_avx512er( ZmmReg1, ZmmReg2_m512_m64bcst ); @@ -7530,7 +7530,7 @@ define pcodeop vexp2pd_avx512er ; # VEXP2PS 5-97 PAGE 1921 LINE 99019 define pcodeop vexp2ps_avx512er ; -:VEXP2PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VEXP2PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vexp2ps_avx512er( ZmmReg1, ZmmReg2_m512_m32bcst ); @@ -7541,7 +7541,7 @@ define pcodeop vexp2ps_avx512er ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99105 define pcodeop vextractf32x4_avx512vl ; -:VEXTRACTF32X4 XmmReg2 XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTF32X4 XmmReg2^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf32x4_avx512vl( YmmReg1, imm8:1 ); @@ -7550,7 +7550,7 @@ define pcodeop vextractf32x4_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTF32X4 m128 XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 ... & m128; imm8 +:VEXTRACTF32X4 m128^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; YmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf32x4_avx512vl( YmmReg1, imm8:1 ); @@ -7562,7 +7562,7 @@ define pcodeop vextractf32x4_avx512vl ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99108 define pcodeop vextractf32x4_avx512f ; -:VEXTRACTF32x4 XmmReg2 XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTF32x4 XmmReg2^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf32x4_avx512f( ZmmReg1, imm8:1 ); @@ -7571,7 +7571,7 @@ define pcodeop vextractf32x4_avx512f ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTF32x4 m128 XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 ... & m128; imm8 +:VEXTRACTF32x4 m128^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x19; ZmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf32x4_avx512f( ZmmReg1, imm8:1 ); @@ -7582,7 +7582,7 @@ define pcodeop vextractf32x4_avx512f ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99111 define pcodeop vextractf64x2_avx512vl ; -:VEXTRACTF64X2 XmmReg2 XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTF64X2 XmmReg2^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf64x2_avx512vl( YmmReg1, imm8:1 ); @@ -7591,7 +7591,7 @@ define pcodeop vextractf64x2_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTF64X2 m128 XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 ... & m128; imm8 +:VEXTRACTF64X2 m128^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; YmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf64x2_avx512vl( YmmReg1, imm8:1 ); @@ -7603,7 +7603,7 @@ define pcodeop vextractf64x2_avx512vl ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99114 define pcodeop vextractf64x2_avx512dq ; -:VEXTRACTF64X2 XmmReg2 XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTF64X2 XmmReg2^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf64x2_avx512dq( ZmmReg1, imm8:1 ); @@ -7612,7 +7612,7 @@ define pcodeop vextractf64x2_avx512dq ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTF64X2 m128 XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 ... & m128; imm8 +:VEXTRACTF64X2 m128^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x19; ZmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextractf64x2_avx512dq( ZmmReg1, imm8:1 ); @@ -7623,7 +7623,7 @@ define pcodeop vextractf64x2_avx512dq ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99117 define pcodeop vextractf32x8_avx512dq ; -:VEXTRACTF32X8 YmmReg2 YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 +:VEXTRACTF32X8 YmmReg2^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextractf32x8_avx512dq( ZmmReg1, imm8:1 ); @@ -7632,7 +7632,7 @@ define pcodeop vextractf32x8_avx512dq ; ZmmReg2 = zext(YmmResult); } -:VEXTRACTF32X8 m256 YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 ... & m256; imm8 +:VEXTRACTF32X8 m256^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x1B; ZmmReg1 ... & m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextractf32x8_avx512dq( ZmmReg1, imm8:1 ); @@ -7643,7 +7643,7 @@ define pcodeop vextractf32x8_avx512dq ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99120 define pcodeop vextractf64x4_avx512f ; -:VEXTRACTF64x4 YmmReg2 YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 +:VEXTRACTF64x4 YmmReg2^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextractf64x4_avx512f( ZmmReg1, imm8:1 ); @@ -7652,7 +7652,7 @@ define pcodeop vextractf64x4_avx512f ; ZmmReg2 = zext(YmmResult); } -:VEXTRACTF64x4 m256 YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 ... & m256; imm8 +:VEXTRACTF64x4 m256^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x1B; ZmmReg1 ... & m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextractf64x4_avx512f( ZmmReg1, imm8:1 ); @@ -7663,7 +7663,7 @@ define pcodeop vextractf64x4_avx512f ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99435 define pcodeop vextracti32x4_avx512vl ; -:VEXTRACTI32X4 XmmReg2 XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTI32X4 XmmReg2^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti32x4_avx512vl( YmmReg1, imm8:1 ); @@ -7672,7 +7672,7 @@ define pcodeop vextracti32x4_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTI32X4 m128 XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 ... & m128; imm8 +:VEXTRACTI32X4 m128^XmmOpMask32, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; YmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti32x4_avx512vl( YmmReg1, imm8:1 ); @@ -7683,7 +7683,7 @@ define pcodeop vextracti32x4_avx512vl ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99438 define pcodeop vextracti32x4_avx512f ; -:VEXTRACTI32x4 XmmReg2 XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTI32x4 XmmReg2^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti32x4_avx512f( ZmmReg1, imm8:1 ); @@ -7692,7 +7692,7 @@ define pcodeop vextracti32x4_avx512f ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTI32x4 m128 XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 ... & m128; imm8 +:VEXTRACTI32x4 m128^XmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask32; byte=0x39; ZmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti32x4_avx512f( ZmmReg1, imm8:1 ); @@ -7703,7 +7703,7 @@ define pcodeop vextracti32x4_avx512f ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99441 define pcodeop vextracti64x2_avx512vl ; -:VEXTRACTI64X2 XmmReg2 XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTI64X2 XmmReg2^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti64x2_avx512vl( YmmReg1, imm8:1 ); @@ -7712,7 +7712,7 @@ define pcodeop vextracti64x2_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTI64X2 m128 XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 ... & m128; imm8 +:VEXTRACTI64X2 m128^XmmOpMask64, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; YmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti64x2_avx512vl( YmmReg1, imm8:1 ); @@ -7723,7 +7723,7 @@ define pcodeop vextracti64x2_avx512vl ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99444 define pcodeop vextracti64x2_avx512dq ; -:VEXTRACTI64X2 XmmReg2 XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 +:VEXTRACTI64X2 XmmReg2^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 & mod=3 & XmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti64x2_avx512dq( ZmmReg1, imm8:1 ); @@ -7732,7 +7732,7 @@ define pcodeop vextracti64x2_avx512dq ; ZmmReg2 = zext(XmmResult); } -:VEXTRACTI64X2 m128 XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 ... & m128; imm8 +:VEXTRACTI64X2 m128^XmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & XmmOpMask64; byte=0x39; ZmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmResult = vextracti64x2_avx512dq( ZmmReg1, imm8:1 ); @@ -7743,7 +7743,7 @@ define pcodeop vextracti64x2_avx512dq ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99447 define pcodeop vextracti32x8_avx512dq ; -:VEXTRACTI32X8 YmmReg2 YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 +:VEXTRACTI32X8 YmmReg2^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextracti32x8_avx512dq( ZmmReg1, imm8:1 ); @@ -7752,7 +7752,7 @@ define pcodeop vextracti32x8_avx512dq ; ZmmReg2 = zext(YmmResult); } -:VEXTRACTI32X8 m256 YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 ... & m256; imm8 +:VEXTRACTI32X8 m256^YmmOpMask32, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask32; byte=0x3B; ZmmReg1 ... & m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextracti32x8_avx512dq( ZmmReg1, imm8:1 ); @@ -7763,7 +7763,7 @@ define pcodeop vextracti32x8_avx512dq ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99450 define pcodeop vextracti64x4_avx512f ; -:VEXTRACTI64x4 YmmReg2 YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 +:VEXTRACTI64x4 YmmReg2^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 & mod=3 & YmmReg2 & ZmmReg2; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextracti64x4_avx512f( ZmmReg1, imm8:1 ); @@ -7772,7 +7772,7 @@ define pcodeop vextracti64x4_avx512f ; ZmmReg2 = zext(YmmResult); } -:VEXTRACTI64x4 m256 YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 ... & m256; imm8 +:VEXTRACTI64x4 m256^YmmOpMask64, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & YmmOpMask64; byte=0x3B; ZmmReg1 ... & m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vextracti64x4_avx512f( ZmmReg1, imm8:1 ); @@ -7782,7 +7782,7 @@ define pcodeop vextracti64x4_avx512f ; } # VFIXUPIMMPD 5-112 PAGE 1936 LINE 99754 define pcodeop vfixupimmpd_avx512vl ; -:VFIXUPIMMPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VFIXUPIMMPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfixupimmpd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -7792,7 +7792,7 @@ define pcodeop vfixupimmpd_avx512vl ; } # VFIXUPIMMPD 5-112 PAGE 1936 LINE 99757 -:VFIXUPIMMPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VFIXUPIMMPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfixupimmpd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -7803,7 +7803,7 @@ define pcodeop vfixupimmpd_avx512vl ; # VFIXUPIMMPD 5-112 PAGE 1936 LINE 99760 define pcodeop vfixupimmpd_avx512f ; -:VFIXUPIMMPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VFIXUPIMMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfixupimmpd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -7814,7 +7814,7 @@ define pcodeop vfixupimmpd_avx512f ; # VFIXUPIMMPS 5-116 PAGE 1940 LINE 99957 define pcodeop vfixupimmps_avx512vl ; -:VFIXUPIMMPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VFIXUPIMMPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfixupimmps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -7824,7 +7824,7 @@ define pcodeop vfixupimmps_avx512vl ; } # VFIXUPIMMPS 5-116 PAGE 1940 LINE 99960 -:VFIXUPIMMPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VFIXUPIMMPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfixupimmps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -7835,7 +7835,7 @@ define pcodeop vfixupimmps_avx512vl ; # VFIXUPIMMPS 5-116 PAGE 1940 LINE 99963 define pcodeop vfixupimmps_avx512f ; -:VFIXUPIMMPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VFIXUPIMMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x54; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfixupimmps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -7846,7 +7846,7 @@ define pcodeop vfixupimmps_avx512f ; # VFIXUPIMMSD 5-120 PAGE 1944 LINE 100159 define pcodeop vfixupimmsd_avx512f ; -:VFIXUPIMMSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8 +:VFIXUPIMMSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfixupimmsd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); @@ -7857,7 +7857,7 @@ define pcodeop vfixupimmsd_avx512f ; # VFIXUPIMMSS 5-123 PAGE 1947 LINE 100331 define pcodeop vfixupimmss_avx512f ; -:VFIXUPIMMSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8 +:VFIXUPIMMSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfixupimmss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8:1 ); @@ -7868,7 +7868,7 @@ define pcodeop vfixupimmss_avx512f ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100523 define pcodeop vfmadd132pd_avx512vl ; -:VFMADD132PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMADD132PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst { XmmResult = vfmadd132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); XmmMask = XmmReg1; @@ -7878,7 +7878,7 @@ define pcodeop vfmadd132pd_avx512vl ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100526 define pcodeop vfmadd213pd_avx512vl ; -:VFMADD213PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMADD213PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmadd213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7889,7 +7889,7 @@ define pcodeop vfmadd213pd_avx512vl ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100529 define pcodeop vfmadd231pd_avx512vl ; -:VFMADD231PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMADD231PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmadd231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7899,7 +7899,7 @@ define pcodeop vfmadd231pd_avx512vl ; } # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100532 -:VFMADD132PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMADD132PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmadd132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7909,7 +7909,7 @@ define pcodeop vfmadd231pd_avx512vl ; } # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100535 -:VFMADD213PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMADD213PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmadd213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7919,7 +7919,7 @@ define pcodeop vfmadd231pd_avx512vl ; } # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100538 -:VFMADD231PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMADD231PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmadd231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7930,7 +7930,7 @@ define pcodeop vfmadd231pd_avx512vl ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100541 define pcodeop vfmadd132pd_avx512f ; -:VFMADD132PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7941,7 +7941,7 @@ define pcodeop vfmadd132pd_avx512f ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100544 define pcodeop vfmadd213pd_avx512f ; -:VFMADD213PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7952,7 +7952,7 @@ define pcodeop vfmadd213pd_avx512f ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100547 define pcodeop vfmadd231pd_avx512f ; -:VFMADD231PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7963,7 +7963,7 @@ define pcodeop vfmadd231pd_avx512f ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100884 define pcodeop vfmadd132ps_avx512vl ; -:VFMADD132PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMADD132PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmadd132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7974,7 +7974,7 @@ define pcodeop vfmadd132ps_avx512vl ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100887 define pcodeop vfmadd213ps_avx512vl ; -:VFMADD213PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMADD213PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmadd213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7985,7 +7985,7 @@ define pcodeop vfmadd213ps_avx512vl ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100890 define pcodeop vfmadd231ps_avx512vl ; -:VFMADD231PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMADD231PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmadd231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7995,7 +7995,7 @@ define pcodeop vfmadd231ps_avx512vl ; } # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100893 -:VFMADD132PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMADD132PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmadd132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8005,7 +8005,7 @@ define pcodeop vfmadd231ps_avx512vl ; } # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100896 -:VFMADD213PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMADD213PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmadd213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8015,7 +8015,7 @@ define pcodeop vfmadd231ps_avx512vl ; } # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100899 -:VFMADD231PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMADD231PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmadd231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8026,7 +8026,7 @@ define pcodeop vfmadd231ps_avx512vl ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100902 define pcodeop vfmadd132ps_avx512f ; -:VFMADD132PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x98; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8037,7 +8037,7 @@ define pcodeop vfmadd132ps_avx512f ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100905 define pcodeop vfmadd213ps_avx512f ; -:VFMADD213PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8048,7 +8048,7 @@ define pcodeop vfmadd213ps_avx512f ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100908 define pcodeop vfmadd231ps_avx512f ; -:VFMADD231PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB8; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8059,7 +8059,7 @@ define pcodeop vfmadd231ps_avx512f ; # VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101235 define pcodeop vfmadd132sd_avx512f ; -:VFMADD132SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFMADD132SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmadd132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8070,7 +8070,7 @@ define pcodeop vfmadd132sd_avx512f ; # VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101238 define pcodeop vfmadd213sd_avx512f ; -:VFMADD213SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFMADD213SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmadd213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8081,7 +8081,7 @@ define pcodeop vfmadd213sd_avx512f ; # VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101241 define pcodeop vfmadd231sd_avx512f ; -:VFMADD231SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFMADD231SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmadd231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8092,7 +8092,7 @@ define pcodeop vfmadd231sd_avx512f ; # VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101403 define pcodeop vfmadd132ss_avx512f ; -:VFMADD132SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFMADD132SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmadd132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8103,7 +8103,7 @@ define pcodeop vfmadd132ss_avx512f ; # VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101406 define pcodeop vfmadd213ss_avx512f ; -:VFMADD213SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFMADD213SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmadd213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8114,7 +8114,7 @@ define pcodeop vfmadd213ss_avx512f ; # VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101409 define pcodeop vfmadd231ss_avx512f ; -:VFMADD231SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFMADD231SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmadd231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8125,7 +8125,7 @@ define pcodeop vfmadd231ss_avx512f ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101585 define pcodeop vfmaddsub213pd_avx512vl ; -:VFMADDSUB213PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMADDSUB213PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmaddsub213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8136,7 +8136,7 @@ define pcodeop vfmaddsub213pd_avx512vl ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101589 define pcodeop vfmaddsub231pd_avx512vl ; -:VFMADDSUB231PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMADDSUB231PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmaddsub231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8147,7 +8147,7 @@ define pcodeop vfmaddsub231pd_avx512vl ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101593 define pcodeop vfmaddsub132pd_avx512vl ; -:VFMADDSUB132PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMADDSUB132PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmaddsub132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8157,7 +8157,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; } # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101597 -:VFMADDSUB213PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMADDSUB213PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmaddsub213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8167,7 +8167,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; } # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101601 -:VFMADDSUB231PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMADDSUB231PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmaddsub231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8177,7 +8177,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; } # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101605 -:VFMADDSUB132PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMADDSUB132PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmaddsub132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8188,7 +8188,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101621 define pcodeop vfmaddsub213pd_avx512f ; -:VFMADDSUB213PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMADDSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmaddsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8199,7 +8199,7 @@ define pcodeop vfmaddsub213pd_avx512f ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101625 define pcodeop vfmaddsub231pd_avx512f ; -:VFMADDSUB231PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMADDSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmaddsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8210,7 +8210,7 @@ define pcodeop vfmaddsub231pd_avx512f ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101629 define pcodeop vfmaddsub132pd_avx512f ; -:VFMADDSUB132PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMADDSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmaddsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8221,7 +8221,7 @@ define pcodeop vfmaddsub132pd_avx512f ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102024 define pcodeop vfmaddsub213ps_avx512vl ; -:VFMADDSUB213PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMADDSUB213PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmaddsub213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8232,7 +8232,7 @@ define pcodeop vfmaddsub213ps_avx512vl ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102028 define pcodeop vfmaddsub231ps_avx512vl ; -:VFMADDSUB231PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMADDSUB231PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmaddsub231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8243,7 +8243,7 @@ define pcodeop vfmaddsub231ps_avx512vl ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102031 define pcodeop vfmaddsub132ps_avx512vl ; -:VFMADDSUB132PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMADDSUB132PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmaddsub132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8253,7 +8253,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; } # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102034 -:VFMADDSUB213PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMADDSUB213PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmaddsub213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8263,7 +8263,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; } # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102038 -:VFMADDSUB231PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMADDSUB231PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmaddsub231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8273,7 +8273,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; } # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102041 -:VFMADDSUB132PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMADDSUB132PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmaddsub132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8284,7 +8284,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102044 define pcodeop vfmaddsub213ps_avx512f ; -:VFMADDSUB213PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMADDSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmaddsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8295,7 +8295,7 @@ define pcodeop vfmaddsub213ps_avx512f ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102048 define pcodeop vfmaddsub231ps_avx512f ; -:VFMADDSUB231PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMADDSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB6; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmaddsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8306,7 +8306,7 @@ define pcodeop vfmaddsub231ps_avx512f ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102051 define pcodeop vfmaddsub132ps_avx512f ; -:VFMADDSUB132PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMADDSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x96; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmaddsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8317,7 +8317,7 @@ define pcodeop vfmaddsub132ps_avx512f ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102454 define pcodeop vfmsubadd132pd_avx512vl ; -:VFMSUBADD132PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMSUBADD132PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsubadd132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8328,7 +8328,7 @@ define pcodeop vfmsubadd132pd_avx512vl ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102458 define pcodeop vfmsubadd213pd_avx512vl ; -:VFMSUBADD213PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMSUBADD213PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsubadd213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8339,7 +8339,7 @@ define pcodeop vfmsubadd213pd_avx512vl ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102462 define pcodeop vfmsubadd231pd_avx512vl ; -:VFMSUBADD231PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMSUBADD231PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsubadd231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8349,7 +8349,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; } # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102466 -:VFMSUBADD132PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMSUBADD132PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsubadd132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8359,7 +8359,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; } # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102470 -:VFMSUBADD213PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMSUBADD213PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsubadd213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8369,7 +8369,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; } # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102474 -:VFMSUBADD231PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMSUBADD231PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsubadd231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8380,7 +8380,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102490 define pcodeop vfmsubadd132pd_avx512f ; -:VFMSUBADD132PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMSUBADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsubadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8391,7 +8391,7 @@ define pcodeop vfmsubadd132pd_avx512f ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102494 define pcodeop vfmsubadd213pd_avx512f ; -:VFMSUBADD213PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMSUBADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsubadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8402,7 +8402,7 @@ define pcodeop vfmsubadd213pd_avx512f ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102498 define pcodeop vfmsubadd231pd_avx512f ; -:VFMSUBADD231PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMSUBADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsubadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8413,7 +8413,7 @@ define pcodeop vfmsubadd231pd_avx512f ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102894 define pcodeop vfmsubadd132ps_avx512vl ; -:VFMSUBADD132PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMSUBADD132PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsubadd132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8424,7 +8424,7 @@ define pcodeop vfmsubadd132ps_avx512vl ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102897 define pcodeop vfmsubadd213ps_avx512vl ; -:VFMSUBADD213PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMSUBADD213PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsubadd213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8435,7 +8435,7 @@ define pcodeop vfmsubadd213ps_avx512vl ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102901 define pcodeop vfmsubadd231ps_avx512vl ; -:VFMSUBADD231PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMSUBADD231PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsubadd231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8445,7 +8445,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; } # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102904 -:VFMSUBADD132PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMSUBADD132PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsubadd132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8455,7 +8455,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; } # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102907 -:VFMSUBADD213PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMSUBADD213PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsubadd213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8465,7 +8465,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; } # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102911 -:VFMSUBADD231PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMSUBADD231PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsubadd231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8476,7 +8476,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102914 define pcodeop vfmsubadd132ps_avx512f ; -:VFMSUBADD132PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMSUBADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x97; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsubadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8487,7 +8487,7 @@ define pcodeop vfmsubadd132ps_avx512f ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102917 define pcodeop vfmsubadd213ps_avx512f ; -:VFMSUBADD213PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMSUBADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xA7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsubadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8498,7 +8498,7 @@ define pcodeop vfmsubadd213ps_avx512f ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102921 define pcodeop vfmsubadd231ps_avx512f ; -:VFMSUBADD231PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMSUBADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xB7; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsubadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8509,7 +8509,7 @@ define pcodeop vfmsubadd231ps_avx512f ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103332 define pcodeop vfmsub132pd_avx512vl ; -:VFMSUB132PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMSUB132PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsub132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8520,7 +8520,7 @@ define pcodeop vfmsub132pd_avx512vl ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103335 define pcodeop vfmsub213pd_avx512vl ; -:VFMSUB213PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMSUB213PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsub213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8531,7 +8531,7 @@ define pcodeop vfmsub213pd_avx512vl ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103338 define pcodeop vfmsub231pd_avx512vl ; -:VFMSUB231PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFMSUB231PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsub231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8541,7 +8541,7 @@ define pcodeop vfmsub231pd_avx512vl ; } # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103341 -:VFMSUB132PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMSUB132PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsub132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8551,7 +8551,7 @@ define pcodeop vfmsub231pd_avx512vl ; } # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103344 -:VFMSUB213PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMSUB213PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsub213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8561,7 +8561,7 @@ define pcodeop vfmsub231pd_avx512vl ; } # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103347 -:VFMSUB231PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFMSUB231PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsub231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8572,7 +8572,7 @@ define pcodeop vfmsub231pd_avx512vl ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103350 define pcodeop vfmsub132pd_avx512f ; -:VFMSUB132PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8583,7 +8583,7 @@ define pcodeop vfmsub132pd_avx512f ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103353 define pcodeop vfmsub213pd_avx512f ; -:VFMSUB213PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8594,7 +8594,7 @@ define pcodeop vfmsub213pd_avx512f ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103356 define pcodeop vfmsub231pd_avx512f ; -:VFMSUB231PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFMSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8605,7 +8605,7 @@ define pcodeop vfmsub231pd_avx512f ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103692 define pcodeop vfmsub132ps_avx512vl ; -:VFMSUB132PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMSUB132PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsub132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8616,7 +8616,7 @@ define pcodeop vfmsub132ps_avx512vl ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103695 define pcodeop vfmsub213ps_avx512vl ; -:VFMSUB213PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMSUB213PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsub213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8627,7 +8627,7 @@ define pcodeop vfmsub213ps_avx512vl ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103698 define pcodeop vfmsub231ps_avx512vl ; -:VFMSUB231PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFMSUB231PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfmsub231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8637,7 +8637,7 @@ define pcodeop vfmsub231ps_avx512vl ; } # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103701 -:VFMSUB132PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMSUB132PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsub132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8647,7 +8647,7 @@ define pcodeop vfmsub231ps_avx512vl ; } # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103704 -:VFMSUB213PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMSUB213PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsub213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8657,7 +8657,7 @@ define pcodeop vfmsub231ps_avx512vl ; } # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103707 -:VFMSUB231PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFMSUB231PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfmsub231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8668,7 +8668,7 @@ define pcodeop vfmsub231ps_avx512vl ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103710 define pcodeop vfmsub132ps_avx512f ; -:VFMSUB132PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9A; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8679,7 +8679,7 @@ define pcodeop vfmsub132ps_avx512f ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103713 define pcodeop vfmsub213ps_avx512f ; -:VFMSUB213PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8690,7 +8690,7 @@ define pcodeop vfmsub213ps_avx512f ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103716 define pcodeop vfmsub231ps_avx512f ; -:VFMSUB231PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFMSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8701,7 +8701,7 @@ define pcodeop vfmsub231ps_avx512f ; # VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104042 define pcodeop vfmsub132sd_avx512f ; -:VFMSUB132SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFMSUB132SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmsub132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8712,7 +8712,7 @@ define pcodeop vfmsub132sd_avx512f ; # VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104045 define pcodeop vfmsub213sd_avx512f ; -:VFMSUB213SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFMSUB213SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmsub213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8723,7 +8723,7 @@ define pcodeop vfmsub213sd_avx512f ; # VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104048 define pcodeop vfmsub231sd_avx512f ; -:VFMSUB231SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFMSUB231SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmsub231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8734,7 +8734,7 @@ define pcodeop vfmsub231sd_avx512f ; # VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104217 define pcodeop vfmsub132ss_avx512f ; -:VFMSUB132SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFMSUB132SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmsub132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8745,7 +8745,7 @@ define pcodeop vfmsub132ss_avx512f ; # VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104220 define pcodeop vfmsub213ss_avx512f ; -:VFMSUB213SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFMSUB213SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmsub213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8756,7 +8756,7 @@ define pcodeop vfmsub213ss_avx512f ; # VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104223 define pcodeop vfmsub231ss_avx512f ; -:VFMSUB231SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFMSUB231SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfmsub231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8767,7 +8767,7 @@ define pcodeop vfmsub231ss_avx512f ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104401 define pcodeop vfnmadd132pd_avx512vl ; -:VFNMADD132PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFNMADD132PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmadd132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8778,7 +8778,7 @@ define pcodeop vfnmadd132pd_avx512vl ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104405 define pcodeop vfnmadd213pd_avx512vl ; -:VFNMADD213PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFNMADD213PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmadd213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8789,7 +8789,7 @@ define pcodeop vfnmadd213pd_avx512vl ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104408 define pcodeop vfnmadd231pd_avx512vl ; -:VFNMADD231PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFNMADD231PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmadd231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8799,7 +8799,7 @@ define pcodeop vfnmadd231pd_avx512vl ; } # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104412 -:VFNMADD132PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFNMADD132PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmadd132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8809,7 +8809,7 @@ define pcodeop vfnmadd231pd_avx512vl ; } # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104416 -:VFNMADD213PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFNMADD213PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmadd213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8819,7 +8819,7 @@ define pcodeop vfnmadd231pd_avx512vl ; } # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104419 -:VFNMADD231PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFNMADD231PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmadd231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8830,7 +8830,7 @@ define pcodeop vfnmadd231pd_avx512vl ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104423 define pcodeop vfnmadd132pd_avx512f ; -:VFNMADD132PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFNMADD132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8841,7 +8841,7 @@ define pcodeop vfnmadd132pd_avx512f ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104426 define pcodeop vfnmadd213pd_avx512f ; -:VFNMADD213PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFNMADD213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8852,7 +8852,7 @@ define pcodeop vfnmadd213pd_avx512f ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104429 define pcodeop vfnmadd231pd_avx512f ; -:VFNMADD231PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFNMADD231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8863,7 +8863,7 @@ define pcodeop vfnmadd231pd_avx512f ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104760 define pcodeop vfnmadd132ps_avx512vl ; -:VFNMADD132PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFNMADD132PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmadd132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8874,7 +8874,7 @@ define pcodeop vfnmadd132ps_avx512vl ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104763 define pcodeop vfnmadd213ps_avx512vl ; -:VFNMADD213PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFNMADD213PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmadd213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8885,7 +8885,7 @@ define pcodeop vfnmadd213ps_avx512vl ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104766 define pcodeop vfnmadd231ps_avx512vl ; -:VFNMADD231PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFNMADD231PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmadd231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8895,7 +8895,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104769 -:VFNMADD132PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFNMADD132PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmadd132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8905,7 +8905,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104772 -:VFNMADD213PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFNMADD213PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmadd213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8915,7 +8915,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104775 -:VFNMADD231PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFNMADD231PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmadd231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8925,7 +8925,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104778 -:VFNMADD132PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFNMADD132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmadd132ps_avx512vl( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8936,7 +8936,7 @@ define pcodeop vfnmadd231ps_avx512vl ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104781 define pcodeop vfnmadd213ps_avx512f ; -:VFNMADD213PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFNMADD213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8947,7 +8947,7 @@ define pcodeop vfnmadd213ps_avx512f ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104784 define pcodeop vfnmadd231ps_avx512f ; -:VFNMADD231PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFNMADD231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8958,7 +8958,7 @@ define pcodeop vfnmadd231ps_avx512f ; # VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105098 define pcodeop vfnmadd132sd_avx512f ; -:VFNMADD132SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFNMADD132SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmadd132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8969,7 +8969,7 @@ define pcodeop vfnmadd132sd_avx512f ; # VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105101 define pcodeop vfnmadd213sd_avx512f ; -:VFNMADD213SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFNMADD213SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmadd213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8980,7 +8980,7 @@ define pcodeop vfnmadd213sd_avx512f ; # VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105104 define pcodeop vfnmadd231sd_avx512f ; -:VFNMADD231SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFNMADD231SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmadd231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8991,7 +8991,7 @@ define pcodeop vfnmadd231sd_avx512f ; # VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105270 define pcodeop vfnmadd132ss_avx512f ; -:VFNMADD132SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFNMADD132SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmadd132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9002,7 +9002,7 @@ define pcodeop vfnmadd132ss_avx512f ; # VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105273 define pcodeop vfnmadd213ss_avx512f ; -:VFNMADD213SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFNMADD213SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmadd213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9013,7 +9013,7 @@ define pcodeop vfnmadd213ss_avx512f ; # VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105276 define pcodeop vfnmadd231ss_avx512f ; -:VFNMADD231SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFNMADD231SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmadd231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9024,7 +9024,7 @@ define pcodeop vfnmadd231ss_avx512f ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105451 define pcodeop vfnmsub132pd_avx512vl ; -:VFNMSUB132PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFNMSUB132PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmsub132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9035,7 +9035,7 @@ define pcodeop vfnmsub132pd_avx512vl ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105455 define pcodeop vfnmsub213pd_avx512vl ; -:VFNMSUB213PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFNMSUB213PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmsub213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9046,7 +9046,7 @@ define pcodeop vfnmsub213pd_avx512vl ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105458 define pcodeop vfnmsub231pd_avx512vl ; -:VFNMSUB231PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VFNMSUB231PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmsub231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9056,7 +9056,7 @@ define pcodeop vfnmsub231pd_avx512vl ; } # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105462 -:VFNMSUB132PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFNMSUB132PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmsub132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9066,7 +9066,7 @@ define pcodeop vfnmsub231pd_avx512vl ; } # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105466 -:VFNMSUB213PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFNMSUB213PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmsub213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9076,7 +9076,7 @@ define pcodeop vfnmsub231pd_avx512vl ; } # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105469 -:VFNMSUB231PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VFNMSUB231PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmsub231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9087,7 +9087,7 @@ define pcodeop vfnmsub231pd_avx512vl ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105473 define pcodeop vfnmsub132pd_avx512f ; -:VFNMSUB132PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFNMSUB132PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9098,7 +9098,7 @@ define pcodeop vfnmsub132pd_avx512f ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105476 define pcodeop vfnmsub213pd_avx512f ; -:VFNMSUB213PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFNMSUB213PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9109,7 +9109,7 @@ define pcodeop vfnmsub213pd_avx512f ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105479 define pcodeop vfnmsub231pd_avx512f ; -:VFNMSUB231PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VFNMSUB231PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9120,7 +9120,7 @@ define pcodeop vfnmsub231pd_avx512f ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105800 define pcodeop vfnmsub132ps_avx512vl ; -:VFNMSUB132PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFNMSUB132PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmsub132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9131,7 +9131,7 @@ define pcodeop vfnmsub132ps_avx512vl ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105803 define pcodeop vfnmsub213ps_avx512vl ; -:VFNMSUB213PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFNMSUB213PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmsub213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9142,7 +9142,7 @@ define pcodeop vfnmsub213ps_avx512vl ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105806 define pcodeop vfnmsub231ps_avx512vl ; -:VFNMSUB231PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VFNMSUB231PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vfnmsub231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9152,7 +9152,7 @@ define pcodeop vfnmsub231ps_avx512vl ; } # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105809 -:VFNMSUB132PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFNMSUB132PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmsub132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9162,7 +9162,7 @@ define pcodeop vfnmsub231ps_avx512vl ; } # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105812 -:VFNMSUB213PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFNMSUB213PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmsub213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9172,7 +9172,7 @@ define pcodeop vfnmsub231ps_avx512vl ; } # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105815 -:VFNMSUB231PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VFNMSUB231PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vfnmsub231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9183,7 +9183,7 @@ define pcodeop vfnmsub231ps_avx512vl ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105818 define pcodeop vfnmsub132ps_avx512f ; -:VFNMSUB132PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFNMSUB132PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x9E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9194,7 +9194,7 @@ define pcodeop vfnmsub132ps_avx512f ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105821 define pcodeop vfnmsub213ps_avx512f ; -:VFNMSUB213PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFNMSUB213PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xAE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9205,7 +9205,7 @@ define pcodeop vfnmsub213ps_avx512f ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105824 define pcodeop vfnmsub231ps_avx512f ; -:VFNMSUB231PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VFNMSUB231PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0xBE; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vfnmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9216,7 +9216,7 @@ define pcodeop vfnmsub231ps_avx512f ; # VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106135 define pcodeop vfnmsub132sd_avx512f ; -:VFNMSUB132SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFNMSUB132SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmsub132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -9227,7 +9227,7 @@ define pcodeop vfnmsub132sd_avx512f ; # VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106138 define pcodeop vfnmsub213sd_avx512f ; -:VFNMSUB213SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFNMSUB213SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmsub213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -9238,7 +9238,7 @@ define pcodeop vfnmsub213sd_avx512f ; # VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106141 define pcodeop vfnmsub231sd_avx512f ; -:VFNMSUB231SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VFNMSUB231SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmsub231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -9249,7 +9249,7 @@ define pcodeop vfnmsub231sd_avx512f ; # VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106307 define pcodeop vfnmsub132ss_avx512f ; -:VFNMSUB132SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFNMSUB132SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmsub132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9260,7 +9260,7 @@ define pcodeop vfnmsub132ss_avx512f ; # VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106310 define pcodeop vfnmsub213ss_avx512f ; -:VFNMSUB213SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFNMSUB213SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmsub213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9271,7 +9271,7 @@ define pcodeop vfnmsub213ss_avx512f ; # VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106313 define pcodeop vfnmsub231ss_avx512f ; -:VFNMSUB231SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VFNMSUB231SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vfnmsub231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9347,7 +9347,7 @@ define pcodeop vfpclassss_avx512dq ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107357 # WARNING: did not recognize qualifier /vsib for "VGATHERDPS xmm1 {k1}, vm32x" define pcodeop vgatherdps_avx512vl ; -:VGATHERDPS XmmReg1 XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32 +:VGATHERDPS XmmReg1^XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgatherdps_avx512vl( m32 ); @@ -9358,7 +9358,7 @@ define pcodeop vgatherdps_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107359 # WARNING: did not recognize qualifier /vsib for "VGATHERDPS ymm1 {k1}, vm32y" -:VGATHERDPS YmmReg1 YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32 +:VGATHERDPS YmmReg1^YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vgatherdps_avx512vl( m32 ); @@ -9370,7 +9370,7 @@ define pcodeop vgatherdps_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107361 # WARNING: did not recognize qualifier /vsib for "VGATHERDPS zmm1 {k1}, vm32z" define pcodeop vgatherdps_avx512f ; -:VGATHERDPS ZmmReg1 ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (ZmmReg1 & ZmmOpMask32) ... & m32 +:VGATHERDPS ZmmReg1^ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x92; (ZmmReg1 & ZmmOpMask32) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vgatherdps_avx512f( m32 ); @@ -9382,7 +9382,7 @@ define pcodeop vgatherdps_avx512f ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107363 # WARNING: did not recognize qualifier /vsib for "VGATHERDPD xmm1 {k1}, vm32x" define pcodeop vgatherdpd_avx512vl ; -:VGATHERDPD XmmReg1 XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32 +:VGATHERDPD XmmReg1^XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgatherdpd_avx512vl( m32 ); @@ -9393,7 +9393,7 @@ define pcodeop vgatherdpd_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107366 # WARNING: did not recognize qualifier /vsib for "VGATHERDPD ymm1 {k1}, vm32x" -:VGATHERDPD YmmReg1 YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32 +:VGATHERDPD YmmReg1^YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vgatherdpd_avx512vl( m32 ); @@ -9405,7 +9405,7 @@ define pcodeop vgatherdpd_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107369 # WARNING: did not recognize qualifier /vsib for "VGATHERDPD zmm1 {k1}, vm32y" define pcodeop vgatherdpd_avx512f ; -:VGATHERDPD ZmmReg1 ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (ZmmReg1 & ZmmOpMask64) ... & m32 +:VGATHERDPD ZmmReg1^ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x92; (ZmmReg1 & ZmmOpMask64) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vgatherdpd_avx512f( m32 ); @@ -9417,7 +9417,7 @@ define pcodeop vgatherdpd_avx512f ; # VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107497 # WARNING: did not recognize qualifier /vsib for "VGATHERPF0DPS vm32z {k1}" define pcodeop vgatherpf0dps_avx512pf ; -:VGATHERPF0DPS m32 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32 +:VGATHERPF0DPS m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf0dps_avx512pf( m32, XmmOpMask ); @@ -9427,7 +9427,7 @@ define pcodeop vgatherpf0dps_avx512pf ; # VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107500 # WARNING: did not recognize qualifier /vsib for "VGATHERPF0QPS vm64z {k1}" define pcodeop vgatherpf0qps_avx512pf ; -:VGATHERPF0QPS m64 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64 +:VGATHERPF0QPS m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf0qps_avx512pf( m64, XmmOpMask ); @@ -9437,7 +9437,7 @@ define pcodeop vgatherpf0qps_avx512pf ; # VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107503 # WARNING: did not recognize qualifier /vsib for "VGATHERPF0DPD vm32y {k1}" define pcodeop vgatherpf0dpd_avx512pf ; -:VGATHERPF0DPD m32 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32 +:VGATHERPF0DPD m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf0dpd_avx512pf( m32, XmmOpMask ); @@ -9447,7 +9447,7 @@ define pcodeop vgatherpf0dpd_avx512pf ; # VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD 5-264 PAGE 2088 LINE 107506 # WARNING: did not recognize qualifier /vsib for "VGATHERPF0QPD vm64z {k1}" define pcodeop vgatherpf0qpd_avx512pf ; -:VGATHERPF0QPD m64 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64 +:VGATHERPF0QPD m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf0qpd_avx512pf( m64, XmmOpMask ); @@ -9457,7 +9457,7 @@ define pcodeop vgatherpf0qpd_avx512pf ; # VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107620 # WARNING: did not recognize qualifier /vsib for "VGATHERPF1DPS vm32z {k1}" define pcodeop vgatherpf1dps_avx512pf ; -:VGATHERPF1DPS m32 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32 +:VGATHERPF1DPS m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf1dps_avx512pf( m32 , XmmOpMask); @@ -9467,7 +9467,7 @@ define pcodeop vgatherpf1dps_avx512pf ; # VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107623 # WARNING: did not recognize qualifier /vsib for "VGATHERPF1QPS vm64z {k1}" define pcodeop vgatherpf1qps_avx512pf ; -:VGATHERPF1QPS m64 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64 +:VGATHERPF1QPS m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf1qps_avx512pf( m64, XmmOpMask ); @@ -9477,7 +9477,7 @@ define pcodeop vgatherpf1qps_avx512pf ; # VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107626 # WARNING: did not recognize qualifier /vsib for "VGATHERPF1DPD vm32y {k1}" define pcodeop vgatherpf1dpd_avx512pf ; -:VGATHERPF1DPD m32 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32 +:VGATHERPF1DPD m32^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC6; reg_opcode=2 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf1dpd_avx512pf( m32, XmmOpMask ); @@ -9487,7 +9487,7 @@ define pcodeop vgatherpf1dpd_avx512pf ; # VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD 5-267 PAGE 2091 LINE 107629 # WARNING: did not recognize qualifier /vsib for "VGATHERPF1QPD vm64z {k1}" define pcodeop vgatherpf1qpd_avx512pf ; -:VGATHERPF1QPD m64 XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64 +:VGATHERPF1QPD m64^XmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xC7; reg_opcode=2 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vgatherpf1qpd_avx512pf( m64, XmmOpMask ); @@ -9497,7 +9497,7 @@ define pcodeop vgatherpf1qpd_avx512pf ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107742 # WARNING: did not recognize qualifier /vsib for "VGATHERQPS xmm1 {k1}, vm64x" define pcodeop vgatherqps_avx512vl ; -:VGATHERQPS XmmReg1 XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 +:VGATHERQPS XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgatherqps_avx512vl( m64 ); @@ -9508,7 +9508,7 @@ define pcodeop vgatherqps_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107745 # WARNING: did not recognize qualifier /vsib for "VGATHERQPS xmm1 {k1}, vm64y" -:VGATHERQPS XmmReg1 XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 +:VGATHERQPS XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgatherqps_avx512vl( m64 ); @@ -9520,7 +9520,7 @@ define pcodeop vgatherqps_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107748 # WARNING: did not recognize qualifier /vsib for "VGATHERQPS ymm1 {k1}, vm64z" define pcodeop vgatherqps_avx512f ; -:VGATHERQPS YmmReg1 YmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64 +:VGATHERQPS YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vgatherqps_avx512f( m64 ); @@ -9532,7 +9532,7 @@ define pcodeop vgatherqps_avx512f ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107751 # WARNING: did not recognize qualifier /vsib for "VGATHERQPD xmm1 {k1}, vm64x" define pcodeop vgatherqpd_avx512vl ; -:VGATHERQPD XmmReg1 XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 +:VGATHERQPD XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgatherqpd_avx512vl( m64 ); @@ -9543,7 +9543,7 @@ define pcodeop vgatherqpd_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107753 # WARNING: did not recognize qualifier /vsib for "VGATHERQPD ymm1 {k1}, vm64y" -:VGATHERQPD YmmReg1 YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64 +:VGATHERQPD YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vgatherqpd_avx512vl( m64 ); @@ -9555,7 +9555,7 @@ define pcodeop vgatherqpd_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107755 # WARNING: did not recognize qualifier /vsib for "VGATHERQPD zmm1 {k1}, vm64z" define pcodeop vgatherqpd_avx512f ; -:VGATHERQPD ZmmReg1 ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (ZmmReg1 & ZmmOpMask64) ... & m64 +:VGATHERQPD ZmmReg1^ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x93; (ZmmReg1 & ZmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vgatherqpd_avx512f( m64 ); @@ -9567,7 +9567,7 @@ define pcodeop vgatherqpd_avx512f ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108099 # WARNING: did not recognize qualifier /vsib for "VPGATHERDD xmm1 {k1}, vm32x" define pcodeop vpgatherdd_avx512vl ; -:VPGATHERDD XmmReg1 XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32 +:VPGATHERDD XmmReg1^XmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpgatherdd_avx512vl( m32 ); @@ -9578,7 +9578,7 @@ define pcodeop vpgatherdd_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108101 # WARNING: did not recognize qualifier /vsib for "VPGATHERDD ymm1 {k1}, vm32y" -:VPGATHERDD YmmReg1 YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32 +:VPGATHERDD YmmReg1^YmmOpMask32, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpgatherdd_avx512vl( m32 ); @@ -9590,7 +9590,7 @@ define pcodeop vpgatherdd_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108103 # WARNING: did not recognize qualifier /vsib for "VPGATHERDD zmm1 {k1}, vm32z" define pcodeop vpgatherdd_avx512f ; -:VPGATHERDD ZmmReg1 ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (ZmmReg1 & ZmmOpMask32) ... & m32 +:VPGATHERDD ZmmReg1^ZmmOpMask32, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x90; (ZmmReg1 & ZmmOpMask32) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpgatherdd_avx512f( m32 ); @@ -9602,7 +9602,7 @@ define pcodeop vpgatherdd_avx512f ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108105 # WARNING: did not recognize qualifier /vsib for "VPGATHERDQ xmm1 {k1}, vm32x" define pcodeop vpgatherdq_avx512vl ; -:VPGATHERDQ XmmReg1 XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32 +:VPGATHERDQ XmmReg1^XmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpgatherdq_avx512vl( m32 ); @@ -9613,7 +9613,7 @@ define pcodeop vpgatherdq_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108107 # WARNING: did not recognize qualifier /vsib for "VPGATHERDQ ymm1 {k1}, vm32x" -:VPGATHERDQ YmmReg1 YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32 +:VPGATHERDQ YmmReg1^YmmOpMask64, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpgatherdq_avx512vl( m32 ); @@ -9625,7 +9625,7 @@ define pcodeop vpgatherdq_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108109 # WARNING: did not recognize qualifier /vsib for "VPGATHERDQ zmm1 {k1}, vm32y" define pcodeop vpgatherdq_avx512f ; -:VPGATHERDQ ZmmReg1 ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (ZmmReg1 & ZmmOpMask64) ... & m32 +:VPGATHERDQ ZmmReg1^ZmmOpMask64, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x90; (ZmmReg1 & ZmmOpMask64) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpgatherdq_avx512f( m32 ); @@ -9637,7 +9637,7 @@ define pcodeop vpgatherdq_avx512f ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108457 # WARNING: did not recognize qualifier /vsib for "VPGATHERQD xmm1 {k1}, vm64x" define pcodeop vpgatherqd_avx512vl ; -:VPGATHERQD XmmReg1 XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64 +:VPGATHERQD XmmReg1^XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpgatherqd_avx512vl( m64 ); @@ -9648,7 +9648,7 @@ define pcodeop vpgatherqd_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108459 # WARNING: did not recognize qualifier /vsib for "VPGATHERQD xmm1 {k1}, vm64y" -:VPGATHERQD XmmReg1 XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64 +:VPGATHERQD XmmReg1^XmmOpMask32, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpgatherqd_avx512vl( m64 ); @@ -9660,7 +9660,7 @@ define pcodeop vpgatherqd_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108461 # WARNING: did not recognize qualifier /vsib for "VPGATHERQD ymm1 {k1}, vm64z" define pcodeop vpgatherqd_avx512f ; -:VPGATHERQD YmmReg1 YmmOpMask32, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m64 +:VPGATHERQD YmmReg1^YmmOpMask32, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpgatherqd_avx512f( m64 ); @@ -9672,7 +9672,7 @@ define pcodeop vpgatherqd_avx512f ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108463 # WARNING: did not recognize qualifier /vsib for "VPGATHERQQ xmm1 {k1}, vm64x" define pcodeop vpgatherqq_avx512vl ; -:VPGATHERQQ XmmReg1 XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 +:VPGATHERQQ XmmReg1^XmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpgatherqq_avx512vl( m64 ); @@ -9683,7 +9683,7 @@ define pcodeop vpgatherqq_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108465 # WARNING: did not recognize qualifier /vsib for "VPGATHERQQ ymm1 {k1}, vm64y" -:VPGATHERQQ YmmReg1 YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64 +:VPGATHERQQ YmmReg1^YmmOpMask64, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpgatherqq_avx512vl( m64 ); @@ -9695,7 +9695,7 @@ define pcodeop vpgatherqq_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108467 # WARNING: did not recognize qualifier /vsib for "VPGATHERQQ zmm1 {k1}, vm64z" define pcodeop vpgatherqq_avx512f ; -:VPGATHERQQ ZmmReg1 ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (ZmmReg1 & ZmmOpMask64) ... & m64 +:VPGATHERQQ ZmmReg1^ZmmOpMask64, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x91; (ZmmReg1 & ZmmOpMask64) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpgatherqq_avx512f( m64 ); @@ -9706,7 +9706,7 @@ define pcodeop vpgatherqq_avx512f ; # VGETEXPPD 5-288 PAGE 2112 LINE 108594 define pcodeop vgetexppd_avx512vl ; -:VGETEXPPD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VGETEXPPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vgetexppd_avx512vl( XmmReg2_m128_m64bcst ); @@ -9716,7 +9716,7 @@ define pcodeop vgetexppd_avx512vl ; } # VGETEXPPD 5-288 PAGE 2112 LINE 108598 -:VGETEXPPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VGETEXPPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vgetexppd_avx512vl( YmmReg2_m256_m64bcst ); @@ -9727,7 +9727,7 @@ define pcodeop vgetexppd_avx512vl ; # VGETEXPPD 5-288 PAGE 2112 LINE 108602 define pcodeop vgetexppd_avx512f ; -:VGETEXPPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VGETEXPPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x42; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vgetexppd_avx512f( ZmmReg2_m512_m64bcst ); @@ -9738,7 +9738,7 @@ define pcodeop vgetexppd_avx512f ; # VGETEXPPS 5-291 PAGE 2115 LINE 108760 define pcodeop vgetexpps_avx512vl ; -:VGETEXPPS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VGETEXPPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vgetexpps_avx512vl( XmmReg2_m128_m32bcst ); @@ -9748,7 +9748,7 @@ define pcodeop vgetexpps_avx512vl ; } # VGETEXPPS 5-291 PAGE 2115 LINE 108764 -:VGETEXPPS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VGETEXPPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vgetexpps_avx512vl( YmmReg2_m256_m32bcst ); @@ -9759,7 +9759,7 @@ define pcodeop vgetexpps_avx512vl ; # VGETEXPPS 5-291 PAGE 2115 LINE 108768 define pcodeop vgetexpps_avx512f ; -:VGETEXPPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VGETEXPPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x42; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vgetexpps_avx512f( ZmmReg2_m512_m32bcst ); @@ -9770,7 +9770,7 @@ define pcodeop vgetexpps_avx512f ; # VGETEXPSD 5-295 PAGE 2119 LINE 108959 define pcodeop vgetexpsd_avx512f ; -:VGETEXPSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VGETEXPSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgetexpsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -9781,7 +9781,7 @@ define pcodeop vgetexpsd_avx512f ; # VGETEXPSS 5-297 PAGE 2121 LINE 109037 define pcodeop vgetexpss_avx512f ; -:VGETEXPSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VGETEXPSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgetexpss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9792,7 +9792,7 @@ define pcodeop vgetexpss_avx512f ; # VGETMANTPD 5-299 PAGE 2123 LINE 109120 define pcodeop vgetmantpd_avx512vl ; -:VGETMANTPD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VGETMANTPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vgetmantpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -9802,7 +9802,7 @@ define pcodeop vgetmantpd_avx512vl ; } # VGETMANTPD 5-299 PAGE 2123 LINE 109125 -:VGETMANTPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VGETMANTPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vgetmantpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -9813,7 +9813,7 @@ define pcodeop vgetmantpd_avx512vl ; # VGETMANTPD 5-299 PAGE 2123 LINE 109130 define pcodeop vgetmantpd_avx512f ; -:VGETMANTPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VGETMANTPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x26; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vgetmantpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -9824,7 +9824,7 @@ define pcodeop vgetmantpd_avx512f ; # VGETMANTPS 5-303 PAGE 2127 LINE 109339 define pcodeop vgetmantps_avx512vl ; -:VGETMANTPS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VGETMANTPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { XmmResult = vgetmantps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -9834,7 +9834,7 @@ define pcodeop vgetmantps_avx512vl ; } # VGETMANTPS 5-303 PAGE 2127 LINE 109344 -:VGETMANTPS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VGETMANTPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { YmmResult = vgetmantps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -9845,7 +9845,7 @@ define pcodeop vgetmantps_avx512vl ; # VGETMANTPS 5-303 PAGE 2127 LINE 109349 define pcodeop vgetmantps_avx512f ; -:VGETMANTPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VGETMANTPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x26; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmResult = vgetmantps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -9856,7 +9856,7 @@ define pcodeop vgetmantps_avx512f ; # VGETMANTSD 5-306 PAGE 2130 LINE 109519 define pcodeop vgetmantsd_avx512f ; -:VGETMANTSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VGETMANTSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgetmantsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -9867,7 +9867,7 @@ define pcodeop vgetmantsd_avx512f ; # VGETMANTSS 5-308 PAGE 2132 LINE 109610 define pcodeop vgetmantss_avx512f ; -:VGETMANTSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VGETMANTSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vgetmantss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -9878,7 +9878,7 @@ define pcodeop vgetmantss_avx512f ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109706 define pcodeop vinsertf32x4_avx512vl ; -:VINSERTF32X4 YmmReg1 YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8 +:VINSERTF32X4 YmmReg1^YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vinsertf32x4_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -9889,7 +9889,7 @@ define pcodeop vinsertf32x4_avx512vl ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109709 define pcodeop vinsertf32x4_avx512f ; -:VINSERTF32X4 ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8 +:VINSERTF32X4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinsertf32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -9900,7 +9900,7 @@ define pcodeop vinsertf32x4_avx512f ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109712 define pcodeop vinsertf64x2_avx512vl ; -:VINSERTF64X2 YmmReg1 YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8 +:VINSERTF64X2 YmmReg1^YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vinsertf64x2_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -9911,7 +9911,7 @@ define pcodeop vinsertf64x2_avx512vl ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109715 define pcodeop vinsertf64x2_avx512dq ; -:VINSERTF64X2 ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8 +:VINSERTF64X2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x18; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinsertf64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -9922,7 +9922,7 @@ define pcodeop vinsertf64x2_avx512dq ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109718 define pcodeop vinsertf32x8_avx512dq ; -:VINSERTF32X8 ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8 +:VINSERTF32X8 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinsertf32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -9933,7 +9933,7 @@ define pcodeop vinsertf32x8_avx512dq ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109721 define pcodeop vinsertf64x4_avx512f ; -:VINSERTF64X4 ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8 +:VINSERTF64X4 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x1A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinsertf64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -9944,7 +9944,7 @@ define pcodeop vinsertf64x4_avx512f ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109930 define pcodeop vinserti32x4_avx512vl ; -:VINSERTI32X4 YmmReg1 YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8 +:VINSERTI32X4 YmmReg1^YmmOpMask32, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vinserti32x4_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -9955,7 +9955,7 @@ define pcodeop vinserti32x4_avx512vl ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109933 define pcodeop vinserti32x4_avx512f ; -:VINSERTI32X4 ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8 +:VINSERTI32X4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinserti32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -9966,7 +9966,7 @@ define pcodeop vinserti32x4_avx512f ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109936 define pcodeop vinserti64x2_avx512vl ; -:VINSERTI64X2 YmmReg1 YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8 +:VINSERTI64X2 YmmReg1^YmmOpMask64, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmResult = vinserti64x2_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -9977,7 +9977,7 @@ define pcodeop vinserti64x2_avx512vl ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109939 define pcodeop vinserti64x2_avx512dq ; -:VINSERTI64X2 ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8 +:VINSERTI64X2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x38; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinserti64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -9988,7 +9988,7 @@ define pcodeop vinserti64x2_avx512dq ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109942 define pcodeop vinserti32x8_avx512dq ; -:VINSERTI32X8 ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8 +:VINSERTI32X8 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask32) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinserti32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -9999,7 +9999,7 @@ define pcodeop vinserti32x8_avx512dq ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109945 define pcodeop vinserti64x4_avx512f ; -:VINSERTI64X4 ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8 +:VINSERTI64X4 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x3A; (ZmmReg1 & ZmmOpMask64) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmResult = vinserti64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -10010,7 +10010,7 @@ define pcodeop vinserti64x4_avx512f ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110393 define pcodeop vpblendmb_avx512vl ; -:VPBLENDMB XmmReg1 XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 +:VPBLENDMB XmmReg1^XmmOpMask8, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpblendmb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -10020,7 +10020,7 @@ define pcodeop vpblendmb_avx512vl ; } # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110396 -:VPBLENDMB YmmReg1 YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 +:VPBLENDMB YmmReg1^YmmOpMask8, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpblendmb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10031,7 +10031,7 @@ define pcodeop vpblendmb_avx512vl ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110399 define pcodeop vpblendmb_avx512bw ; -:VPBLENDMB ZmmReg1 ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 +:VPBLENDMB ZmmReg1^ZmmOpMask8, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask8) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpblendmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10042,7 +10042,7 @@ define pcodeop vpblendmb_avx512bw ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110402 define pcodeop vpblendmw_avx512vl ; -:VPBLENDMW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPBLENDMW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpblendmw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -10052,7 +10052,7 @@ define pcodeop vpblendmw_avx512vl ; } # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110405 -:VPBLENDMW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPBLENDMW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpblendmw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10063,7 +10063,7 @@ define pcodeop vpblendmw_avx512vl ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110408 define pcodeop vpblendmw_avx512bw ; -:VPBLENDMW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPBLENDMW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x66; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpblendmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10074,7 +10074,7 @@ define pcodeop vpblendmw_avx512bw ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110495 define pcodeop vpblendmd_avx512vl ; -:VPBLENDMD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPBLENDMD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpblendmd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -10084,7 +10084,7 @@ define pcodeop vpblendmd_avx512vl ; } # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110498 -:VPBLENDMD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPBLENDMD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpblendmd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10095,7 +10095,7 @@ define pcodeop vpblendmd_avx512vl ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110501 define pcodeop vpblendmd_avx512f ; -:VPBLENDMD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPBLENDMD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpblendmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10106,7 +10106,7 @@ define pcodeop vpblendmd_avx512f ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110504 define pcodeop vpblendmq_avx512vl ; -:VPBLENDMQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPBLENDMQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpblendmq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -10116,7 +10116,7 @@ define pcodeop vpblendmq_avx512vl ; } # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110507 -:VPBLENDMQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPBLENDMQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpblendmq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10127,7 +10127,7 @@ define pcodeop vpblendmq_avx512vl ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110510 define pcodeop vpblendmq_avx512f ; -:VPBLENDMQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPBLENDMQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x64; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpblendmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10140,7 +10140,7 @@ define pcodeop vpblendmq_avx512f ; # WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTB xmm1 {k1}{z}, reg" #TODO: fix define pcodeop vpbroadcastb_avx512vl ; -:VPBROADCASTB XmmReg1 XmmOpMask8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask8) +:VPBROADCASTB XmmReg1^XmmOpMask8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (XmmReg1 & ZmmReg1 & XmmOpMask8) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpbroadcastb_avx512vl( ); @@ -10150,7 +10150,7 @@ define pcodeop vpbroadcastb_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110619 # WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTB ymm1 {k1}{z}, reg" -:VPBROADCASTB YmmReg1 YmmOpMask8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask8) +:VPBROADCASTB YmmReg1^YmmOpMask8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; (YmmReg1 & ZmmReg1 & YmmOpMask8) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpbroadcastb_avx512vl( ); @@ -10162,7 +10162,7 @@ define pcodeop vpbroadcastb_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110621 # WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTB zmm1 {k1}{z}, reg" define pcodeop vpbroadcastb_avx512bw ; -:VPBROADCASTB ZmmReg1 ZmmOpMask8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; ZmmReg1 & ZmmOpMask8 +:VPBROADCASTB ZmmReg1^ZmmOpMask8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7A; ZmmReg1 & ZmmOpMask8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpbroadcastb_avx512bw( ); @@ -10174,7 +10174,7 @@ define pcodeop vpbroadcastb_avx512bw ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110623 # WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTW xmm1 {k1}{z}, reg" define pcodeop vpbroadcastw_avx512vl ; -:VPBROADCASTW XmmReg1 XmmOpMask16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask16) +:VPBROADCASTW XmmReg1^XmmOpMask16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (XmmReg1 & ZmmReg1 & XmmOpMask16) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpbroadcastw_avx512vl( ); @@ -10185,7 +10185,7 @@ define pcodeop vpbroadcastw_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110625 # WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTW ymm1 {k1}{z}, reg" -:VPBROADCASTW YmmReg1 YmmOpMask16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask16) +:VPBROADCASTW YmmReg1^YmmOpMask16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; (YmmReg1 & ZmmReg1 & YmmOpMask16) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpbroadcastw_avx512vl( ); @@ -10197,7 +10197,7 @@ define pcodeop vpbroadcastw_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110627 # WARNING: did not recognize operand "reg" (encoding ModRM:r/m (r)) for "VPBROADCASTW zmm1 {k1}{z}, reg" define pcodeop vpbroadcastw_avx512bw ; -:VPBROADCASTW ZmmReg1 ZmmOpMask16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; ZmmReg1 & ZmmOpMask16 +:VPBROADCASTW ZmmReg1^ZmmOpMask16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7B; ZmmReg1 & ZmmOpMask16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpbroadcastw_avx512bw( ); @@ -10209,7 +10209,7 @@ define pcodeop vpbroadcastw_avx512bw ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110629 # WARNING: did not recognize operand "r32" (encoding ModRM:r/m (r)) for "VPBROADCASTD xmm1 {k1}{z}, r32" define pcodeop vpbroadcastd_avx512vl ; -:VPBROADCASTD XmmReg1 XmmOpMask32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask32) +:VPBROADCASTD XmmReg1^XmmOpMask32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask32) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpbroadcastd_avx512vl( ); @@ -10220,7 +10220,7 @@ define pcodeop vpbroadcastd_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110631 # WARNING: did not recognize operand "r32" (encoding ModRM:r/m (r)) for "VPBROADCASTD ymm1 {k1}{z}, r32" -:VPBROADCASTD YmmReg1 YmmOpMask32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask32) +:VPBROADCASTD YmmReg1^YmmOpMask32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask32) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpbroadcastd_avx512vl( ); @@ -10232,7 +10232,7 @@ define pcodeop vpbroadcastd_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110633 # WARNING: did not recognize operand "r32" (encoding ModRM:r/m (r)) for "VPBROADCASTD zmm1 {k1}{z}, r32" define pcodeop vpbroadcastd_avx512f ; -:VPBROADCASTD ZmmReg1 ZmmOpMask32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; ZmmReg1 & ZmmOpMask32 +:VPBROADCASTD ZmmReg1^ZmmOpMask32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x7C; ZmmReg1 & ZmmOpMask32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpbroadcastd_avx512f( ); @@ -10245,7 +10245,7 @@ define pcodeop vpbroadcastd_avx512f ; # WARNING: did not recognize operand "r64" (encoding ModRM:r/m (r)) for "VPBROADCASTQ xmm1 {k1}{z}, r64" define pcodeop vpbroadcastq_avx512vl ; @ifdef IA64 -:VPBROADCASTQ XmmReg1 XmmOpMask64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask64) +:VPBROADCASTQ XmmReg1^XmmOpMask64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (XmmReg1 & ZmmReg1 & XmmOpMask64) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpbroadcastq_avx512vl( ); @@ -10258,7 +10258,7 @@ define pcodeop vpbroadcastq_avx512vl ; # VPBROADCASTB/W/D/Q 5-328 PAGE 2152 LINE 110637 # WARNING: did not recognize operand "r64" (encoding ModRM:r/m (r)) for "VPBROADCASTQ ymm1 {k1}{z}, r64" @ifdef IA64 -:VPBROADCASTQ YmmReg1 YmmOpMask64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask64) +:VPBROADCASTQ YmmReg1^YmmOpMask64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; (YmmReg1 & ZmmReg1 & YmmOpMask64) [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpbroadcastq_avx512vl( ); @@ -10272,7 +10272,7 @@ define pcodeop vpbroadcastq_avx512vl ; # WARNING: did not recognize operand "r64" (encoding ModRM:r/m (r)) for "VPBROADCASTQ zmm1 {k1}{z}, r64" define pcodeop vpbroadcastq_avx512f ; @ifdef IA64 -:VPBROADCASTQ ZmmReg1 ZmmOpMask64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; ZmmReg1 & ZmmOpMask64 +:VPBROADCASTQ ZmmReg1^ZmmOpMask64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1); byte=0x7C; ZmmReg1 & ZmmOpMask64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpbroadcastq_avx512f( ); @@ -10283,7 +10283,7 @@ define pcodeop vpbroadcastq_avx512f ; @endif # VPBROADCAST 5-331 PAGE 2155 LINE 110780 -:VPBROADCASTB XmmReg1 XmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m8 +:VPBROADCASTB XmmReg1^XmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (XmmReg1 & ZmmReg1 & XmmOpMask8) ... & XmmReg2_m8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { XmmResult = vpbroadcastb_avx512vl( XmmReg2_m8 ); @@ -10293,7 +10293,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110782 -:VPBROADCASTB YmmReg1 YmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & XmmReg2_m8 +:VPBROADCASTB YmmReg1^YmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (YmmReg1 & ZmmReg1 & YmmOpMask8) ... & XmmReg2_m8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vpbroadcastb_avx512vl( XmmReg2_m8 ); @@ -10303,7 +10303,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110784 -:VPBROADCASTB ZmmReg1 ZmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask8) ... & XmmReg2_m8 +:VPBROADCASTB ZmmReg1^ZmmOpMask8, XmmReg2_m8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x78; (ZmmReg1 & ZmmOpMask8) ... & XmmReg2_m8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vpbroadcastb_avx512bw( XmmReg2_m8 ); @@ -10313,7 +10313,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110791 -:VPBROADCASTW XmmReg1 XmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m16 +:VPBROADCASTW XmmReg1^XmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { XmmResult = vpbroadcastw_avx512vl( XmmReg2_m16 ); @@ -10323,7 +10323,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110794 -:VPBROADCASTW YmmReg1 YmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m16 +:VPBROADCASTW YmmReg1^YmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vpbroadcastw_avx512vl( XmmReg2_m16 ); @@ -10333,7 +10333,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110797 -:VPBROADCASTW ZmmReg1 ZmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m16 +:VPBROADCASTW ZmmReg1^ZmmOpMask16, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x79; (ZmmReg1 & ZmmOpMask16) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vpbroadcastw_avx512bw( XmmReg2_m16 ); @@ -10343,7 +10343,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110804 -:VPBROADCASTD XmmReg1 XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VPBROADCASTD XmmReg1^XmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { XmmResult = vpbroadcastd_avx512vl( XmmReg2_m32 ); @@ -10353,7 +10353,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110807 -:VPBROADCASTD YmmReg1 YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32 +:VPBROADCASTD YmmReg1^YmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vpbroadcastd_avx512vl( XmmReg2_m32 ); @@ -10363,7 +10363,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110810 -:VPBROADCASTD ZmmReg1 ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32 +:VPBROADCASTD ZmmReg1^ZmmOpMask32, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x58; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vpbroadcastd_avx512f( XmmReg2_m32 ); @@ -10373,7 +10373,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110817 -:VPBROADCASTQ XmmReg1 XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VPBROADCASTQ XmmReg1^XmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { XmmResult = vpbroadcastq_avx512vl( XmmReg2_m64 ); @@ -10383,7 +10383,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110819 -:VPBROADCASTQ YmmReg1 YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 +:VPBROADCASTQ YmmReg1^YmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vpbroadcastq_avx512vl( XmmReg2_m64 ); @@ -10393,7 +10393,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110821 -:VPBROADCASTQ ZmmReg1 ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 +:VPBROADCASTQ ZmmReg1^ZmmOpMask64, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x59; (ZmmReg1 & ZmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vpbroadcastq_avx512f( XmmReg2_m64 ); @@ -10404,7 +10404,7 @@ define pcodeop vpbroadcastq_avx512f ; # VPBROADCAST 5-331 PAGE 2155 LINE 110823 define pcodeop vbroadcasti32x2_avx512vl ; -:VBROADCASTI32x2 XmmReg1 XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 +:VBROADCASTI32x2 XmmReg1^XmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { XmmResult = vbroadcasti32x2_avx512vl( XmmReg2_m64 ); @@ -10414,7 +10414,7 @@ define pcodeop vbroadcasti32x2_avx512vl ; } # VPBROADCAST 5-332 PAGE 2156 LINE 110837 -:VBROADCASTI32x2 YmmReg1 YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 +:VBROADCASTI32x2 YmmReg1^YmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcasti32x2_avx512vl( XmmReg2_m64 ); @@ -10425,7 +10425,7 @@ define pcodeop vbroadcasti32x2_avx512vl ; # VPBROADCAST 5-332 PAGE 2156 LINE 110840 define pcodeop vbroadcasti32x2_avx512dq ; -:VBROADCASTI32x2 ZmmReg1 ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64 +:VBROADCASTI32x2 ZmmReg1^ZmmOpMask32, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x59; (ZmmReg1 & ZmmOpMask32) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcasti32x2_avx512dq( XmmReg2_m64 ); @@ -10436,7 +10436,7 @@ define pcodeop vbroadcasti32x2_avx512dq ; # VPBROADCAST 5-332 PAGE 2156 LINE 110845 define pcodeop vbroadcasti32x4_avx512vl ; -:VBROADCASTI32X4 YmmReg1 YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128 +:VBROADCASTI32X4 YmmReg1^YmmOpMask32, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcasti32x4_avx512vl( m128 ); @@ -10447,7 +10447,7 @@ define pcodeop vbroadcasti32x4_avx512vl ; # VPBROADCAST 5-332 PAGE 2156 LINE 110848 define pcodeop vbroadcasti32x4_avx512f ; -:VBROADCASTI32X4 ZmmReg1 ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask32) ... & m128 +:VBROADCASTI32X4 ZmmReg1^ZmmOpMask32, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5A; (ZmmReg1 & ZmmOpMask32) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcasti32x4_avx512f( m128 ); @@ -10458,7 +10458,7 @@ define pcodeop vbroadcasti32x4_avx512f ; # VPBROADCAST 5-332 PAGE 2156 LINE 110851 define pcodeop vbroadcasti64x2_avx512vl ; -:VBROADCASTI64X2 YmmReg1 YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128 +:VBROADCASTI64X2 YmmReg1^YmmOpMask64, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { YmmResult = vbroadcasti64x2_avx512vl( m128 ); @@ -10469,7 +10469,7 @@ define pcodeop vbroadcasti64x2_avx512vl ; # VPBROADCAST 5-332 PAGE 2156 LINE 110854 define pcodeop vbroadcasti64x2_avx512dq ; -:VBROADCASTI64X2 ZmmReg1 ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & m128 +:VBROADCASTI64X2 ZmmReg1^ZmmOpMask64, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5A; (ZmmReg1 & ZmmOpMask64) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcasti64x2_avx512dq( m128 ); @@ -10480,7 +10480,7 @@ define pcodeop vbroadcasti64x2_avx512dq ; # VPBROADCAST 5-332 PAGE 2156 LINE 110857 define pcodeop vbroadcasti32x8_avx512dq ; -:VBROADCASTI32X8 ZmmReg1 ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & m256 +:VBROADCASTI32X8 ZmmReg1^ZmmOpMask32, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x5B; (ZmmReg1 & ZmmOpMask32) ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcasti32x8_avx512dq( m256 ); @@ -10491,7 +10491,7 @@ define pcodeop vbroadcasti32x8_avx512dq ; # VPBROADCAST 5-332 PAGE 2156 LINE 110860 define pcodeop vbroadcasti64x4_avx512f ; -:VBROADCASTI64X4 ZmmReg1 ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5B; (ZmmReg1 & ZmmOpMask64) ... & m256 +:VBROADCASTI64X4 ZmmReg1^ZmmOpMask64, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x5B; (ZmmReg1 & ZmmOpMask64) ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmResult = vbroadcasti64x4_avx512f( m256 ); @@ -10711,7 +10711,7 @@ define pcodeop vpcmpuw_avx512bw ; # VPCOMPRESSD 5-351 PAGE 2175 LINE 111873 define pcodeop vpcompressd_avx512vl ; -:VPCOMPRESSD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VPCOMPRESSD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpcompressd_avx512vl( XmmReg1 ); @@ -10720,7 +10720,7 @@ define pcodeop vpcompressd_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPCOMPRESSD m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 ... & m128 +:VPCOMPRESSD m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x8B; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpcompressd_avx512vl( XmmReg1 ); @@ -10730,7 +10730,7 @@ define pcodeop vpcompressd_avx512vl ; } # VPCOMPRESSD 5-351 PAGE 2175 LINE 111875 -:VPCOMPRESSD YmmReg2 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VPCOMPRESSD YmmReg2^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpcompressd_avx512vl( YmmReg1 ); @@ -10739,7 +10739,7 @@ define pcodeop vpcompressd_avx512vl ; ZmmReg2 = zext(YmmResult); } -:VPCOMPRESSD m256 YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 ... & m256 +:VPCOMPRESSD m256^YmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x8B; YmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpcompressd_avx512vl( YmmReg1 ); @@ -10750,7 +10750,7 @@ define pcodeop vpcompressd_avx512vl ; # VPCOMPRESSD 5-351 PAGE 2175 LINE 111877 define pcodeop vpcompressd_avx512f ; -:VPCOMPRESSD ZmmReg2_m512 ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 +:VPCOMPRESSD ZmmReg2_m512^ZmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask32; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpcompressd_avx512f( ZmmReg1 ); @@ -10761,7 +10761,7 @@ define pcodeop vpcompressd_avx512f ; # VPCOMPRESSQ 5-353 PAGE 2177 LINE 111970 define pcodeop vpcompressq_avx512vl ; -:VPCOMPRESSQ XmmReg2 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 +:VPCOMPRESSQ XmmReg2^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 & mod=3 & XmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmReg2 = vpcompressq_avx512vl( XmmReg1 ); @@ -10770,7 +10770,7 @@ define pcodeop vpcompressq_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPCOMPRESSQ m128 XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 ... & m128 +:VPCOMPRESSQ m128^XmmOpMask64, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask64; byte=0x8B; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpcompressq_avx512vl( XmmReg1 ); @@ -10780,7 +10780,7 @@ define pcodeop vpcompressq_avx512vl ; } # VPCOMPRESSQ 5-353 PAGE 2177 LINE 111972 -:VPCOMPRESSQ YmmReg2 YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 +:VPCOMPRESSQ YmmReg2^YmmOpMask64, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask64; byte=0x8B; YmmReg1 & mod=3 & YmmReg2 & ZmmReg2 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpcompressq_avx512vl( YmmReg1 ); @@ -10800,7 +10800,7 @@ define pcodeop vpcompressq_avx512vl ; # VPCOMPRESSQ 5-353 PAGE 2177 LINE 111974 define pcodeop vpcompressq_avx512f ; -:VPCOMPRESSQ ZmmReg2_m512 ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 +:VPCOMPRESSQ ZmmReg2_m512^ZmmOpMask64, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask64; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpcompressq_avx512f( ZmmReg1 ); @@ -10811,7 +10811,7 @@ define pcodeop vpcompressq_avx512f ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112068 define pcodeop vpconflictd_avx512vl ; -:VPCONFLICTD XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPCONFLICTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpconflictd_avx512vl( XmmReg2_m128_m32bcst ); @@ -10821,7 +10821,7 @@ define pcodeop vpconflictd_avx512vl ; } # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112072 -:VPCONFLICTD YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPCONFLICTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpconflictd_avx512vl( YmmReg2_m256_m32bcst ); @@ -10832,7 +10832,7 @@ define pcodeop vpconflictd_avx512vl ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112076 define pcodeop vpconflictd_avx512cd ; -:VPCONFLICTD ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPCONFLICTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xC4; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpconflictd_avx512cd( ZmmReg2_m512_m32bcst ); @@ -10843,7 +10843,7 @@ define pcodeop vpconflictd_avx512cd ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112080 define pcodeop vpconflictq_avx512vl ; -:VPCONFLICTQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPCONFLICTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpconflictq_avx512vl( XmmReg2_m128_m64bcst ); @@ -10853,7 +10853,7 @@ define pcodeop vpconflictq_avx512vl ; } # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112084 -:VPCONFLICTQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPCONFLICTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpconflictq_avx512vl( YmmReg2_m256_m64bcst ); @@ -10864,7 +10864,7 @@ define pcodeop vpconflictq_avx512vl ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112088 define pcodeop vpconflictq_avx512cd ; -:VPCONFLICTQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPCONFLICTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xC4; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpconflictq_avx512cd( ZmmReg2_m512_m64bcst ); @@ -10875,7 +10875,7 @@ define pcodeop vpconflictq_avx512cd ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112407 define pcodeop vpermd_avx512vl ; -:VPERMD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPERMD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpermd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10886,7 +10886,7 @@ define pcodeop vpermd_avx512vl ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112410 define pcodeop vpermd_avx512f ; -:VPERMD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPERMD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpermd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10897,7 +10897,7 @@ define pcodeop vpermd_avx512f ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112413 define pcodeop vpermw_avx512vl ; -:VPERMW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPERMW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpermw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -10907,7 +10907,7 @@ define pcodeop vpermw_avx512vl ; } # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112417 -:VPERMW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPERMW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpermw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10918,7 +10918,7 @@ define pcodeop vpermw_avx512vl ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112421 define pcodeop vpermw_avx512bw ; -:VPERMW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x8D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPERMW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x8D; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpermw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10929,7 +10929,7 @@ define pcodeop vpermw_avx512bw ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112553 define pcodeop vpermi2w_avx512vl ; -:VPERMI2W XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPERMI2W XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpermi2w_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); @@ -10939,7 +10939,7 @@ define pcodeop vpermi2w_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112556 -:VPERMI2W YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPERMI2W YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpermi2w_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10950,7 +10950,7 @@ define pcodeop vpermi2w_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112559 define pcodeop vpermi2w_avx512bw ; -:VPERMI2W ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x75; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPERMI2W ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x75; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpermi2w_avx512bw( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10961,7 +10961,7 @@ define pcodeop vpermi2w_avx512bw ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112562 define pcodeop vpermi2d_avx512vl ; -:VPERMI2D XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPERMI2D XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpermi2d_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -10971,7 +10971,7 @@ define pcodeop vpermi2d_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112566 -:VPERMI2D YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPERMI2D YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpermi2d_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10982,7 +10982,7 @@ define pcodeop vpermi2d_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112570 define pcodeop vpermi2d_avx512f ; -:VPERMI2D ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPERMI2D ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpermi2d_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10993,7 +10993,7 @@ define pcodeop vpermi2d_avx512f ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112574 define pcodeop vpermi2q_avx512vl ; -:VPERMI2Q XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPERMI2Q XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpermi2q_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -11003,7 +11003,7 @@ define pcodeop vpermi2q_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112578 -:VPERMI2Q YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPERMI2Q YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpermi2q_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11014,7 +11014,7 @@ define pcodeop vpermi2q_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112582 define pcodeop vpermi2q_avx512f ; -:VPERMI2Q ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPERMI2Q ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x76; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpermi2q_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11025,7 +11025,7 @@ define pcodeop vpermi2q_avx512f ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112586 define pcodeop vpermi2ps_avx512vl ; -:VPERMI2PS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPERMI2PS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpermi2ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -11035,7 +11035,7 @@ define pcodeop vpermi2ps_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112590 -:VPERMI2PS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPERMI2PS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpermi2ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -11046,7 +11046,7 @@ define pcodeop vpermi2ps_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112594 define pcodeop vpermi2ps_avx512f ; -:VPERMI2PS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPERMI2PS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpermi2ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -11057,7 +11057,7 @@ define pcodeop vpermi2ps_avx512f ; # VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112610 define pcodeop vpermi2pd_avx512vl ; -:VPERMI2PD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPERMI2PD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpermi2pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -11067,7 +11067,7 @@ define pcodeop vpermi2pd_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112614 -:VPERMI2PD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPERMI2PD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpermi2pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11078,7 +11078,7 @@ define pcodeop vpermi2pd_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112618 define pcodeop vpermi2pd_avx512f ; -:VPERMI2PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPERMI2PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x77; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpermi2pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11089,7 +11089,7 @@ define pcodeop vpermi2pd_avx512f ; # VPERMILPD 5-371 PAGE 2195 LINE 112866 define pcodeop vpermilpd_avx512vl ; -:VPERMILPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPERMILPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { XmmResult = vpermilpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -11099,7 +11099,7 @@ define pcodeop vpermilpd_avx512vl ; } # VPERMILPD 5-371 PAGE 2195 LINE 112869 -:VPERMILPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPERMILPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vpermilpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11110,7 +11110,7 @@ define pcodeop vpermilpd_avx512vl ; # VPERMILPD 5-371 PAGE 2195 LINE 112872 define pcodeop vpermilpd_avx512f ; -:VPERMILPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x0D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPERMILPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x0D; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vpermilpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11120,7 +11120,7 @@ define pcodeop vpermilpd_avx512f ; } # VPERMILPD 5-371 PAGE 2195 LINE 112879 -:VPERMILPD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VPERMILPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { XmmResult = vpermilpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -11130,7 +11130,7 @@ define pcodeop vpermilpd_avx512f ; } # VPERMILPD 5-371 PAGE 2195 LINE 112882 -:VPERMILPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VPERMILPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { YmmResult = vpermilpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -11140,7 +11140,7 @@ define pcodeop vpermilpd_avx512f ; } # VPERMILPD 5-371 PAGE 2195 LINE 112885 -:VPERMILPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VPERMILPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x05; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { ZmmResult = vpermilpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -11151,7 +11151,7 @@ define pcodeop vpermilpd_avx512f ; # VPERMILPS 5-376 PAGE 2200 LINE 113170 define pcodeop vpermilps_avx512vl ; -:VPERMILPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPERMILPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { XmmResult = vpermilps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -11161,7 +11161,7 @@ define pcodeop vpermilps_avx512vl ; } # VPERMILPS 5-376 PAGE 2200 LINE 113173 -:VPERMILPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPERMILPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vpermilps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -11172,7 +11172,7 @@ define pcodeop vpermilps_avx512vl ; # VPERMILPS 5-376 PAGE 2200 LINE 113176 define pcodeop vpermilps_avx512f ; -:VPERMILPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x0C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPERMILPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x0C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vpermilps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -11182,7 +11182,7 @@ define pcodeop vpermilps_avx512f ; } # VPERMILPS 5-376 PAGE 2200 LINE 113179 -:VPERMILPS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VPERMILPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { XmmResult = vpermilps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -11192,7 +11192,7 @@ define pcodeop vpermilps_avx512f ; } # VPERMILPS 5-376 PAGE 2200 LINE 113182 -:VPERMILPS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VPERMILPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { YmmResult = vpermilps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -11202,7 +11202,7 @@ define pcodeop vpermilps_avx512f ; } # VPERMILPS 5-376 PAGE 2200 LINE 113186 -:VPERMILPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VPERMILPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x04; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { ZmmResult = vpermilps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -11213,7 +11213,7 @@ define pcodeop vpermilps_avx512f ; # VPERMPD 5-381 PAGE 2205 LINE 113456 define pcodeop vpermpd_avx512vl ; -:VPERMPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VPERMPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { YmmResult = vpermpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -11224,7 +11224,7 @@ define pcodeop vpermpd_avx512vl ; # VPERMPD 5-381 PAGE 2205 LINE 113459 define pcodeop vpermpd_avx512f ; -:VPERMPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VPERMPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x01; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { ZmmResult = vpermpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -11234,7 +11234,7 @@ define pcodeop vpermpd_avx512f ; } # VPERMPD 5-381 PAGE 2205 LINE 113462 -:VPERMPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPERMPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vpermpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11244,7 +11244,7 @@ define pcodeop vpermpd_avx512f ; } # VPERMPD 5-381 PAGE 2205 LINE 113465 -:VPERMPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPERMPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vpermpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11255,7 +11255,7 @@ define pcodeop vpermpd_avx512f ; # VPERMPS 5-384 PAGE 2208 LINE 113636 define pcodeop vpermps_avx512vl ; -:VPERMPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPERMPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpermps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -11266,7 +11266,7 @@ define pcodeop vpermps_avx512vl ; # VPERMPS 5-384 PAGE 2208 LINE 113639 define pcodeop vpermps_avx512f ; -:VPERMPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPERMPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x16; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpermps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -11277,7 +11277,7 @@ define pcodeop vpermps_avx512f ; # VPERMQ 5-387 PAGE 2211 LINE 113771 define pcodeop vpermq_avx512vl ; -:VPERMQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VPERMQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { YmmResult = vpermq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -11288,7 +11288,7 @@ define pcodeop vpermq_avx512vl ; # VPERMQ 5-387 PAGE 2211 LINE 113774 define pcodeop vpermq_avx512f ; -:VPERMQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VPERMQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x00; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { ZmmResult = vpermq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -11298,7 +11298,7 @@ define pcodeop vpermq_avx512f ; } # VPERMQ 5-387 PAGE 2211 LINE 113777 -:VPERMQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPERMQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vpermq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11308,7 +11308,7 @@ define pcodeop vpermq_avx512f ; } # VPERMQ 5-387 PAGE 2211 LINE 113780 -:VPERMQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPERMQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x36; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vpermq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11318,7 +11318,7 @@ define pcodeop vpermq_avx512f ; } define pcodeop vpermt2pd_avx512f; -:VPERMT2PD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst { +:VPERMT2PD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x7F; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst { ZmmResult = vpermt2pd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); ZmmMask = ZmmReg1; build ZmmOpMask64; @@ -11327,7 +11327,7 @@ define pcodeop vpermt2pd_avx512f; # VPEXPANDD 5-390 PAGE 2214 LINE 113945 define pcodeop vpexpandd_avx512vl ; -:VPEXPANDD XmmReg1 XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 +:VPEXPANDD XmmReg1^XmmOpMask32, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpexpandd_avx512vl( XmmReg2_m128 ); @@ -11337,7 +11337,7 @@ define pcodeop vpexpandd_avx512vl ; } # VPEXPANDD 5-390 PAGE 2214 LINE 113948 -:VPEXPANDD YmmReg1 YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 +:VPEXPANDD YmmReg1^YmmOpMask32, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpexpandd_avx512vl( YmmReg2_m256 ); @@ -11348,7 +11348,7 @@ define pcodeop vpexpandd_avx512vl ; # VPEXPANDD 5-390 PAGE 2214 LINE 113951 define pcodeop vpexpandd_avx512f ; -:VPEXPANDD ZmmReg1 ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 +:VPEXPANDD ZmmReg1^ZmmOpMask32, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x89; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpexpandd_avx512f( ZmmReg2_m512 ); @@ -11359,7 +11359,7 @@ define pcodeop vpexpandd_avx512f ; # VPEXPANDQ 5-392 PAGE 2216 LINE 114033 define pcodeop vpexpandq_avx512vl ; -:VPEXPANDQ XmmReg1 XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 +:VPEXPANDQ XmmReg1^XmmOpMask64, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vpexpandq_avx512vl( XmmReg2_m128 ); @@ -11369,7 +11369,7 @@ define pcodeop vpexpandq_avx512vl ; } # VPEXPANDQ 5-392 PAGE 2216 LINE 114035 -:VPEXPANDQ YmmReg1 YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 +:VPEXPANDQ YmmReg1^YmmOpMask64, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmResult = vpexpandq_avx512vl( YmmReg2_m256 ); @@ -11380,7 +11380,7 @@ define pcodeop vpexpandq_avx512vl ; # VPEXPANDQ 5-392 PAGE 2216 LINE 114037 define pcodeop vpexpandq_avx512f ; -:VPEXPANDQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 +:VPEXPANDQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x89; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmResult = vpexpandq_avx512f( ZmmReg2_m512 ); @@ -11391,7 +11391,7 @@ define pcodeop vpexpandq_avx512f ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114118 define pcodeop vplzcntd_avx512vl ; -:VPLZCNTD XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPLZCNTD XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vplzcntd_avx512vl( XmmReg2_m128_m32bcst ); @@ -11401,7 +11401,7 @@ define pcodeop vplzcntd_avx512vl ; } # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114122 -:VPLZCNTD YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPLZCNTD YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vplzcntd_avx512vl( YmmReg2_m256_m32bcst ); @@ -11412,7 +11412,7 @@ define pcodeop vplzcntd_avx512vl ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114126 define pcodeop vplzcntd_avx512cd ; -:VPLZCNTD ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPLZCNTD ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x44; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vplzcntd_avx512cd( ZmmReg2_m512_m32bcst ); @@ -11423,7 +11423,7 @@ define pcodeop vplzcntd_avx512cd ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114130 define pcodeop vplzcntq_avx512vl ; -:VPLZCNTQ XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPLZCNTQ XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vplzcntq_avx512vl( XmmReg2_m128_m64bcst ); @@ -11433,7 +11433,7 @@ define pcodeop vplzcntq_avx512vl ; } # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114134 -:VPLZCNTQ YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPLZCNTQ YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vplzcntq_avx512vl( YmmReg2_m256_m64bcst ); @@ -11444,7 +11444,7 @@ define pcodeop vplzcntq_avx512vl ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114138 define pcodeop vplzcntq_avx512cd ; -:VPLZCNTQ ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPLZCNTQ ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x44; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vplzcntq_avx512cd( ZmmReg2_m512_m64bcst ); @@ -11624,7 +11624,7 @@ define pcodeop vpmovq2m_avx512dq ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115959 define pcodeop vprolvd_avx512vl ; -:VPROLVD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPROLVD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { XmmResult = vprolvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -11635,7 +11635,7 @@ define pcodeop vprolvd_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115962 define pcodeop vprold_avx512vl ; -:VPROLD vexVVVV_XmmReg XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m32bcst; imm8 +:VPROLD vexVVVV_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { XmmResult = vprold_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -11646,7 +11646,7 @@ define pcodeop vprold_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115965 define pcodeop vprolvq_avx512vl ; -:VPROLVQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPROLVQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { XmmResult = vprolvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -11657,7 +11657,7 @@ define pcodeop vprolvq_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115968 define pcodeop vprolq_avx512vl ; -:VPROLQ vexVVVV_XmmReg XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m64bcst; imm8 +:VPROLQ vexVVVV_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { XmmResult = vprolq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -11667,7 +11667,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115971 -:VPROLVD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPROLVD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vprolvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -11677,7 +11677,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115974 -:VPROLD vexVVVV_YmmReg YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m32bcst; imm8 +:VPROLD vexVVVV_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { YmmResult = vprold_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -11687,7 +11687,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115977 -:VPROLVQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPROLVQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vprolvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11697,7 +11697,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115980 -:VPROLQ vexVVVV_YmmReg YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m64bcst; imm8 +:VPROLQ vexVVVV_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { YmmResult = vprolq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -11708,7 +11708,7 @@ define pcodeop vprolq_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115983 define pcodeop vprolvd_avx512f ; -:VPROLVD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPROLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vprolvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -11719,7 +11719,7 @@ define pcodeop vprolvd_avx512f ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115987 define pcodeop vprold_avx512f ; -:VPROLD evexV5_ZmmReg ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m32bcst; imm8 +:VPROLD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { ZmmResult = vprold_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -11730,7 +11730,7 @@ define pcodeop vprold_avx512f ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115990 define pcodeop vprolvq_avx512f ; -:VPROLVQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPROLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x15; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vprolvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11741,7 +11741,7 @@ define pcodeop vprolvq_avx512f ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115993 define pcodeop vprolq_avx512f ; -:VPROLQ evexV5_ZmmReg ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m64bcst; imm8 +:VPROLQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { ZmmResult = vprolq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -11752,7 +11752,7 @@ define pcodeop vprolq_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116190 define pcodeop vprorvd_avx512vl ; -:VPRORVD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPRORVD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { XmmResult = vprorvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -11763,7 +11763,7 @@ define pcodeop vprorvd_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116194 define pcodeop vprord_avx512vl ; -:VPRORD vexVVVV_XmmReg XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m32bcst; imm8 +:VPRORD vexVVVV_XmmReg^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask32; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { XmmResult = vprord_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -11774,7 +11774,7 @@ define pcodeop vprord_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116197 define pcodeop vprorvq_avx512vl ; -:VPRORVQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPRORVQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { XmmResult = vprorvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -11785,7 +11785,7 @@ define pcodeop vprorvq_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116200 define pcodeop vprorq_avx512vl ; -:VPRORQ vexVVVV_XmmReg XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m64bcst; imm8 +:VPRORQ vexVVVV_XmmReg^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & XmmOpMask64; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { XmmResult = vprorq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -11795,7 +11795,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116203 -:VPRORVD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPRORVD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vprorvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -11805,7 +11805,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116207 -:VPRORD vexVVVV_YmmReg YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m32bcst; imm8 +:VPRORD vexVVVV_YmmReg^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask32; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { YmmResult = vprord_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -11815,7 +11815,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116210 -:VPRORVQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPRORVQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { YmmResult = vprorvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -11825,7 +11825,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116213 -:VPRORQ vexVVVV_YmmReg YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m64bcst; imm8 +:VPRORQ vexVVVV_YmmReg^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & YmmOpMask64; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { YmmResult = vprorq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -11836,7 +11836,7 @@ define pcodeop vprorq_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116216 define pcodeop vprorvd_avx512f ; -:VPRORVD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPRORVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vprorvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -11847,7 +11847,7 @@ define pcodeop vprorvd_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116220 define pcodeop vprord_avx512f ; -:VPRORD evexV5_ZmmReg ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m32bcst; imm8 +:VPRORD evexV5_ZmmReg^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & ZmmOpMask32; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { ZmmResult = vprord_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -11858,7 +11858,7 @@ define pcodeop vprord_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116223 define pcodeop vprorvq_avx512f ; -:VPRORVQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPRORVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x14; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmResult = vprorvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -11869,7 +11869,7 @@ define pcodeop vprorvq_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116226 define pcodeop vprorq_avx512f ; -:VPRORQ evexV5_ZmmReg ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m64bcst; imm8 +:VPRORQ evexV5_ZmmReg^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & ZmmOpMask64; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { ZmmResult = vprorq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -11880,7 +11880,7 @@ define pcodeop vprorq_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116424 define pcodeop vpscatterdd_avx512vl ; -:VPSCATTERDD x_vm32x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x +:VPSCATTERDD x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdd_avx512vl( x_vm32x, XmmOpMask, XmmReg1 ); @@ -11888,7 +11888,7 @@ define pcodeop vpscatterdd_avx512vl ; } # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116426 -:VPSCATTERDD y_vm32y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y +:VPSCATTERDD y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdd_avx512vl( y_vm32y, YmmOpMask, YmmReg1 ); @@ -11897,7 +11897,7 @@ define pcodeop vpscatterdd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116428 define pcodeop vpscatterdd_avx512f ; -:VPSCATTERDD z_vm32z ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z +:VPSCATTERDD z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdd_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 ); @@ -11906,7 +11906,7 @@ define pcodeop vpscatterdd_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116430 define pcodeop vpscatterdq_avx512vl ; -:VPSCATTERDQ x_vm32x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x +:VPSCATTERDQ x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA0; XmmReg1 ... & x_vm32x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdq_avx512vl( x_vm32x, XmmOpMask, XmmReg1 ); @@ -11914,7 +11914,7 @@ define pcodeop vpscatterdq_avx512vl ; } # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116432 -:VPSCATTERDQ y_vm32y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y +:VPSCATTERDQ y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA0; YmmReg1 ... & y_vm32y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdq_avx512vl( y_vm32y, YmmOpMask, YmmReg1 ); @@ -11923,7 +11923,7 @@ define pcodeop vpscatterdq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116434 define pcodeop vpscatterdq_avx512f ; -:VPSCATTERDQ z_vm32z ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z +:VPSCATTERDQ z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA0; ZmmReg1 ... & z_vm32z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdq_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 ); @@ -11935,7 +11935,7 @@ define pcodeop vpscatterdq_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116436 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64x {k1}, xmm1" define pcodeop vpscatterqd_avx512vl ; -:VPSCATTERQD q_vm64x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x +:VPSCATTERQD q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqd_avx512vl( q_vm64x, XmmOpMask, XmmReg1 ); @@ -11944,7 +11944,7 @@ define pcodeop vpscatterqd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116438 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64y {k1}, xmm1" -:VPSCATTERQD q_vm64x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x +:VPSCATTERQD q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA1; XmmReg1 ... & q_vm64x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqd_avx512vl( q_vm64x, XmmOpMask, XmmReg1 ); @@ -11954,7 +11954,7 @@ define pcodeop vpscatterqd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116440 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64z {k1}, ymm1" define pcodeop vpscatterqd_avx512f ; -:VPSCATTERQD q_vm64y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA1; YmmReg1 ... & q_vm64y +:VPSCATTERQD q_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA1; YmmReg1 ... & q_vm64y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqd_avx512f( q_vm64y, YmmOpMask, YmmReg1 ); @@ -11964,7 +11964,7 @@ define pcodeop vpscatterqd_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116442 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64x {k1}, xmm1" define pcodeop vpscatterqq_avx512vl ; -:VPSCATTERQQ x_vm64x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA1; XmmReg1 ... & x_vm64x +:VPSCATTERQQ x_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA1; XmmReg1 ... & x_vm64x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqq_avx512vl( x_vm64x, XmmOpMask, XmmReg1 ); @@ -11973,7 +11973,7 @@ define pcodeop vpscatterqq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116444 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64y {k1}, ymm1" -:VPSCATTERQQ y_vm64y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA1; YmmReg1 ... & y_vm64y +:VPSCATTERQQ y_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA1; YmmReg1 ... & y_vm64y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqq_avx512vl( y_vm64y, YmmOpMask, YmmReg1 ); @@ -11983,7 +11983,7 @@ define pcodeop vpscatterqq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116446 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64z {k1}, zmm1" define pcodeop vpscatterqq_avx512f ; -:VPSCATTERQQ z_vm64z ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA1; ZmmReg1 ... & z_vm64z +:VPSCATTERQQ z_vm64z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA1; ZmmReg1 ... & z_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqq_avx512f( z_vm64z, ZmmOpMask, ZmmReg1 ); @@ -11993,7 +11993,7 @@ define pcodeop vpscatterqq_avx512f ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116632 define pcodeop vpsllvw_avx512vl ; -:VPSLLVW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSLLVW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsllvw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -12003,7 +12003,7 @@ define pcodeop vpsllvw_avx512vl ; } # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116635 -:VPSLLVW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPSLLVW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x12; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsllvw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -12014,7 +12014,7 @@ define pcodeop vpsllvw_avx512vl ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116638 define pcodeop vpsllvw_avx512bw ; -:VPSLLVW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x12; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPSLLVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x12; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsllvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -12025,7 +12025,7 @@ define pcodeop vpsllvw_avx512bw ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116641 define pcodeop vpsllvd_avx512vl ; -:VPSLLVD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPSLLVD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsllvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -12035,7 +12035,7 @@ define pcodeop vpsllvd_avx512vl ; } # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116644 -:VPSLLVD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPSLLVD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsllvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -12046,7 +12046,7 @@ define pcodeop vpsllvd_avx512vl ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116647 define pcodeop vpsllvd_avx512f ; -:VPSLLVD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPSLLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsllvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -12057,7 +12057,7 @@ define pcodeop vpsllvd_avx512f ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116650 define pcodeop vpsllvq_avx512vl ; -:VPSLLVQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPSLLVQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsllvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -12067,7 +12067,7 @@ define pcodeop vpsllvq_avx512vl ; } # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116653 -:VPSLLVQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPSLLVQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsllvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -12078,7 +12078,7 @@ define pcodeop vpsllvq_avx512vl ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116656 define pcodeop vpsllvq_avx512f ; -:VPSLLVQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPSLLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x47; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsllvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -12089,7 +12089,7 @@ define pcodeop vpsllvq_avx512f ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116880 define pcodeop vpsravw_avx512vl ; -:VPSRAVW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x11; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSRAVW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x11; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsravw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -12099,7 +12099,7 @@ define pcodeop vpsravw_avx512vl ; } # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116883 -:VPSRAVW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x11; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPSRAVW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x11; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsravw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -12110,7 +12110,7 @@ define pcodeop vpsravw_avx512vl ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116886 define pcodeop vpsravw_avx512bw ; -:VPSRAVW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x11; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPSRAVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x11; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsravw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -12121,7 +12121,7 @@ define pcodeop vpsravw_avx512bw ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116889 define pcodeop vpsravd_avx512vl ; -:VPSRAVD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPSRAVD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsravd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -12131,7 +12131,7 @@ define pcodeop vpsravd_avx512vl ; } # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116893 -:VPSRAVD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPSRAVD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsravd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -12142,7 +12142,7 @@ define pcodeop vpsravd_avx512vl ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116897 define pcodeop vpsravd_avx512f ; -:VPSRAVD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPSRAVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsravd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -12153,7 +12153,7 @@ define pcodeop vpsravd_avx512f ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116901 define pcodeop vpsravq_avx512vl ; -:VPSRAVQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPSRAVQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsravq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -12163,7 +12163,7 @@ define pcodeop vpsravq_avx512vl ; } # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116905 -:VPSRAVQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPSRAVQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsravq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -12174,7 +12174,7 @@ define pcodeop vpsravq_avx512vl ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116910 define pcodeop vpsravq_avx512f ; -:VPSRAVQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPSRAVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x46; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsravq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -12185,7 +12185,7 @@ define pcodeop vpsravq_avx512f ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117151 define pcodeop vpsrlvw_avx512vl ; -:VPSRLVW XmmReg1 XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 +:VPSRLVW XmmReg1^XmmOpMask16, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1 & XmmOpMask16) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { XmmResult = vpsrlvw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -12195,7 +12195,7 @@ define pcodeop vpsrlvw_avx512vl ; } # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117154 -:VPSRLVW YmmReg1 YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 +:VPSRLVW YmmReg1^YmmOpMask16, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x10; (YmmReg1 & ZmmReg1 & YmmOpMask16) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { YmmResult = vpsrlvw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -12206,7 +12206,7 @@ define pcodeop vpsrlvw_avx512vl ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117157 define pcodeop vpsrlvw_avx512bw ; -:VPSRLVW ZmmReg1 ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x10; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 +:VPSRLVW ZmmReg1^ZmmOpMask16, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x10; (ZmmReg1 & ZmmOpMask16) ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmResult = vpsrlvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -12217,7 +12217,7 @@ define pcodeop vpsrlvw_avx512bw ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117160 define pcodeop vpsrlvd_avx512vl ; -:VPSRLVD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VPSRLVD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsrlvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -12227,7 +12227,7 @@ define pcodeop vpsrlvd_avx512vl ; } # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117163 -:VPSRLVD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VPSRLVD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsrlvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -12238,7 +12238,7 @@ define pcodeop vpsrlvd_avx512vl ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117166 define pcodeop vpsrlvd_avx512f ; -:VPSRLVD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VPSRLVD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsrlvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -12249,7 +12249,7 @@ define pcodeop vpsrlvd_avx512f ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117169 define pcodeop vpsrlvq_avx512vl ; -:VPSRLVQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VPSRLVQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpsrlvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -12259,7 +12259,7 @@ define pcodeop vpsrlvq_avx512vl ; } # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117172 -:VPSRLVQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VPSRLVQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpsrlvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -12270,7 +12270,7 @@ define pcodeop vpsrlvq_avx512vl ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117175 define pcodeop vpsrlvq_avx512f ; -:VPSRLVQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VPSRLVQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x45; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpsrlvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -12281,7 +12281,7 @@ define pcodeop vpsrlvq_avx512f ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117395 define pcodeop vpternlogd_avx512vl ; -:VPTERNLOGD XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VPTERNLOGD XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpternlogd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -12291,7 +12291,7 @@ define pcodeop vpternlogd_avx512vl ; } # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117400 -:VPTERNLOGD YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VPTERNLOGD YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpternlogd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -12302,7 +12302,7 @@ define pcodeop vpternlogd_avx512vl ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117405 define pcodeop vpternlogd_avx512f ; -:VPTERNLOGD ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VPTERNLOGD ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpternlogd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -12313,7 +12313,7 @@ define pcodeop vpternlogd_avx512f ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117410 define pcodeop vpternlogq_avx512vl ; -:VPTERNLOGQ XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VPTERNLOGQ XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vpternlogq_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -12323,7 +12323,7 @@ define pcodeop vpternlogq_avx512vl ; } # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117415 -:VPTERNLOGQ YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VPTERNLOGQ YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vpternlogq_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -12334,7 +12334,7 @@ define pcodeop vpternlogq_avx512vl ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117420 define pcodeop vpternlogq_avx512f ; -:VPTERNLOGQ ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VPTERNLOGQ ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x25; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vpternlogq_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -12553,7 +12553,7 @@ define pcodeop vptestnmq_avx512f ; # VRANGEPD 5-470 PAGE 2294 LINE 117905 define pcodeop vrangepd_avx512vl ; -:VRANGEPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VRANGEPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrangepd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -12563,7 +12563,7 @@ define pcodeop vrangepd_avx512vl ; } # VRANGEPD 5-470 PAGE 2294 LINE 117910 -:VRANGEPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VRANGEPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrangepd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -12574,7 +12574,7 @@ define pcodeop vrangepd_avx512vl ; # VRANGEPD 5-470 PAGE 2294 LINE 117915 define pcodeop vrangepd_avx512dq ; -:VRANGEPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VRANGEPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrangepd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -12585,7 +12585,7 @@ define pcodeop vrangepd_avx512dq ; # VRANGEPS 5-475 PAGE 2299 LINE 118139 define pcodeop vrangeps_avx512vl ; -:VRANGEPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VRANGEPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrangeps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -12595,7 +12595,7 @@ define pcodeop vrangeps_avx512vl ; } # VRANGEPS 5-475 PAGE 2299 LINE 118144 -:VRANGEPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VRANGEPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrangeps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -12606,7 +12606,7 @@ define pcodeop vrangeps_avx512vl ; # VRANGEPS 5-475 PAGE 2299 LINE 118149 define pcodeop vrangeps_avx512dq ; -:VRANGEPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VRANGEPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x50; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrangeps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -12617,7 +12617,7 @@ define pcodeop vrangeps_avx512dq ; # VRANGESD 5-479 PAGE 2303 LINE 118318 define pcodeop vrangesd_avx512dq ; -:VRANGESD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8 +:VRANGESD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrangesd_avx512dq( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); @@ -12628,7 +12628,7 @@ define pcodeop vrangesd_avx512dq ; # VRANGESS 5-482 PAGE 2306 LINE 118473 define pcodeop vrangess_avx512dq ; -:VRANGESS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRANGESS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrangess_avx512dq( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -12639,7 +12639,7 @@ define pcodeop vrangess_avx512dq ; # VRCP14PD 5-485 PAGE 2309 LINE 118626 define pcodeop vrcp14pd_avx512vl ; -:VRCP14PD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VRCP14PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrcp14pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -12649,7 +12649,7 @@ define pcodeop vrcp14pd_avx512vl ; } # VRCP14PD 5-485 PAGE 2309 LINE 118629 -:VRCP14PD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VRCP14PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrcp14pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -12660,7 +12660,7 @@ define pcodeop vrcp14pd_avx512vl ; # VRCP14PD 5-485 PAGE 2309 LINE 118632 define pcodeop vrcp14pd_avx512f ; -:VRCP14PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VRCP14PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrcp14pd_avx512f( ZmmReg2_m512_m64bcst ); @@ -12671,7 +12671,7 @@ define pcodeop vrcp14pd_avx512f ; # VRCP14SD 5-487 PAGE 2311 LINE 118726 define pcodeop vrcp14sd_avx512f ; -:VRCP14SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VRCP14SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrcp14sd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -12682,7 +12682,7 @@ define pcodeop vrcp14sd_avx512f ; # VRCP14PS 5-489 PAGE 2313 LINE 118800 define pcodeop vrcp14ps_avx512vl ; -:VRCP14PS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VRCP14PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrcp14ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -12692,7 +12692,7 @@ define pcodeop vrcp14ps_avx512vl ; } # VRCP14PS 5-489 PAGE 2313 LINE 118803 -:VRCP14PS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VRCP14PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrcp14ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -12703,7 +12703,7 @@ define pcodeop vrcp14ps_avx512vl ; # VRCP14PS 5-489 PAGE 2313 LINE 118806 define pcodeop vrcp14ps_avx512f ; -:VRCP14PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VRCP14PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrcp14ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -12714,7 +12714,7 @@ define pcodeop vrcp14ps_avx512f ; # VRCP14SS 5-491 PAGE 2315 LINE 118904 define pcodeop vrcp14ss_avx512f ; -:VRCP14SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRCP14SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrcp14ss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -12725,7 +12725,7 @@ define pcodeop vrcp14ss_avx512f ; # VRCP28PD 5-493 PAGE 2317 LINE 118979 define pcodeop vrcp28pd_avx512er ; -:VRCP28PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VRCP28PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCA; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrcp28pd_avx512er( ZmmReg2_m512_m64bcst ); @@ -12736,7 +12736,7 @@ define pcodeop vrcp28pd_avx512er ; # VRCP28SD 5-495 PAGE 2319 LINE 119074 define pcodeop vrcp28sd_avx512er ; -:VRCP28SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VRCP28SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrcp28sd_avx512er( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -12747,7 +12747,7 @@ define pcodeop vrcp28sd_avx512er ; # VRCP28PS 5-497 PAGE 2321 LINE 119167 define pcodeop vrcp28ps_avx512er ; -:VRCP28PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VRCP28PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCA; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrcp28ps_avx512er( ZmmReg2_m512_m32bcst ); @@ -12758,7 +12758,7 @@ define pcodeop vrcp28ps_avx512er ; # VRCP28SS 5-499 PAGE 2323 LINE 119263 define pcodeop vrcp28ss_avx512er ; -:VRCP28SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRCP28SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrcp28ss_avx512er( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -12769,7 +12769,7 @@ define pcodeop vrcp28ss_avx512er ; # VREDUCEPD 5-501 PAGE 2325 LINE 119356 define pcodeop vreducepd_avx512vl ; -:VREDUCEPD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VREDUCEPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vreducepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -12779,7 +12779,7 @@ define pcodeop vreducepd_avx512vl ; } # VREDUCEPD 5-501 PAGE 2325 LINE 119360 -:VREDUCEPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VREDUCEPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vreducepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -12790,7 +12790,7 @@ define pcodeop vreducepd_avx512vl ; # VREDUCEPD 5-501 PAGE 2325 LINE 119364 define pcodeop vreducepd_avx512dq ; -:VREDUCEPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VREDUCEPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x56; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vreducepd_avx512dq( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -12801,7 +12801,7 @@ define pcodeop vreducepd_avx512dq ; # VREDUCESD 5-504 PAGE 2328 LINE 119510 define pcodeop vreducesd_avx512dq ; -:VREDUCESD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VREDUCESD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vreducesd_avx512dq( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -12812,7 +12812,7 @@ define pcodeop vreducesd_avx512dq ; # VREDUCEPS 5-506 PAGE 2330 LINE 119605 define pcodeop vreduceps_avx512vl ; -:VREDUCEPS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VREDUCEPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vreduceps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -12822,7 +12822,7 @@ define pcodeop vreduceps_avx512vl ; } # VREDUCEPS 5-506 PAGE 2330 LINE 119609 -:VREDUCEPS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VREDUCEPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vreduceps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -12833,7 +12833,7 @@ define pcodeop vreduceps_avx512vl ; # VREDUCEPS 5-506 PAGE 2330 LINE 119613 define pcodeop vreduceps_avx512dq ; -:VREDUCEPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VREDUCEPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x56; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vreduceps_avx512dq( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -12844,7 +12844,7 @@ define pcodeop vreduceps_avx512dq ; # VREDUCESS 5-508 PAGE 2332 LINE 119719 define pcodeop vreducess_avx512dq ; -:VREDUCESS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VREDUCESS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vreducess_avx512dq( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -12855,7 +12855,7 @@ define pcodeop vreducess_avx512dq ; # VRNDSCALEPD 5-510 PAGE 2334 LINE 119814 define pcodeop vrndscalepd_avx512vl ; -:VRNDSCALEPD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 +:VRNDSCALEPD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrndscalepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -12865,7 +12865,7 @@ define pcodeop vrndscalepd_avx512vl ; } # VRNDSCALEPD 5-510 PAGE 2334 LINE 119818 -:VRNDSCALEPD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 +:VRNDSCALEPD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrndscalepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -12876,7 +12876,7 @@ define pcodeop vrndscalepd_avx512vl ; # VRNDSCALEPD 5-510 PAGE 2334 LINE 119822 define pcodeop vrndscalepd_avx512f ; -:VRNDSCALEPD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 +:VRNDSCALEPD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) ; byte=0x09; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrndscalepd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -12887,7 +12887,7 @@ define pcodeop vrndscalepd_avx512f ; # VRNDSCALESD 5-514 PAGE 2338 LINE 119998 define pcodeop vrndscalesd_avx512f ; -:VRNDSCALESD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8 +:VRNDSCALESD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrndscalesd_avx512f( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); @@ -12898,7 +12898,7 @@ define pcodeop vrndscalesd_avx512f ; # VRNDSCALEPS 5-516 PAGE 2340 LINE 120116 define pcodeop vrndscaleps_avx512vl ; -:VRNDSCALEPS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 +:VRNDSCALEPS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrndscaleps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -12908,7 +12908,7 @@ define pcodeop vrndscaleps_avx512vl ; } # VRNDSCALEPS 5-516 PAGE 2340 LINE 120120 -:VRNDSCALEPS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 +:VRNDSCALEPS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrndscaleps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -12919,7 +12919,7 @@ define pcodeop vrndscaleps_avx512vl ; # VRNDSCALEPS 5-516 PAGE 2340 LINE 120124 define pcodeop vrndscaleps_avx512f ; -:VRNDSCALEPS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 +:VRNDSCALEPS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x08; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrndscaleps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -12930,7 +12930,7 @@ define pcodeop vrndscaleps_avx512f ; # VRNDSCALESS 5-519 PAGE 2343 LINE 120263 define pcodeop vrndscaless_avx512f ; -:VRNDSCALESS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRNDSCALESS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrndscaless_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -12941,7 +12941,7 @@ define pcodeop vrndscaless_avx512f ; # VRSQRT14PD 5-521 PAGE 2345 LINE 120381 define pcodeop vrsqrt14pd_avx512vl ; -:VRSQRT14PD XmmReg1 XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VRSQRT14PD XmmReg1^XmmOpMask64, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrsqrt14pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -12951,7 +12951,7 @@ define pcodeop vrsqrt14pd_avx512vl ; } # VRSQRT14PD 5-521 PAGE 2345 LINE 120385 -:VRSQRT14PD YmmReg1 YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VRSQRT14PD YmmReg1^YmmOpMask64, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrsqrt14pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -12962,7 +12962,7 @@ define pcodeop vrsqrt14pd_avx512vl ; # VRSQRT14PD 5-521 PAGE 2345 LINE 120389 define pcodeop vrsqrt14pd_avx512f ; -:VRSQRT14PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VRSQRT14PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0x4E; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrsqrt14pd_avx512f( ZmmReg2_m512_m64bcst ); @@ -12973,7 +12973,7 @@ define pcodeop vrsqrt14pd_avx512f ; # VRSQRT14SD 5-523 PAGE 2347 LINE 120491 define pcodeop vrsqrt14sd_avx512f ; -:VRSQRT14SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VRSQRT14SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrsqrt14sd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -12984,7 +12984,7 @@ define pcodeop vrsqrt14sd_avx512f ; # VRSQRT14PS 5-525 PAGE 2349 LINE 120578 define pcodeop vrsqrt14ps_avx512vl ; -:VRSQRT14PS XmmReg1 XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VRSQRT14PS XmmReg1^XmmOpMask32, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vrsqrt14ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -12994,7 +12994,7 @@ define pcodeop vrsqrt14ps_avx512vl ; } # VRSQRT14PS 5-525 PAGE 2349 LINE 120582 -:VRSQRT14PS YmmReg1 YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VRSQRT14PS YmmReg1^YmmOpMask32, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vrsqrt14ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -13005,7 +13005,7 @@ define pcodeop vrsqrt14ps_avx512vl ; # VRSQRT14PS 5-525 PAGE 2349 LINE 120586 define pcodeop vrsqrt14ps_avx512f ; -:VRSQRT14PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VRSQRT14PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0x4E; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrsqrt14ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -13016,7 +13016,7 @@ define pcodeop vrsqrt14ps_avx512f ; # VRSQRT14SS 5-527 PAGE 2351 LINE 120690 define pcodeop vrsqrt14ss_avx512f ; -:VRSQRT14SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRSQRT14SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrsqrt14ss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -13027,7 +13027,7 @@ define pcodeop vrsqrt14ss_avx512f ; # VRSQRT28PD 5-529 PAGE 2353 LINE 120778 define pcodeop vrsqrt28pd_avx512er ; -:VRSQRT28PD ZmmReg1 ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VRSQRT28PD ZmmReg1^ZmmOpMask64, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) ; byte=0xCC; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrsqrt28pd_avx512er( ZmmReg2_m512_m64bcst ); @@ -13038,7 +13038,7 @@ define pcodeop vrsqrt28pd_avx512er ; # VRSQRT28SD 5-531 PAGE 2355 LINE 120869 define pcodeop vrsqrt28sd_avx512er ; -:VRSQRT28SD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VRSQRT28SD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrsqrt28sd_avx512er( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -13049,7 +13049,7 @@ define pcodeop vrsqrt28sd_avx512er ; # VRSQRT28PS 5-533 PAGE 2357 LINE 120959 define pcodeop vrsqrt28ps_avx512er ; -:VRSQRT28PS ZmmReg1 ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VRSQRT28PS ZmmReg1^ZmmOpMask32, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0); byte=0xCC; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vrsqrt28ps_avx512er( ZmmReg2_m512_m32bcst ); @@ -13060,7 +13060,7 @@ define pcodeop vrsqrt28ps_avx512er ; # VRSQRT28SS 5-535 PAGE 2359 LINE 121051 define pcodeop vrsqrt28ss_avx512er ; -:VRSQRT28SS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VRSQRT28SS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vrsqrt28ss_avx512er( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -13071,7 +13071,7 @@ define pcodeop vrsqrt28ss_avx512er ; # VSCALEFPD 5-537 PAGE 2361 LINE 121140 define pcodeop vscalefpd_avx512vl ; -:VSCALEFPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VSCALEFPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vscalefpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -13081,7 +13081,7 @@ define pcodeop vscalefpd_avx512vl ; } # VSCALEFPD 5-537 PAGE 2361 LINE 121143 -:VSCALEFPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VSCALEFPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vscalefpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -13092,7 +13092,7 @@ define pcodeop vscalefpd_avx512vl ; # VSCALEFPD 5-537 PAGE 2361 LINE 121146 define pcodeop vscalefpd_avx512f ; -:VSCALEFPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VSCALEFPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vscalefpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -13103,7 +13103,7 @@ define pcodeop vscalefpd_avx512f ; # VSCALEFSD 5-540 PAGE 2364 LINE 121269 define pcodeop vscalefsd_avx512f ; -:VSCALEFSD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 +:VSCALEFSD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vscalefsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -13114,7 +13114,7 @@ define pcodeop vscalefsd_avx512f ; # VSCALEFPS 5-542 PAGE 2366 LINE 121355 define pcodeop vscalefps_avx512vl ; -:VSCALEFPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VSCALEFPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vscalefps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -13124,7 +13124,7 @@ define pcodeop vscalefps_avx512vl ; } # VSCALEFPS 5-542 PAGE 2366 LINE 121358 -:VSCALEFPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VSCALEFPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vscalefps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -13135,7 +13135,7 @@ define pcodeop vscalefps_avx512vl ; # VSCALEFPS 5-542 PAGE 2366 LINE 121361 define pcodeop vscalefps_avx512f ; -:VSCALEFPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VSCALEFPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & evexV5_ZmmReg; byte=0x2C; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vscalefps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -13146,7 +13146,7 @@ define pcodeop vscalefps_avx512f ; # VSCALEFSS 5-544 PAGE 2368 LINE 121470 define pcodeop vscalefss_avx512f ; -:VSCALEFSS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 +:VSCALEFSS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmResult = vscalefss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -13157,7 +13157,7 @@ define pcodeop vscalefss_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121559 define pcodeop vscatterdps_avx512vl ; -:VSCATTERDPS x_vm32x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x +:VSCATTERDPS x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdps_avx512vl( x_vm32x, XmmOpMask, XmmReg1 ); @@ -13165,7 +13165,7 @@ define pcodeop vscatterdps_avx512vl ; } # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121561 -:VSCATTERDPS y_vm32y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y +:VSCATTERDPS y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdps_avx512vl( y_vm32y, YmmOpMask, YmmReg1 ); @@ -13174,7 +13174,7 @@ define pcodeop vscatterdps_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121563 define pcodeop vscatterdps_avx512f ; -:VSCATTERDPS z_vm32z ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z +:VSCATTERDPS z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdps_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 ); @@ -13183,7 +13183,7 @@ define pcodeop vscatterdps_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121565 define pcodeop vscatterdpd_avx512vl ; -:VSCATTERDPD x_vm32x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x +:VSCATTERDPD x_vm32x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA2; XmmReg1 ... & x_vm32x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdpd_avx512vl( x_vm32x, XmmOpMask, XmmReg1 ); @@ -13191,7 +13191,7 @@ define pcodeop vscatterdpd_avx512vl ; } # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121567 -:VSCATTERDPD y_vm32y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y +:VSCATTERDPD y_vm32y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA2; YmmReg1 ... & y_vm32y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdpd_avx512vl( y_vm32y, YmmOpMask, YmmReg1 ); @@ -13200,7 +13200,7 @@ define pcodeop vscatterdpd_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121569 define pcodeop vscatterdpd_avx512f ; -:VSCATTERDPD z_vm32z ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z +:VSCATTERDPD z_vm32z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA2; ZmmReg1 ... & z_vm32z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdpd_avx512f( z_vm32z, ZmmOpMask, ZmmReg1 ); @@ -13210,7 +13210,7 @@ define pcodeop vscatterdpd_avx512f ; @ifdef IA64 # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121571 define pcodeop vscatterqps_avx512vl ; -:VSCATTERQPS q_vm64x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64x +:VSCATTERQPS q_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqps_avx512vl( q_vm64x, XmmOpMask, XmmReg1 ); @@ -13218,7 +13218,7 @@ define pcodeop vscatterqps_avx512vl ; } # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121573 -:VSCATTERQPS q_vm64y XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64y +:VSCATTERQPS q_vm64y^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask; byte=0xA3; XmmReg1 ... & q_vm64y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqps_avx512vl( q_vm64y, XmmOpMask, XmmReg1 ); @@ -13227,7 +13227,7 @@ define pcodeop vscatterqps_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121575 define pcodeop vscatterqps_avx512f ; -:VSCATTERQPS q_vm64z YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA3; YmmReg1 ... & q_vm64z +:VSCATTERQPS q_vm64z^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask; byte=0xA3; YmmReg1 ... & q_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqps_avx512f( q_vm64z, YmmOpMask, YmmReg1 ); @@ -13236,7 +13236,7 @@ define pcodeop vscatterqps_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121577 define pcodeop vscatterqpd_avx512vl ; -:VSCATTERQPD x_vm64x XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA3; XmmReg1 ... & x_vm64x +:VSCATTERQPD x_vm64x^XmmOpMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & XmmOpMask; byte=0xA3; XmmReg1 ... & x_vm64x [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqpd_avx512vl( x_vm64x, XmmOpMask, XmmReg1 ); @@ -13244,7 +13244,7 @@ define pcodeop vscatterqpd_avx512vl ; } # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121579 -:VSCATTERQPD y_vm64y YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA3; YmmReg1 ... & y_vm64y +:VSCATTERQPD y_vm64y^YmmOpMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xA3; YmmReg1 ... & y_vm64y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqpd_avx512vl( y_vm64y, YmmOpMask, YmmReg1 ); @@ -13255,7 +13255,7 @@ define pcodeop vscatterqpd_avx512vl ; @ifdef IA64 # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121581 define pcodeop vscatterqpd_avx512f ; -:VSCATTERQPD z_vm64z ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA3; ZmmReg1 ... & z_vm64z +:VSCATTERQPD z_vm64z^ZmmOpMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xA3; ZmmReg1 ... & z_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqpd_avx512f( z_vm64z, ZmmOpMask, ZmmReg1 ); @@ -13265,7 +13265,7 @@ define pcodeop vscatterqpd_avx512f ; # VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121759 define pcodeop vscatterpf0dps_avx512pf ; -:VSCATTERPF0DPS z_vm32z ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=5 ... & z_vm32z +:VSCATTERPF0DPS z_vm32z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=5 ... & z_vm32z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf0dps_avx512pf( z_vm32z , ZmmOpMask); @@ -13275,7 +13275,7 @@ define pcodeop vscatterpf0dps_avx512pf ; @ifdef IA64 # VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121762 define pcodeop vscatterpf0qps_avx512pf ; -:VSCATTERPF0QPS z_vm64z ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z +:VSCATTERPF0QPS z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf0qps_avx512pf( z_vm64z, ZmmOpMask ); @@ -13285,7 +13285,7 @@ define pcodeop vscatterpf0qps_avx512pf ; # VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121765 define pcodeop vscatterpf0dpd_avx512pf ; -:VSCATTERPF0DPD y_vm32y YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=5 ... & y_vm32y +:VSCATTERPF0DPD y_vm32y^YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=5 ... & y_vm32y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf0dpd_avx512pf( y_vm32y, YmmOpMask ); @@ -13295,7 +13295,7 @@ define pcodeop vscatterpf0dpd_avx512pf ; @ifdef IA64 # VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD 5-551 PAGE 2375 LINE 121768 define pcodeop vscatterpf0qpd_avx512pf ; -:VSCATTERPF0QPD z_vm64z ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z +:VSCATTERPF0QPD z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=5 ... & z_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf0qpd_avx512pf( z_vm64z, ZmmOpMask ); @@ -13305,7 +13305,7 @@ define pcodeop vscatterpf0qpd_avx512pf ; # VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121877 define pcodeop vscatterpf1dps_avx512pf ; -:VSCATTERPF1DPS z_vm32z ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=6 ... & z_vm32z +:VSCATTERPF1DPS z_vm32z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC6; reg_opcode=6 ... & z_vm32z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf1dps_avx512pf( z_vm32z, ZmmOpMask ); @@ -13315,7 +13315,7 @@ define pcodeop vscatterpf1dps_avx512pf ; @ifdef IA64 # VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121880 define pcodeop vscatterpf1qps_avx512pf ; -:VSCATTERPF1QPS z_vm64z ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z +:VSCATTERPF1QPS z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf1qps_avx512pf( z_vm64z, ZmmOpMask ); @@ -13325,7 +13325,7 @@ define pcodeop vscatterpf1qps_avx512pf ; # VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121883 define pcodeop vscatterpf1dpd_avx512pf ; -:VSCATTERPF1DPD y_vm32y YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=6 ... & y_vm32y +:VSCATTERPF1DPD y_vm32y^YmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & YmmOpMask; byte=0xC6; reg_opcode=6 ... & y_vm32y [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf1dpd_avx512pf( y_vm32y, YmmOpMask ); @@ -13335,7 +13335,7 @@ define pcodeop vscatterpf1dpd_avx512pf ; @ifdef IA64 # VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD 5-553 PAGE 2377 LINE 121886 define pcodeop vscatterpf1qpd_avx512pf ; -:VSCATTERPF1QPD z_vm64z ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z +:VSCATTERPF1QPD z_vm64z^ZmmOpMask is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & ZmmOpMask; byte=0xC7; reg_opcode=6 ... & z_vm64z [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterpf1qpd_avx512pf( z_vm64z, ZmmOpMask ); @@ -13345,7 +13345,7 @@ define pcodeop vscatterpf1qpd_avx512pf ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121994 define pcodeop vshuff32x4_avx512vl ; -:VSHUFF32X4 YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VSHUFF32X4 YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vshuff32x4_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -13356,7 +13356,7 @@ define pcodeop vshuff32x4_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121998 define pcodeop vshuff32x4_avx512f ; -:VSHUFF32x4 ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VSHUFF32x4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vshuff32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -13367,7 +13367,7 @@ define pcodeop vshuff32x4_avx512f ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122002 define pcodeop vshuff64x2_avx512vl ; -:VSHUFF64X2 YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VSHUFF64X2 YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vshuff64x2_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -13378,7 +13378,7 @@ define pcodeop vshuff64x2_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122006 define pcodeop vshuff64x2_avx512f ; -:VSHUFF64x2 ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VSHUFF64x2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x23; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vshuff64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -13389,7 +13389,7 @@ define pcodeop vshuff64x2_avx512f ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122010 define pcodeop vshufi32x4_avx512vl ; -:VSHUFI32X4 YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VSHUFI32X4 YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vshufi32x4_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -13400,7 +13400,7 @@ define pcodeop vshufi32x4_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122013 define pcodeop vshufi32x4_avx512f ; -:VSHUFI32x4 ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VSHUFI32x4 ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vshufi32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -13411,7 +13411,7 @@ define pcodeop vshufi32x4_avx512f ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122016 define pcodeop vshufi64x2_avx512vl ; -:VSHUFI64X2 YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VSHUFI64X2 YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vshufi64x2_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -13422,7 +13422,7 @@ define pcodeop vshufi64x2_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122019 define pcodeop vshufi64x2_avx512f ; -:VSHUFI64x2 ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VSHUFI64x2 ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & evexV5_ZmmReg; byte=0x43; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vshufi64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -13433,7 +13433,7 @@ define pcodeop vshufi64x2_avx512f ; # XORPD 5-596 PAGE 2420 LINE 123834 define pcodeop vxorpd_avx512vl ; -:VXORPD XmmReg1 XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst +:VXORPD XmmReg1^XmmOpMask64, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask64) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vxorpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -13443,7 +13443,7 @@ define pcodeop vxorpd_avx512vl ; } # XORPD 5-596 PAGE 2420 LINE 123837 -:VXORPD YmmReg1 YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst +:VXORPD YmmReg1^YmmOpMask64, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask64) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vxorpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -13454,7 +13454,7 @@ define pcodeop vxorpd_avx512vl ; # XORPD 5-596 PAGE 2420 LINE 123840 define pcodeop vxorpd_avx512dq ; -:VXORPD ZmmReg1 ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst +:VXORPD ZmmReg1^ZmmOpMask64, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask64) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vxorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -13465,7 +13465,7 @@ define pcodeop vxorpd_avx512dq ; # XORPS 5-599 PAGE 2423 LINE 123959 define pcodeop vxorps_avx512vl ; -:VXORPS XmmReg1 XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst +:VXORPS XmmReg1^XmmOpMask32, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1 & XmmOpMask32) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { XmmResult = vxorps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -13475,7 +13475,7 @@ define pcodeop vxorps_avx512vl ; } # XORPS 5-599 PAGE 2423 LINE 123962 -:VXORPS YmmReg1 YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst +:VXORPS YmmReg1^YmmOpMask32, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1 & YmmOpMask32) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { YmmResult = vxorps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -13486,7 +13486,7 @@ define pcodeop vxorps_avx512vl ; # XORPS 5-599 PAGE 2423 LINE 123965 define pcodeop vxorps_avx512dq ; -:VXORPS ZmmReg1 ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst +:VXORPS ZmmReg1^ZmmOpMask32, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg; byte=0x57; (ZmmReg1 & ZmmOpMask32) ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmResult = vxorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); diff --git a/Ghidra/Processors/x86/data/languages/avx512_manual.sinc b/Ghidra/Processors/x86/data/languages/avx512_manual.sinc index 3c181c7b66..ef603b157d 100644 --- a/Ghidra/Processors/x86/data/languages/avx512_manual.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512_manual.sinc @@ -464,7 +464,7 @@ # VCVTPS2PH 5-37 PAGE 1861 LINE 96116 define pcodeop vcvtps2ph_avx512vl ; -:VCVTPS2PH XmmReg2 XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8 +:VCVTPS2PH XmmReg2^XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8 { XmmResult = vcvtps2ph_avx512vl( XmmReg1, imm8:1 ); XmmMask = XmmReg2; @@ -476,7 +476,7 @@ define pcodeop vcvtps2ph_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VCVTPS2PH m64 XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; XmmReg1 ... & m64; imm8 +:VCVTPS2PH m64^XmmOpMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; XmmReg1 ... & m64; imm8 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vcvtps2ph_avx512vl( XmmReg1, imm8:1 ); @@ -490,7 +490,7 @@ define pcodeop vcvtps2ph_avx512vl ; } # VCVTPS2PH 5-37 PAGE 1861 LINE 96119 -:VCVTPS2PH XmmReg2 XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8 +:VCVTPS2PH XmmReg2^XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8 { XmmResult = vcvtps2ph_avx512vl( YmmReg1, imm8:1 ); XmmMask = XmmReg2; @@ -507,7 +507,7 @@ define pcodeop vcvtps2ph_avx512vl ; } # VCVTPS2PH 5-37 PAGE 1861 LINE 96119 -:VCVTPS2PH m128 XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; YmmReg1 ... & m128; imm8 +:VCVTPS2PH m128^XmmOpMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & XmmOpMask; byte=0x1D; YmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vcvtps2ph_avx512vl( YmmReg1, imm8:1 ); @@ -526,7 +526,7 @@ define pcodeop vcvtps2ph_avx512vl ; # VCVTPS2PH 5-37 PAGE 1861 LINE 96122 define pcodeop vcvtps2ph_avx512f ; -:VCVTPS2PH YmmReg2 YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8 +:VCVTPS2PH YmmReg2^YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8 { YmmResult = vcvtps2ph_avx512f( ZmmReg1, imm8:1 ); YmmMask = YmmReg2; @@ -550,7 +550,7 @@ define pcodeop vcvtps2ph_avx512f ; ZmmReg2 = zext(YmmResult); } -:VCVTPS2PH m256 YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; ZmmReg1 ... & m256; imm8 +:VCVTPS2PH m256^YmmOpMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & YmmOpMask; byte=0x1D; ZmmReg1 ... & m256; imm8 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vcvtps2ph_avx512f( ZmmReg1, imm8:1 ); @@ -577,7 +577,7 @@ define pcodeop vcvtps2ph_avx512f ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115319 define pcodeop vpmovdb_avx512vl ; -:VPMOVDB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovdb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -585,7 +585,7 @@ define pcodeop vpmovdb_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVDB m32 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; XmmReg1 ... & m32 +:VPMOVDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovdb_avx512vl( XmmReg1 ); @@ -596,7 +596,7 @@ define pcodeop vpmovdb_avx512vl ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115322 define pcodeop vpmovsdb_avx512vl ; -:VPMOVSDB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsdb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -604,7 +604,7 @@ define pcodeop vpmovsdb_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVSDB m32 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; XmmReg1 ... & m32 +:VPMOVSDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovsdb_avx512vl( XmmReg1 ); @@ -614,7 +614,7 @@ define pcodeop vpmovsdb_avx512vl ; } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115326 define pcodeop vpmovusdb_avx512vl ; -:VPMOVUSDB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusdb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -622,7 +622,7 @@ define pcodeop vpmovusdb_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVUSDB m32 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; XmmReg1 ... & m32 +:VPMOVUSDB m32^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovusdb_avx512vl( XmmReg1 ); @@ -632,7 +632,7 @@ define pcodeop vpmovusdb_avx512vl ; } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115330 -:VPMOVDB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovdb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -640,7 +640,7 @@ define pcodeop vpmovusdb_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVDB m64 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; YmmReg1 ... & m64 +:VPMOVDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovdb_avx512vl( YmmReg1 ); @@ -650,7 +650,7 @@ define pcodeop vpmovusdb_avx512vl ; } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115333 -:VPMOVSDB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsdb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -658,7 +658,7 @@ define pcodeop vpmovusdb_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVSDB m64 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; YmmReg1 ... & m64 +:VPMOVSDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovsdb_avx512vl( YmmReg1 ); @@ -668,7 +668,7 @@ define pcodeop vpmovusdb_avx512vl ; } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115337 -:VPMOVUSDB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusdb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -676,7 +676,7 @@ define pcodeop vpmovusdb_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVUSDB m64 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; YmmReg1 ... & m64 +:VPMOVUSDB m64^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovusdb_avx512vl( YmmReg1 ); @@ -687,7 +687,7 @@ define pcodeop vpmovusdb_avx512vl ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115341 define pcodeop vpmovdb_avx512f ; -:VPMOVDB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovdb_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -695,7 +695,7 @@ define pcodeop vpmovdb_avx512f ; ZmmReg2 = zext(XmmResult); } -:VPMOVDB m128 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; ZmmReg1 ... & m128 +:VPMOVDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x31; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovdb_avx512f( ZmmReg1 ); @@ -706,7 +706,7 @@ define pcodeop vpmovdb_avx512f ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115344 define pcodeop vpmovsdb_avx512f ; -:VPMOVSDB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsdb_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -714,7 +714,7 @@ define pcodeop vpmovsdb_avx512f ; ZmmReg2 = zext(XmmResult); } -:VPMOVSDB m128 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; ZmmReg1 ... & m128 +:VPMOVSDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x21; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovsdb_avx512f( ZmmReg1 ); @@ -725,7 +725,7 @@ define pcodeop vpmovsdb_avx512f ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115348 define pcodeop vpmovusdb_avx512f ; -:VPMOVUSDB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusdb_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -733,7 +733,7 @@ define pcodeop vpmovusdb_avx512f ; ZmmReg2 = zext(XmmResult); } -:VPMOVUSDB m128 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; ZmmReg1 ... & m128 +:VPMOVUSDB m128^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x11; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovusdb_avx512f( ZmmReg1 ); @@ -744,7 +744,7 @@ define pcodeop vpmovusdb_avx512f ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115532 define pcodeop vpmovdw_avx512vl ; -:VPMOVDW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovdw_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -752,7 +752,7 @@ define pcodeop vpmovdw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVDW m64 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; XmmReg1 ... & m64 +:VPMOVDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovdw_avx512vl( XmmReg1 ); @@ -763,7 +763,7 @@ define pcodeop vpmovdw_avx512vl ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115535 define pcodeop vpmovsdw_avx512vl ; -:VPMOVSDW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsdw_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -771,7 +771,7 @@ define pcodeop vpmovsdw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVSDW m64 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; XmmReg1 ... & m64 +:VPMOVSDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovsdw_avx512vl( XmmReg1 ); @@ -782,7 +782,7 @@ define pcodeop vpmovsdw_avx512vl ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115539 define pcodeop vpmovusdw_avx512vl ; -:VPMOVUSDW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusdw_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -790,7 +790,7 @@ define pcodeop vpmovusdw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVUSDW m64 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; XmmReg1 ... & m64 +:VPMOVUSDW m64^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovusdw_avx512vl( XmmReg1 ); @@ -800,7 +800,7 @@ define pcodeop vpmovusdw_avx512vl ; } # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115543 -:VPMOVDW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovdw_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -808,7 +808,7 @@ define pcodeop vpmovusdw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVDW m128 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; YmmReg1 ... & m128 +:VPMOVDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x33; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovdw_avx512vl( YmmReg1 ); @@ -818,7 +818,7 @@ define pcodeop vpmovusdw_avx512vl ; } # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115546 -:VPMOVSDW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsdw_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -826,7 +826,7 @@ define pcodeop vpmovusdw_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVSDW m128 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; YmmReg1 ... & m128 +:VPMOVSDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x23; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovsdw_avx512vl( YmmReg1 ); @@ -836,7 +836,7 @@ define pcodeop vpmovusdw_avx512vl ; } # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115550 -:VPMOVUSDW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusdw_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -844,7 +844,7 @@ define pcodeop vpmovusdw_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVUSDW m128 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; YmmReg1 ... & m128 +:VPMOVUSDW m128^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x13; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovusdw_avx512vl( YmmReg1 ); @@ -855,7 +855,7 @@ define pcodeop vpmovusdw_avx512vl ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115554 define pcodeop vpmovdw_avx512f ; -:VPMOVDW YmmReg2 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovdw_avx512f( ZmmReg1 ); YmmMask = YmmReg2; @@ -863,7 +863,7 @@ define pcodeop vpmovdw_avx512f ; ZmmReg2 = zext(YmmResult); } -:VPMOVDW m256 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; ZmmReg1 ... & m256 +:VPMOVDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x33; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovdw_avx512f( ZmmReg1 ); @@ -874,7 +874,7 @@ define pcodeop vpmovdw_avx512f ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115557 define pcodeop vpmovsdw_avx512f ; -:VPMOVSDW YmmReg2 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVSDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovsdw_avx512f( ZmmReg1 ); YmmMask = YmmReg2; @@ -882,7 +882,7 @@ define pcodeop vpmovsdw_avx512f ; ZmmReg2 = zext(YmmResult); } -:VPMOVSDW m256 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; ZmmReg1 ... & m256 +:VPMOVSDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x23; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovsdw_avx512f( ZmmReg1 ); @@ -893,7 +893,7 @@ define pcodeop vpmovsdw_avx512f ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115561 define pcodeop vpmovusdw_avx512f ; -:VPMOVUSDW YmmReg2 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVUSDW YmmReg2^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovusdw_avx512f( ZmmReg1 ); YmmMask = YmmReg2; @@ -901,7 +901,7 @@ define pcodeop vpmovusdw_avx512f ; ZmmReg2 = zext(YmmResult); } -:VPMOVUSDW m256 YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; ZmmReg1 ... & m256 +:VPMOVUSDW m256^YmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask16; byte=0x13; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovusdw_avx512f( ZmmReg1 ); @@ -912,7 +912,7 @@ define pcodeop vpmovusdw_avx512f ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114671 define pcodeop vpmovqb_avx512vl ; -:VPMOVQB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -920,7 +920,7 @@ define pcodeop vpmovqb_avx512vl ; ZmmReg2 = zext(XmmResult[0,16]); } -:VPMOVQB m16 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; XmmReg1 ... & m16 +:VPMOVQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; XmmReg1 ... & m16 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovqb_avx512vl( XmmReg1 ); @@ -931,7 +931,7 @@ define pcodeop vpmovqb_avx512vl ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114674 define pcodeop vpmovsqb_avx512vl ; -:VPMOVSQB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -939,7 +939,7 @@ define pcodeop vpmovsqb_avx512vl ; ZmmReg2 = zext(XmmResult[0,16]); } -:VPMOVSQB m16 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; XmmReg1 ... & m16 +:VPMOVSQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; XmmReg1 ... & m16 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovsqb_avx512vl( XmmReg1 ); @@ -950,7 +950,7 @@ define pcodeop vpmovsqb_avx512vl ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114678 define pcodeop vpmovusqb_avx512vl ; -:VPMOVUSQB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -958,7 +958,7 @@ define pcodeop vpmovusqb_avx512vl ; ZmmReg2 = zext(XmmResult[0,16]); } -:VPMOVUSQB m16 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; XmmReg1 ... & m16 +:VPMOVUSQB m16^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; XmmReg1 ... & m16 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovusqb_avx512vl( XmmReg1 ); @@ -968,7 +968,7 @@ define pcodeop vpmovusqb_avx512vl ; } # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114682 -:VPMOVQB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -976,7 +976,7 @@ define pcodeop vpmovusqb_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVQB m32 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; YmmReg1 ... & m32 +:VPMOVQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovqb_avx512vl( YmmReg1 ); @@ -986,7 +986,7 @@ define pcodeop vpmovusqb_avx512vl ; } # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114685 -:VPMOVSQB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -994,7 +994,7 @@ define pcodeop vpmovusqb_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVSQB m32 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; YmmReg1 ... & m32 +:VPMOVSQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovsqb_avx512vl( YmmReg1 ); @@ -1004,7 +1004,7 @@ define pcodeop vpmovusqb_avx512vl ; } # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114689 -:VPMOVUSQB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1012,7 +1012,7 @@ define pcodeop vpmovusqb_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVUSQB m32 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; YmmReg1 ... & m32 +:VPMOVUSQB m32^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovusqb_avx512vl( YmmReg1 ); @@ -1023,7 +1023,7 @@ define pcodeop vpmovusqb_avx512vl ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114693 define pcodeop vpmovqb_avx512f ; -:VPMOVQB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqb_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -1031,7 +1031,7 @@ define pcodeop vpmovqb_avx512f ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVQB m64 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; ZmmReg1 ... & m64 +:VPMOVQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x32; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovqb_avx512f( ZmmReg1 ); @@ -1042,7 +1042,7 @@ define pcodeop vpmovqb_avx512f ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114696 define pcodeop vpmovsqb_avx512f ; -:VPMOVSQB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqb_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -1050,7 +1050,7 @@ define pcodeop vpmovsqb_avx512f ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVSQB m64 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; ZmmReg1 ... & m64 +:VPMOVSQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x22; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovsqb_avx512f( ZmmReg1 ); @@ -1061,7 +1061,7 @@ define pcodeop vpmovsqb_avx512f ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114700 define pcodeop vpmovusqb_avx512f ; -:VPMOVUSQB XmmReg2 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQB XmmReg2^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqb_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -1069,7 +1069,7 @@ define pcodeop vpmovusqb_avx512f ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVUSQB m64 XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; ZmmReg1 ... & m64 +:VPMOVUSQB m64^XmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x12; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { XmmResult = vpmovusqb_avx512f( ZmmReg1 ); @@ -1080,7 +1080,7 @@ define pcodeop vpmovusqb_avx512f ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114887 define pcodeop vpmovqw_avx512vl ; -:VPMOVQW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqw_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1088,7 +1088,7 @@ define pcodeop vpmovqw_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVQW m32 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; XmmReg1 ... & m32 +:VPMOVQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovqw_avx512vl( XmmReg1 ); @@ -1099,7 +1099,7 @@ define pcodeop vpmovqw_avx512vl ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114890 define pcodeop vpmovsqw_avx512vl ; -:VPMOVSQW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqw_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1107,7 +1107,7 @@ define pcodeop vpmovsqw_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVSQW m32 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; XmmReg1 ... & m32 +:VPMOVSQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovsqw_avx512vl( XmmReg1 ); @@ -1118,7 +1118,7 @@ define pcodeop vpmovsqw_avx512vl ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114894 define pcodeop vpmovusqw_avx512vl ; -:VPMOVUSQW XmmReg2 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQW XmmReg2^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqw_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1126,7 +1126,7 @@ define pcodeop vpmovusqw_avx512vl ; ZmmReg2 = zext(XmmResult[0,32]); } -:VPMOVUSQW m32 XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; XmmReg1 ... & m32 +:VPMOVUSQW m32^XmmOpMask16, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovusqw_avx512vl( XmmReg1 ); @@ -1136,7 +1136,7 @@ define pcodeop vpmovusqw_avx512vl ; } # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114898 -:VPMOVQW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqw_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1144,7 +1144,7 @@ define pcodeop vpmovusqw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVQW m64 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; YmmReg1 ... & m64 +:VPMOVQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovqw_avx512vl( YmmReg1 ); @@ -1154,7 +1154,7 @@ define pcodeop vpmovusqw_avx512vl ; } # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114901 -:VPMOVSQW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqw_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1162,7 +1162,7 @@ define pcodeop vpmovusqw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVSQW m64 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; YmmReg1 ... & m64 +:VPMOVSQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovsqw_avx512vl( YmmReg1 ); @@ -1172,7 +1172,7 @@ define pcodeop vpmovusqw_avx512vl ; } # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114905 -:VPMOVUSQW XmmReg2 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQW XmmReg2^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqw_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1180,7 +1180,7 @@ define pcodeop vpmovusqw_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVUSQW m64 XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; YmmReg1 ... & m64 +:VPMOVUSQW m64^XmmOpMask16, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovusqw_avx512vl( YmmReg1 ); @@ -1191,7 +1191,7 @@ define pcodeop vpmovusqw_avx512vl ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114909 define pcodeop vpmovqw_avx512f ; -:VPMOVQW XmmReg2 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqw_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -1199,7 +1199,7 @@ define pcodeop vpmovqw_avx512f ; ZmmReg2 = zext(XmmResult); } -:VPMOVQW m128 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; ZmmReg1 ... & m128 +:VPMOVQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x34; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovqw_avx512f( ZmmReg1 ); @@ -1210,7 +1210,7 @@ define pcodeop vpmovqw_avx512f ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114912 define pcodeop vpmovsqw_avx512f ; -:VPMOVSQW XmmReg2 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqw_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -1218,7 +1218,7 @@ define pcodeop vpmovsqw_avx512f ; ZmmReg2 = zext(XmmResult); } -:VPMOVSQW m128 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; ZmmReg1 ... & m128 +:VPMOVSQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x24; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovsqw_avx512f( ZmmReg1 ); @@ -1229,7 +1229,7 @@ define pcodeop vpmovsqw_avx512f ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114916 define pcodeop vpmovusqw_avx512f ; -:VPMOVUSQW XmmReg2 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQW XmmReg2^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqw_avx512f( ZmmReg1 ); XmmMask = XmmReg2; @@ -1237,7 +1237,7 @@ define pcodeop vpmovusqw_avx512f ; ZmmReg2 = zext(XmmResult); } -:VPMOVUSQW m128 XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; ZmmReg1 ... & m128 +:VPMOVUSQW m128^XmmOpMask16, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask16; byte=0x14; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { XmmResult = vpmovusqw_avx512f( ZmmReg1 ); @@ -1248,7 +1248,7 @@ define pcodeop vpmovusqw_avx512f ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115104 define pcodeop vpmovqd_avx512vl ; -:VPMOVQD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqd_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1256,7 +1256,7 @@ define pcodeop vpmovqd_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVQD m128 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; XmmReg1 ... & m128 +:VPMOVQD m128^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovqd_avx512vl( XmmReg1 ); @@ -1267,7 +1267,7 @@ define pcodeop vpmovqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115108 define pcodeop vpmovsqd_avx512vl ; -:VPMOVSQD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqd_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1275,7 +1275,7 @@ define pcodeop vpmovsqd_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVSQD m64 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; XmmReg1 ... & m64 +:VPMOVSQD m64^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovsqd_avx512vl( XmmReg1 ); @@ -1286,7 +1286,7 @@ define pcodeop vpmovsqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115113 define pcodeop vpmovusqd_avx512vl ; -:VPMOVUSQD XmmReg2 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQD XmmReg2^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqd_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1294,7 +1294,7 @@ define pcodeop vpmovusqd_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVUSQD m64 XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; XmmReg1 ... & m64 +:VPMOVUSQD m64^XmmOpMask32, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovusqd_avx512vl( XmmReg1 ); @@ -1305,7 +1305,7 @@ define pcodeop vpmovusqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115118 -:VPMOVQD XmmReg2 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovqd_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1313,7 +1313,7 @@ define pcodeop vpmovusqd_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVQD m128 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; YmmReg1 ... & m128 +:VPMOVQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x35; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovqd_avx512vl( YmmReg1 ); @@ -1323,7 +1323,7 @@ define pcodeop vpmovusqd_avx512vl ; } # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115122 -:VPMOVSQD XmmReg2 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovsqd_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1331,7 +1331,7 @@ define pcodeop vpmovusqd_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVSQD m128 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; YmmReg1 ... & m128 +:VPMOVSQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x25; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovsqd_avx512vl( YmmReg1 ); @@ -1341,7 +1341,7 @@ define pcodeop vpmovusqd_avx512vl ; } # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115127 -:VPMOVUSQD XmmReg2 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQD XmmReg2^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovusqd_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1349,7 +1349,7 @@ define pcodeop vpmovusqd_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVUSQD m128 XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; YmmReg1 ... & m128 +:VPMOVUSQD m128^XmmOpMask32, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask32; byte=0x15; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovusqd_avx512vl( YmmReg1 ); @@ -1360,7 +1360,7 @@ define pcodeop vpmovusqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115131 define pcodeop vpmovqd_avx512f ; -:VPMOVQD YmmReg2 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovqd_avx512f( ZmmReg1 ); YmmMask = YmmReg2; @@ -1368,7 +1368,7 @@ define pcodeop vpmovqd_avx512f ; ZmmReg2 = zext(YmmResult); } -:VPMOVQD m256 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; ZmmReg1 ... & m256 +:VPMOVQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x35; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovqd_avx512f( ZmmReg1 ); @@ -1379,7 +1379,7 @@ define pcodeop vpmovqd_avx512f ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115134 define pcodeop vpmovsqd_avx512f ; -:VPMOVSQD YmmReg2 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVSQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovsqd_avx512f( ZmmReg1 ); YmmMask = YmmReg2; @@ -1387,7 +1387,7 @@ define pcodeop vpmovsqd_avx512f ; ZmmReg2 = zext(YmmResult); } -:VPMOVSQD m256 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; ZmmReg1 ... & m256 +:VPMOVSQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x25; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovsqd_avx512f( ZmmReg1 ); @@ -1398,7 +1398,7 @@ define pcodeop vpmovsqd_avx512f ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115138 define pcodeop vpmovusqd_avx512f ; -:VPMOVUSQD YmmReg2 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVUSQD YmmReg2^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovusqd_avx512f( ZmmReg1 ); YmmMask = YmmReg2; @@ -1406,7 +1406,7 @@ define pcodeop vpmovusqd_avx512f ; ZmmReg2 = zext(YmmResult); } -:VPMOVUSQD m256 YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; ZmmReg1 ... & m256 +:VPMOVUSQD m256^YmmOpMask32, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask32; byte=0x15; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovusqd_avx512f( ZmmReg1 ); @@ -1417,7 +1417,7 @@ define pcodeop vpmovusqd_avx512f ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115748 define pcodeop vpmovwb_avx512vl ; -:VPMOVWB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovwb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1425,7 +1425,7 @@ define pcodeop vpmovwb_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVWB m64 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; XmmReg1 ... & m64 +:VPMOVWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovwb_avx512vl( XmmReg1 ); @@ -1436,7 +1436,7 @@ define pcodeop vpmovwb_avx512vl ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115751 define pcodeop vpmovswb_avx512vl ; -:VPMOVSWB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovswb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1444,7 +1444,7 @@ define pcodeop vpmovswb_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVSWB m64 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; XmmReg1 ... & m64 +:VPMOVSWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovswb_avx512vl( XmmReg1 ); @@ -1455,7 +1455,7 @@ define pcodeop vpmovswb_avx512vl ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115754 define pcodeop vpmovuswb_avx512vl ; -:VPMOVUSWB XmmReg2 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSWB XmmReg2^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovuswb_avx512vl( XmmReg1 ); XmmMask = XmmReg2; @@ -1463,7 +1463,7 @@ define pcodeop vpmovuswb_avx512vl ; ZmmReg2 = zext(XmmResult[0,64]); } -:VPMOVUSWB m64 XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; XmmReg1 ... & m64 +:VPMOVUSWB m64^XmmOpMask8, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovuswb_avx512vl( XmmReg1 ); @@ -1473,7 +1473,7 @@ define pcodeop vpmovuswb_avx512vl ; } # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115757 -:VPMOVWB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovwb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1482,7 +1482,7 @@ define pcodeop vpmovuswb_avx512vl ; } -:VPMOVWB m128 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; YmmReg1 ... & m128 +:VPMOVWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x30; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovwb_avx512vl( YmmReg1 ); @@ -1492,7 +1492,7 @@ define pcodeop vpmovuswb_avx512vl ; } # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115760 -:VPMOVSWB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovswb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1500,7 +1500,7 @@ define pcodeop vpmovuswb_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVSWB m128 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; YmmReg1 ... & m128 +:VPMOVSWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x20; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovswb_avx512vl( YmmReg1 ); @@ -1510,7 +1510,7 @@ define pcodeop vpmovuswb_avx512vl ; } # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115763 -:VPMOVUSWB XmmReg2 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSWB XmmReg2^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmResult = vpmovuswb_avx512vl( YmmReg1 ); XmmMask = XmmReg2; @@ -1518,7 +1518,7 @@ define pcodeop vpmovuswb_avx512vl ; ZmmReg2 = zext(XmmResult); } -:VPMOVUSWB m128 XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; YmmReg1 ... & m128 +:VPMOVUSWB m128^XmmOpMask8, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & XmmOpMask8; byte=0x10; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { XmmResult = vpmovuswb_avx512vl( YmmReg1 ); @@ -1529,7 +1529,7 @@ define pcodeop vpmovuswb_avx512vl ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115766 define pcodeop vpmovwb_avx512bw ; -:VPMOVWB YmmReg2 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovwb_avx512bw( ZmmReg1 ); YmmMask = YmmReg2; @@ -1537,7 +1537,7 @@ define pcodeop vpmovwb_avx512bw ; ZmmReg2 = zext(YmmResult); } -:VPMOVWB m256 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; ZmmReg1 ... & m256 +:VPMOVWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x30; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovwb_avx512bw( ZmmReg1 ); @@ -1548,7 +1548,7 @@ define pcodeop vpmovwb_avx512bw ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115769 define pcodeop vpmovswb_avx512bw ; -:VPMOVSWB YmmReg2 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVSWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovswb_avx512bw( ZmmReg1 ); YmmMask = YmmReg2; @@ -1556,7 +1556,7 @@ define pcodeop vpmovswb_avx512bw ; ZmmReg2 = zext(YmmResult); } -:VPMOVSWB m256 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; ZmmReg1 ... & m256 +:VPMOVSWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x20; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovswb_avx512bw( ZmmReg1 ); @@ -1567,7 +1567,7 @@ define pcodeop vpmovswb_avx512bw ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115772 define pcodeop vpmovuswb_avx512bw ; -:VPMOVUSWB YmmReg2 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVUSWB YmmReg2^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmResult = vpmovuswb_avx512bw( ZmmReg1 ); YmmMask = YmmReg2; @@ -1575,7 +1575,7 @@ define pcodeop vpmovuswb_avx512bw ; ZmmReg2 = zext(YmmResult); } -:VPMOVUSWB m256 YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; ZmmReg1 ... & m256 +:VPMOVUSWB m256^YmmOpMask8, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & YmmOpMask8; byte=0x10; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { YmmResult = vpmovuswb_avx512bw( ZmmReg1 );