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Cleaning up warnings and errors, mostly looking for:

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temporary is written but not read in constructor
This commit is contained in:
mumbel
2020-01-20 18:52:48 -06:00
parent 6ae0c1ce23
commit dce6e9f6a8
16 changed files with 65 additions and 45 deletions
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Ghidra/Processors/6805/data/languages/6805.slaspec
+3 -1
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@@ -628,7 +628,9 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
*:1 SP = X; *:1 SP = X;
SP=SP-1; SP=SP-1;
*:1 SP = A; *:1 SP = A;
tmp:1 = (H << 4) | (I << 3) | (N << 2) | ( Z << 1) | C; tmp:1 = 0b11100000 | (H << 4) | (I << 3) | (N << 2) | ( Z << 1) | C;
SP=SP-1;
*:1 SP = tmp;
I = 1; I = 1;
call [SWI_VECTOR]; call [SWI_VECTOR];
} }
Ghidra/Processors/6805/data/languages/6x09_pull.sinc
+2 -2
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@@ -18,7 +18,7 @@ puls5: puls4" "Y is Y & imm85=1 & puls4 { Pull2(S, Y); }
puls5: puls4 is imm85=0 & puls4 { } puls5: puls4 is imm85=0 & puls4 { }
puls6: puls5" "U is U & imm86=1 & puls5 { Pull2(S, U); } puls6: puls5" "U is U & imm86=1 & puls5 { Pull2(S, U); }
puls6: puls5 is imm86=0 & puls5 { } puls6: puls5 is imm86=0 & puls5 { }
puls7: puls6" "PC is PC & imm87=1 & puls6 { local t:2 = inst_next; Pull2(S, t); } puls7: puls6" "PC is PC & imm87=1 & puls6 { local t:2 = 0; Pull2(S, t); goto [t]; }
puls7: puls6 is imm87=0 & puls6 { } puls7: puls6 is imm87=0 & puls6 { }
:PULS puls7 is op=0x35; puls7 { } :PULS puls7 is op=0x35; puls7 { }
@@ -41,7 +41,7 @@ pulu5: pulu4" "Y is Y & imm85=1 & pulu4 { Pull2(U, Y); }
pulu5: pulu4 is imm85=0 & pulu4 { } pulu5: pulu4 is imm85=0 & pulu4 { }
pulu6: pulu5" "S is S & imm86=1 & pulu5 { Pull2(U, S); } pulu6: pulu5" "S is S & imm86=1 & pulu5 { Pull2(U, S); }
pulu6: pulu5 is imm86=0 & pulu5 { } pulu6: pulu5 is imm86=0 & pulu5 { }
pulu7: pulu6" "PC is PC & imm87=1 & pulu6 { local t:2 = inst_next; Pull2(U, t); } pulu7: pulu6" "PC is PC & imm87=1 & pulu6 { local t:2 = 0; Pull2(U, t); goto [t]; }
pulu7: pulu6 is imm87=0 & pulu6 { } pulu7: pulu6 is imm87=0 & pulu6 { }
:PULU pulu7 is op=0x37; pulu7 { } :PULU pulu7 is op=0x37; pulu7 { }
Ghidra/Processors/8048/data/languages/8048.slaspec
+1 -1
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@@ -199,7 +199,7 @@ macro xch(node1, node2) {
} }
@ifdef SINGLE_REGISTER_BANK @ifdef SINGLE_REGISTER_BANK
macro regbank(r) { } macro regbank(r) { r = r; }
macro setbank(bs) { macro setbank(bs) {
BS = bs; BS = bs;
local tmp:1 = bs; local tmp:1 = bs;
Ghidra/Processors/8051/data/languages/80251.sinc
+1 -1
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@@ -573,7 +573,7 @@ macro pop24(val) {
:PUSH drk47 is $(GROUP3) & ophi=12 & oplo=10; $(DRK47) & s03=11 { push16(drk47); } :PUSH drk47 is $(GROUP3) & ophi=12 & oplo=10; $(DRK47) & s03=11 { push16(drk47); }
# SETB bit # SETB bit
:SETB xBitAddr^"."^xBitByteAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=13 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitBtyteAddr:1 = (xBitByteAddr) | (1 << bit02); } :SETB xBitAddr^"."^xBitByteAddr is $(GROUP3) & ophi=10 & oplo=9; (d47=13 & s3=0 & bit02; xBitByteAddr) & xBitAddr { xBitByteAddr = (xBitByteAddr) | (1 << bit02); }
# SLL Rm # SLL Rm
:SLL rm47 is $(GROUP3) & ophi=3 & oplo=14; rm47 & s03=0 { $(CY) = ((rm47>>7) & 1); rm47 = rm47 << 1; resultflags(rm47); } :SLL rm47 is $(GROUP3) & ophi=3 & oplo=14; rm47 & s03=0 { $(CY) = ((rm47>>7) & 1); rm47 = rm47 << 1; resultflags(rm47); }
Ghidra/Processors/8051/data/languages/8051_main.sinc
+12 -4
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@@ -360,14 +360,16 @@ macro push8(val) {
#tmp:3 = zext(SP) + $(STACKBASE); #tmp:3 = zext(SP) + $(STACKBASE);
tmp:3 = SP; tmp:3 = SP;
*[RAM]:1 tmp = val; *[RAM]:1 tmp = val;
@else
val = val;
@endif @endif
} }
@ifdef OMIT_RETADDR @ifdef OMIT_RETADDR
@ifdef MCS80390 @ifdef MCS80390
macro push24(val) { } macro push24(val) { val = val; }
@else @else
macro push16(val) { } macro push16(val) { val = val; }
@endif @endif
@else @else
@@ -404,6 +406,8 @@ macro push16(val) {
*[RAM]:1 SP = al; *[RAM]:1 SP = al;
SP = SP + 1; SP = SP + 1;
*[RAM]:1 SP = ah; *[RAM]:1 SP = ah;
@else
val = val;
@endif @endif
} }
@else @else
@@ -436,12 +440,14 @@ macro pop8(val) {
ptr:3 = SP; ptr:3 = SP;
val = *[RAM]:1 ptr; val = *[RAM]:1 ptr;
SP = SP - 1; SP = SP - 1;
@else
val = val;
@endif @endif
} }
@if defined(MCS80390) @if defined(MCS80390)
@ifdef OMIT_RETADDR @ifdef OMIT_RETADDR
macro pop24(val) { } macro pop24(val) { val = val; }
@else @else
macro pop24(val) { macro pop24(val) {
ptr:1 = SP - 2; ptr:1 = SP - 2;
@@ -460,7 +466,7 @@ macro pop24(val) {
@endif @endif
@else @else
@ifdef OMIT_RETADDR @ifdef OMIT_RETADDR
macro pop16(val) { } macro pop16(val) { val = val; }
@else @else
macro pop16(val) { macro pop16(val) {
@if defined(MCS251) @if defined(MCS251)
@@ -489,6 +495,8 @@ macro pop16(val) {
SP = SP - 1; SP = SP - 1;
val = (zext(ah) << 8) | zext(al); val = (zext(ah) << 8) | zext(al);
@else
val = val;
@endif @endif
} }
@endif @endif
Ghidra/Processors/8051/data/languages/mx51.sinc
+2 -2
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@@ -31,8 +31,8 @@ PRi: PRi_revend is PRi_sel=1 & PRi_revend { tmp:3 = (zext(R7) << 16) | (zext(R6)
#################### ####################
@ifdef OMIT_RETADDR @ifdef OMIT_RETADDR
macro push24(val) { } macro push24(val) { val = val; }
macro pop24(val) { } macro pop24(val) { val = val; }
@else @else
# stack grows up. # stack grows up.
Ghidra/Processors/8085/data/languages/8085.slaspec
+1 -1
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@@ -373,7 +373,7 @@ cc: "M" is bits3_3=0x7 { export S_flag;
val:1 = *:1 HL; val:1 = *:1 HL;
setSubtractFlags(A,val); setSubtractFlags(A,val);
cmp:1 = A - val; cmp:1 = A - val;
setResultFlags(val); setResultFlags(cmp);
} }
:INR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 { :INR reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x4 {
Ghidra/Processors/ARM/data/languages/ARMneon.sinc
+28 -16
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@@ -423,20 +423,20 @@ simdExpImmDT: "i64" is TMode=1 & thv_c0811=14 & thv_c0505=1 { }
simdExpImmDT: "f32" is TMode=1 & thv_c0811=15 & thv_c0505=0 { } simdExpImmDT: "f32" is TMode=1 & thv_c0811=15 & thv_c0505=0 { }
macro replicate1to8(bytes, dest) { macro replicate1to8(bytes, dest) {
val:8 = zext(bytes); local val:8 = zext(bytes);
val = val | (val << 8); val = val | (val << 8);
val = val | (val << 16); val = val | (val << 16);
dest = val | (val << 32); dest = val | (val << 32);
} }
macro replicate2to8(bytes, dest) { macro replicate2to8(bytes, dest) {
val:8 = zext(bytes); local val:8 = zext(bytes);
val = val | (val << 16); val = val | (val << 16);
dest = val | (val << 32); dest = val | (val << 32);
} }
macro replicate4to8(bytes, dest) { macro replicate4to8(bytes, dest) {
val:8 = zext(bytes); local val:8 = zext(bytes);
dest = val | (val << 32); dest = val | (val << 32);
} }
@@ -3745,24 +3745,30 @@ define pcodeop VectorShiftNarrowRight;
vst1Dd: Dreg is Dreg & c0607=0 vst1Dd: Dreg is Dreg & c0607=0
{ {
local tmpDreg = Dreg; local tmpDreg = Dreg;
val:1 = tmpDreg:1; local val:1 = tmpDreg:1;
replicate1to8(val, *:8 mult_addr); local tmp8:8 = 0;
replicate1to8(val, tmp8);
*:8 mult_addr = tmp8;
} }
vst1Dd: Dreg is Dreg & c0607=1 vst1Dd: Dreg is Dreg & c0607=1
{ {
local tmpDreg = Dreg; local tmpDreg = Dreg;
val:2 = tmpDreg:2; local val:2 = tmpDreg:2;
replicate2to8(val, *:8 mult_addr); local tmp8:8 = 0;
replicate2to8(val, tmp8);
*:8 mult_addr = tmp8;
} }
vst1Dd: Dreg is Dreg & c0607=2 vst1Dd: Dreg is Dreg & c0607=2
{ {
local tmpDreg = Dreg; local tmpDreg = Dreg;
val:4 = tmpDreg:4; local val:4 = tmpDreg:4;
replicate4to8(val, *:8 mult_addr); local tmp8:8 = 0;
replicate4to8(val, tmp8);
*:8 mult_addr = tmp8;
} }
vst1Dd: Dreg is Dreg & c0607=3 vst1Dd: Dreg is Dreg & c0607=3
{ {
*:8 mult_addr = Dreg; *:8 mult_addr = Dreg;
} }
buildVst1DdList: is counter=0 { } buildVst1DdList: is counter=0 { }
@@ -3804,20 +3810,26 @@ vst1DdList: "{"^buildVst1DdList^"}" is c0811=2 & D22 & c1215 & buildVst1DdList [
thv_vst1Dd: Dreg is Dreg & thv_c0607=0 thv_vst1Dd: Dreg is Dreg & thv_c0607=0
{ {
local tmpDreg = Dreg; local tmpDreg = Dreg;
val:1 = tmpDreg:1; local val:1 = tmpDreg:1;
replicate1to8(val, *:8 mult_addr); local tmp8:8 = 0;
replicate1to8(val, tmp8);
*:8 mult_addr = tmp8;
} }
thv_vst1Dd: Dreg is Dreg & thv_c0607=1 thv_vst1Dd: Dreg is Dreg & thv_c0607=1
{ {
local tmpDreg = Dreg; local tmpDreg = Dreg;
val:2 = tmpDreg:2; local val:2 = tmpDreg:2;
replicate2to8(val, *:8 mult_addr); local tmp8:8 = 0;
replicate2to8(val, tmp8);
*:8 mult_addr = tmp8;
} }
thv_vst1Dd: Dreg is Dreg & thv_c0607=2 thv_vst1Dd: Dreg is Dreg & thv_c0607=2
{ {
local tmpDreg = Dreg; local tmpDreg = Dreg;
val:4 = tmpDreg:4; local val:4 = tmpDreg:4;
replicate4to8(val, *:8 mult_addr); local tmp8:8 = 0;
replicate4to8(val, tmp8);
*:8 mult_addr = tmp8;
} }
thv_vst1Dd: Dreg is Dreg & thv_c0607=3 thv_vst1Dd: Dreg is Dreg & thv_c0607=3
{ {
Ghidra/Processors/Atmel/data/languages/avr8.sinc
+2
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@@ -682,10 +682,12 @@ define pcodeop break;
:cpc RdFull,RrFull is phase=1 & ophi6=0x1 & RdFull & RrFull { :cpc RdFull,RrFull is phase=1 & ophi6=0x1 & RdFull & RrFull {
local res = 0; local res = 0;
doSubtractWithCarry(RdFull,RrFull,res); doSubtractWithCarry(RdFull,RrFull,res);
res = res; # avoid warning
} }
:cpi RdHi,K8 is phase=1 & ophi4=0x3 & RdHi & K8 { :cpi RdHi,K8 is phase=1 & ophi4=0x3 & RdHi & K8 {
local res = 0; local res = 0;
doSubtract(RdHi,K8,res); doSubtract(RdHi,K8,res);
res = res; # avoid warning
} }
@ifdef FUSION @ifdef FUSION
Ghidra/Processors/Dalvik/data/languages/Dalvik.slaspec
+2 -1
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@@ -806,7 +806,8 @@ define pcodeop switchAssist;
:packed_switch registerA8,B_BITS_0_31_S is inst0=0x2b ; registerA8 ; B_BITS_0_31_S :packed_switch registerA8,B_BITS_0_31_S is inst0=0x2b ; registerA8 ; B_BITS_0_31_S
{ {
distance:4 = B_BITS_0_31_S * 2; distance:4 = B_BITS_0_31_S * 2;
ident:4 = *[ram] ( inst_start + distance ); # ident:2 = *[ram] ( inst_start + distance );
# if (ident != 0x0100) goto inst_next;
size2:2 = *[ram] ( inst_start + distance + 2 ); size2:2 = *[ram] ( inst_start + distance + 2 );
sze:4 = zext( size2 ); sze:4 = zext( size2 );
first_key:4 = *[ram] ( inst_start + distance + 2 + 2 ); first_key:4 = *[ram] ( inst_start + distance + 2 + 2 );
Ghidra/Processors/MCS96/data/languages/MCS96.sinc
+1
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@@ -1218,6 +1218,7 @@ cc: "E" is cond=15 { tmp:1 = ($(Z) == 1); export tmp; }
:SKIP is op8=0x00 { :SKIP is op8=0x00 {
local tmp:1 = 0; local tmp:1 = 0;
tmp = tmp; # avoid warning
} #2-byte NOP } #2-byte NOP
:ST wreg, oper16 is op6=0x30 ... & oper16; wreg { :ST wreg, oper16 is op6=0x30 ... & oper16; wreg {
Ghidra/Processors/MIPS/data/languages/mipsfloat.sinc
+1 -2
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@@ -28,7 +28,6 @@ define pcodeop mipsFloatPS;
# 0100 01ff ffft tttt ssss sddd dd00 0000 # 0100 01ff ffft tttt ssss sddd dd00 0000
:add.S fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x10 & ft & fs & fd { :add.S fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x10 & ft & fs & fd {
fd_tmp:4 = fs:4 f+ ft:4;
fd[0,32] = fs:4 f+ ft:4; fd[0,32] = fs:4 f+ ft:4;
} }
:add.D fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x11 & ft & fs & fd & ftD & fsD & fdD { :add.D fd, fs, ft is $(AMODE) & prime=17 & fct=0 & fmt1 & format=0x11 & ft & fs & fd & ftD & fsD & fdD {
@@ -53,7 +52,7 @@ define pcodeop mipsFloatPS;
# 0100 01ff fff0 0000 ssss sddd dd00 1110 # 0100 01ff fff0 0000 ssss sddd dd00 1110
:ceil.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x10 { :ceil.w.S fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x10 {
fs_ceil_tmp:4 = ceil(fs:4); # Note that ceil returns a float the same size as its argument fs_ceil_tmp:4 = ceil(fs:4); # Note that ceil returns a float the same size as its argument
fd[0,32] = trunc( ceil(fs:4) ); fd[0,32] = trunc(fs_ceil_tmp);
} }
:ceil.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x11 & fsD { :ceil.w.D fd, fs is $(AMODE) & prime=0x11 & ft=0x0 & fct=0x0E & fmt2 & fd & fs & format=0x11 & fsD {
fs_tmp:8 = ceil(fsD); # Note that ceil returns a float the same size as its argument fs_tmp:8 = ceil(fsD); # Note that ceil returns a float the same size as its argument
Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
+6 -7
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@@ -139,8 +139,8 @@ macro setSubtractCFlags(op1,op2) {
macro setSubtractFlags(op1,op2) { macro setSubtractFlags(op1,op2) {
# op1 and op2 are assumed to be 8-bit values # op1 and op2 are assumed to be 8-bit values
# NOTE: carry flag is SET if there is NO borrow # NOTE: carry flag is SET if there is NO borrow
C = (op1 >= op2); $(C) = (op1 >= op2);
DC = ((op1<<4) < (op2<<4)); $(DC) = ((op1<<4) < (op2<<4));
} }
macro push(val) { # TODO: Uncertain about this !! macro push(val) { # TODO: Uncertain about this !!
@@ -890,17 +890,16 @@ srcFSRk: sk6"["fsrk"]" is fsrk & sk6 {
:SUBWFB srcREG, D is op6=0x3b & srcREG & D & destREG { :SUBWFB srcREG, D is op6=0x3b & srcREG & D & destREG {
val:1 = srcREG; val:1 = srcREG;
bor:1 = !$(C); bor:1 = !$(C);
setSubtractFlags(val, W); setSubtractFlags(val, W);
val = val - W; val = val - W;
tb:1 = $(C); tb:1 = $(C);
setSubtractFlags(val,bor); setSubtractFlags(val,bor);
# first subtraction could cause borrow # first subtraction could cause borrow
$(C) = $(C) & tb; # borrow if C not set $(C) = $(C) & tb; # borrow if C not set
val = val - bor; val = val - bor;
setResultFlags(val); setResultFlags(val);
destREG = val; destREG = val;
} }
Ghidra/Processors/PowerPC/data/languages/4xx.sinc
+1 -1
View File
@@ -1,7 +1,7 @@
#dcread r0,0,r0 0x7c 00 03 cc #dcread r0,0,r0 0x7c 00 03 cc
:dcread S,RA_OR_ZERO,B is OP=31 & S & B & (XOP_1_10=486 | XOP_1_10=326) & BIT_0=0 & RA_OR_ZERO :dcread S,RA_OR_ZERO,B is OP=31 & S & B & (XOP_1_10=486 | XOP_1_10=326) & BIT_0=0 & RA_OR_ZERO
{ {
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B; # ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
S = dataCacheRead(RA_OR_ZERO,B); S = dataCacheRead(RA_OR_ZERO,B);
} }
Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
-4
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@@ -834,7 +834,6 @@ define pcodeop DetermineLeftmostZeroByte;
@endif @endif
tmpX:8 = 0; tmpX:8 = 0;
tmpY:8 = 0;
<unmatched> <unmatched>
@@ -843,9 +842,6 @@ define pcodeop DetermineLeftmostZeroByte;
if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>; if ( ( ( tmpD << ( (tmpX - 1) * 8 ) ) & 0xFF00000000000000 ) != 0 ) goto <unmatched>;
# matched
tmpY = 1;
<done_searching> <done_searching>
# place byte number in register A and low 7 bits of XER # place byte number in register A and low 7 bits of XER
Ghidra/Processors/SuperH4/data/languages/SuperH4.sinc
+2 -2
View File
@@ -1623,7 +1623,7 @@ define pcodeop InvalidateCacheBlock;
:icbi N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xe3 { :icbi N_0t_at1 is OP_0=0x0 & N_0t_at1 & OP_4=0xe3 {
tmp:4 = N_0t_at1; tmp:4 = N_0t_at1;
InvalidateCacheBlock(N_0t_at1); InvalidateCacheBlock(tmp);
} }
# Unconditional Branch # Unconditional Branch
@@ -2374,7 +2374,7 @@ define pcodeop mac_wOp;
temp:4 = -M_0t; temp:4 = -M_0t;
N_0t = temp - zext($(T_FLAG)); N_0t = temp - zext($(T_FLAG));
$(T_FLAG) = ( 0 < temp ); $(T_FLAG) = ( 0 != temp );
if ( temp >= N_0t ) goto <skip>; if ( temp >= N_0t ) goto <skip>;
$(T_FLAG) = 1; $(T_FLAG) = 1;
<skip> <skip>