GP-2775: Added MIPS MT and MIPS DSP modules

Ghidra/Processors/MIPS/certification.manifest

@@ -26,6 +26,8 @@ data/languages/mips64_32_o64.cspec||GHIDRA||||END|
 data/languages/mips64be.slaspec||GHIDRA||||END|
 data/languages/mips64le.slaspec||GHIDRA||||END|
 data/languages/mips64micro.pspec||GHIDRA||||END|
+data/languages/mips_dsp.sinc||GHIDRA||||END|
+data/languages/mips_mt.sinc||GHIDRA||||END|
 data/languages/mipsfloat.sinc||GHIDRA||||END|
 data/languages/mipsmicro.sinc||GHIDRA||||END|
 data/manuals/MIPS.idx||GHIDRA||||END|

Ghidra/Processors/MIPS/data/languages/mips.ldefs

@@ -4,7 +4,7 @@
             endian="big"
             size="32"
             variant="default"
-            version="1.6"
+            version="1.7"
             slafile="mips32be.sla"
             processorspec="mips32.pspec"
             manualindexfile="../manuals/mipsM16.idx"
@@ -20,7 +20,7 @@
             endian="little"
             size="32"
             variant="default"
-            version="1.6"
+            version="1.7"
             slafile="mips32le.sla"
             processorspec="mips32.pspec"
             manualindexfile="../manuals/mipsM16.idx"
@@ -36,7 +36,7 @@
             endian="big"
             size="32"
             variant="R6"
-            version="1.6"
+            version="1.7"
             slafile="mips32R6be.sla"
             processorspec="mips32R6.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -50,7 +50,7 @@
             endian="little"
             size="32"
             variant="R6"
-            version="1.6"
+            version="1.7"
             slafile="mips32R6le.sla"
             processorspec="mips32R6.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -64,7 +64,7 @@
             endian="big"
             size="64"
             variant="default"
-            version="1.6"
+            version="1.7"
             slafile="mips64be.sla"
             processorspec="mips64.pspec"
             manualindexfile="../manuals/mipsM16.idx"
@@ -80,7 +80,7 @@
             endian="little"
             size="64"
             variant="default"
-            version="1.6"
+            version="1.7"
             slafile="mips64le.sla"
             processorspec="mips64.pspec"
             manualindexfile="../manuals/mipsM16.idx"
@@ -97,7 +97,7 @@
             endian="big"
             size="64"
             variant="micro"
-            version="1.6"
+            version="1.7"
             slafile="mips64be.sla"
             processorspec="mips64micro.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -112,7 +112,7 @@
             endian="little"
             size="64"
             variant="micro"
-            version="1.6"
+            version="1.7"
             slafile="mips64le.sla"
             processorspec="mips64micro.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -128,7 +128,7 @@
             endian="big"
             size="64"
             variant="R6"
-            version="1.6"
+            version="1.7"
             slafile="mips64be.sla"
             processorspec="mips64R6.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -143,7 +143,7 @@
             endian="little"
             size="64"
             variant="R6"
-            version="1.6"
+            version="1.7"
             slafile="mips64le.sla"
             processorspec="mips64R6.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -159,7 +159,7 @@
             endian="big"
             size="32"
             variant="64-32addr"
-            version="1.6"
+            version="1.7"
             slafile="mips64be.sla"
             processorspec="mips64.pspec"
             manualindexfile="../manuals/mipsM16.idx"
@@ -179,7 +179,7 @@
             endian="little"
             size="32"
             variant="64-32addr"
-            version="1.6"
+            version="1.7"
             slafile="mips64le.sla"
             processorspec="mips64.pspec"
             manualindexfile="../manuals/mipsM16.idx"
@@ -200,7 +200,7 @@
             endian="little"
             size="32"
             variant="64-32addr-micro"
-            version="1.6"
+            version="1.7"
             slafile="mips64le.sla"
             processorspec="mips64micro.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -220,7 +220,7 @@
             endian="big"
             size="32"
             variant="64-32addr-micro"
-            version="1.6"
+            version="1.7"
             slafile="mips64be.sla"
             processorspec="mips64micro.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -239,7 +239,7 @@
             endian="big"
             size="32"
             variant="64-32addr-R6"
-            version="1.6"
+            version="1.7"
             slafile="mips64be.sla"
             processorspec="mips64R6.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -258,7 +258,7 @@
             endian="little"
             size="32"
             variant="64-32addr-R6"
-            version="1.6"
+            version="1.7"
             slafile="mips64le.sla"
             processorspec="mips64R6.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -278,7 +278,7 @@
             endian="big"
             size="32"
             variant="micro"
-            version="1.6"
+            version="1.7"
             slafile="mips32be.sla"
             processorspec="mips32micro.pspec"
             manualindexfile="../manuals/mipsMic.idx"
@@ -293,7 +293,7 @@
             endian="little"
             size="32"
             variant="micro"
-            version="1.6"
+            version="1.7"
             slafile="mips32le.sla"
             processorspec="mips32micro.pspec"
             manualindexfile="../manuals/mipsMic.idx"

Ghidra/Processors/MIPS/data/languages/mips.sinc

@@ -142,6 +142,7 @@
 @define REGSIZE "8"     # General purpose register size (8 or 4)
 @define FREGSIZE "8"    # Floating point register size (8 or 4)
 @define ADDRSIZE "4"    # Memory address size (8 or 4, virtual and physical)
+@define DREGSIZE "16"     # 2x REGSIZE used for accumulators
 @define SIZETO4  "4"   # In 32-bit mode, no truncation needed
 @define ADDRCAST ":4"   # need to down cast to pointer size
 @define NEEDCAST "1"
@@ -151,6 +152,7 @@
 @define REGSIZE "8"     # General purpose register size (8 or 4)
 @define FREGSIZE "8"    # Floating point register size (8 or 4)
 @define ADDRSIZE "8"    # Memory address size (8 or 4, virtual and physical)
+@define DREGSIZE "16"     # 2x REGSIZE used for accumulators
 @define SIZETO4 "4"    # In 64-bit mode, use when need to do 32-bit operation
 @define ADDRCAST ""     # no need to down cast to pointer size
 
@@ -162,6 +164,8 @@
 @define REGSIZE "4"     # General purpose register size (8 or 4)
 # FREGSIZE for mips32 is set in slaspec file
 @define ADDRSIZE "4"    # Memory address size (8 or 4, virtual and physical)
+@define DOUBLE "8"     # 2x REGSIZE used for accumulators
+@define DREGSIZE "8"
 @define SIZETO4 "4"
 @define ADDRCAST ""     # no need to down cast to pointer size
 
@@ -320,7 +324,7 @@ define register offset=0x2400 size=$(REGSIZE) [
 
 # COP-0 control registers, sel=5
 define register offset=0x2500 size=$(REGSIZE) [
-    cop0_reg0.5 VPESchedule TCContext   cop0_reg3.5
+    cop0_reg0.5     VPESchedule     TCContext       cop0_reg3.5
     cop0_reg4.5     cop0_reg5.5     SRSConf4        cop0_reg7.5
     cop0_reg8.5     cop0_reg9.5     cop0_reg10.5    cop0_reg11.5
     cop0_reg12.5    cop0_reg13.5    cop0_reg14.5    cop0_reg15.5
@@ -355,8 +359,19 @@ define register offset=0x2700 size=$(REGSIZE) [
 ];
 
 # Some other internal registers
-define register offset=0x3000 size=$(REGSIZE) [ hi lo hi1 lo1 hi2 lo2 hi3 lo3 tsp ];
+define register offset=0x3000 size=$(REGSIZE) [
+@if ENDIAN == "big"
+    hi lo hi1 lo1 hi2 lo2 hi3 lo3
+@else
+    lo hi lo1 hi1 lo2 hi2 lo3 hi3
+@endif # ENDIAN
+    tsp
+];
 
+# MIPS dsp lo/hi combined registers
+define register offset=0x3000 size=$(DREGSIZE) [ ac0 ac1 ac2 ac3 ];
+
+define register offset=0x3100 size=$(REGSIZE) [ DSPControl ];
 
 define register offset=0x3200 size=$(REGSIZE) [
 	HW_CPUNUM	HW_SYNCI_STEP	HW_CC		HW_CCRe
@@ -373,6 +388,24 @@ define register offset=0x3200 size=$(REGSIZE) [
 define register offset=0x3F00 size=1 [ ISAModeSwitch ];
 @endif
 
+# Dummy registers for multi-threading
+define register offset=0x3300 size=$(REGSIZE) [
+	thread_zero	thread_at	thread_v0	thread_v1	thread_a0	thread_a1	thread_a2	thread_a3
+	thread_t0	thread_t1	thread_t2	thread_t3	thread_t4	thread_t5	thread_t6	thread_t7
+	thread_s0	thread_s1	thread_s2	thread_s3	thread_s4	thread_s5	thread_s6	thread_s7
+	thread_t8	thread_t9	thread_k0	thread_k1	thread_gp	thread_sp	thread_s8	thread_ra
+	
+	thread_f0	thread_f1	thread_f2	thread_f3	thread_f4	thread_f5	thread_f6	thread_f7
+	thread_f8	thread_f9	thread_f10	thread_f11	thread_f12	thread_f13	thread_f14	thread_f15
+	thread_f16	thread_f17	thread_f18	thread_f19	thread_f20	thread_f21	thread_f22	thread_f23
+	thread_f24	thread_f25	thread_f26	thread_f27	thread_f28	thread_f29	thread_f30	thread_f31
+	
+	thread_lo0	thread_hi0	thread_acx0	_	thread_lo1	thread_hi1	thread_acx1	_
+	thread_lo2	thread_hi2	thread_acx2	_	thread_lo3	thread_hi3	thread_acx3	_
+	
+	thread_fir	thread_fccr	thread_fexr	thread_fenr	thread_fcsr
+];
+
 # Define context bits
 define register offset=0x4000 size=4   contextreg;
 define context contextreg
@@ -455,6 +488,7 @@ define context contextreg
 define token instr(32)
     prime       = (26,31)
     bit25       = (25,25)
+    zero2425    = (24,25)
     zero2325    = (23,25)
     zero1       = (22,25)
     rs32        = (21,25)
@@ -465,24 +499,37 @@ define token instr(32)
     format      = (21,25)
     copop       = (21,25)
     mfmc0       = (21,25)
-    zero21	= (21,25)
+    zero21      = (21,25)
-    jsub	= (21,25)
+    jsub        = (21,25)
+    sa_dsp2     = (21,25)
+    shift21     = (21,25)
+    sz          = (21,25)
+    
+    acf         = (21,22)
     acflo       = (21,22)
     acfhi       = (21,22)
+    shift20     = (20,25)
     breakcode   = (6,25)
     off26       = (0,25) signed			# 26 bit signed offset, e.g. balc, bc
     ind26       = (0,25)				# 26 bit unsigned index, e.g. jal
     copfill     = (6,24)
     cofun       = (0,24)
-    off21	= (0,20) signed		# 21 bit signed offset in conditional branch/link
+    off21       = (0,20) signed		# 21 bit signed offset in conditional branch/link
-    off16	= (0,15) signed		# 16 bit signed offset in conditional branch/link
+    off16       = (0,15) signed		# 16 bit signed offset in conditional branch/link
     bit21       = (21,21)
-    bitz19	= (19,20)
+    bitz19      = (19,20)
-    pcrel	= (19,20)
+    pcrel       = (19,20)
-    pcrel2	= (18,20)
+    pcrel2      = (18,20)
     cc          = (18,20)
+    immed1625   = (16,25) signed
+    immed1623   = (16,23) signed
     rt32        = (16,20)
     rt          = (16,20)
+    rtmtdsp     = (16,20)
+    RT0thread   = (16,20)
+    RTthread    = (16,20)
+    FTthread    = (16,20)
+    FCTthread   = (16,20)
     ftD         = (16,20)
     ft          = (16,20)
     index       = (16,20)
@@ -492,14 +539,19 @@ define token instr(32)
     cond        = (16,20)
     op          = (16,20)
     zero1620    = (16,20)
+    
+    zero1619    = (16,19)
+    lohiacx     = (16,19)
     nd          = (17,17)
     tf          = (16,16)
     zero1320    = (13,20)
     zero1315    = (13,15)
     szero       = (11,25)
-    baser6	= (11,15)
+    mask        = (11,20)
+    baser6      = (11,15)
     rd32        = (11,15)
     rd          = (11,15)
+    rdmtdsp     = (11,15)
     rd0_0       = (11,15)
     rd0_1       = (11,15)
     rd0_2       = (11,15)
@@ -519,18 +571,27 @@ define token instr(32)
     cp2cprSel7	= (11,15)
     fsD         = (11,15)
     fs          = (11,15)
-    fs_unk	= (11,15)
+    RD0thread   = (11,15)
-    fs_fcr	= (11,15)
+    RDthread    = (11,15)
+    FDthread    = (11,15)
+    FCRthread   = (16,20)
+    sa_dsp      = (11,15)
+    fs_unk      = (11,15)
+    fs_fcr      = (11,15)
     zero4       = (11,15)
     msbd        = (11,15)
+    
+    lohiacx2    = (11,14)
     aclo        = (11,12)
     achi        = (11,12)
-    code        = (6,15)
+    ac          = (11,12)
+    bp          = (11,12)
     bit10       = (10,10)
-    spec2	= (9,10)
+    spec2       = (9,10)
-    spec3	= (8,10)
+    spec3       = (8,10)
-    simmed9	= (7,15)
+    simmed9     = (7,15)
     zero2       = (7,10)
+    code        = (6,15)
     fdD         = (6,10)
     fd          = (6,10)
     stype       = (6,10)
@@ -539,10 +600,11 @@ define token instr(32)
     fct2        = (6,10)
     zero5       = (6,10)
     wsbh        = (6,10)
-    bp3			= (6,8)
+    
+    bp3         = (6,8)
     sel_0608    = (6,8)
-    sa2			= (6,7)
+    sa2         = (6,7)
-    bp2			= (6,7)
+    bp2         = (6,7)
     zero6       = (3,10)
     bigfunct    = (0,10)
     fct         = (0,5)
@@ -550,15 +612,17 @@ define token instr(32)
     bit6        = (6,6)
     zero3       = (0,4)
     bit5        = (5,5)
+    h           = (4,4)
     op4         = (3,5)
+    bit3        = (3,3)
     sel         = (0,2)
     format1X    = (0,2)
-    simmed19	= (0,18) signed
+    simmed19    = (0,18) signed
-    simmed18	= (0,17) signed
+    simmed18    = (0,17) signed
     immed       = (0,15)
     simmed      = (0,15) signed
-    simmseq	= (6,15) signed
+    simmseq     = (6,15) signed
-    simmed11	= (0,10)
+    simmed11    = (0,10)
 ;
 
 attach variables [ rs rt rd base index baser6 ] [ 
@@ -714,6 +778,7 @@ attach variables [ rd0_7 ] [
 
 attach variables [ aclo acflo ] [ lo lo1 lo2 lo3 ];
 attach variables [ achi acfhi ] [ hi hi1 hi2 hi3 ];
+attach variables [ ac acf ] [ ac0 ac1 ac2 ac3 ];
 
 attach names hint [ 
     "load" "store" "hint2" "hint3" "load_streamed" "store_streamed" "load_retained" "store_retained"
@@ -721,6 +786,32 @@ attach names hint [
     "hint16" "hint17" "hint18" "hint19" "hint20" "hint21" "hint22" "hint23" "hint24"
     "writeback_invalidate" "hint26" "hint27" "hint28" "hint29" "PrepareForStore" "hint31" ];
 
+attach variables [RTthread RDthread] [
+	thread_zero	thread_at	thread_v0	thread_v1	thread_a0	thread_a1	thread_a2	thread_a3
+	thread_t0	thread_t1	thread_t2	thread_t3	thread_t4	thread_t5	thread_t6	thread_t7
+	thread_s0	thread_s1	thread_s2	thread_s3	thread_s4	thread_s5	thread_s6	thread_s7
+	thread_t8	thread_t9	thread_k0	thread_k1	thread_gp	thread_sp	thread_s8	thread_ra
+];
+
+attach variables [ FTthread FDthread ] [
+	thread_f0	thread_f1	thread_f2	thread_f3	thread_f4	thread_f5	thread_f6	thread_f7
+	thread_f8	thread_f9	thread_f10	thread_f11	thread_f12	thread_f13	thread_f14	thread_f15
+	thread_f16	thread_f17	thread_f18	thread_f19	thread_f20	thread_f21	thread_f22	thread_f23
+	thread_f24	thread_f25	thread_f26	thread_f27	thread_f28	thread_f29	thread_f30	thread_f31
+];
+
+attach variables [ rtmtdsp rdmtdsp ] [
+	thread_lo0	thread_hi0	thread_acx0	_	thread_lo1	thread_hi1	thread_acx1	_
+	thread_lo2	thread_hi2	thread_acx2	_	thread_lo3	thread_hi3	thread_acx3	_
+	_	_	_	_	_	_	_	_	_	_	_	_	_	_	_	_
+];
+
+attach variables [ FCTthread FCRthread ] [
+	thread_fir	_			_			_	_			_	_	_
+	_			_			_			_	_			_	_	_
+	_			_			_			_	_			_	_	_
+	_			thread_fccr	thread_fexr	_	thread_fenr	_	_	thread_fcsr
+];
 
 # Subconstructors
 RD0: rd0_0  is rd0_0 & sel=0  { export rd0_0; }

Ghidra/Processors/MIPS/data/languages/mips32Instructions.sinc

@@ -407,32 +407,11 @@ define pcodeop special2;
     RD = sext(*[ram]:1 INDEX_BASE);
 }
 
-:lbux RD, INDEX_BASE		is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=6 & INDEX_BASE {
-    RD = zext(*[ram]:1 INDEX_BASE);
-}
-
-@ifdef MIPS64
-:ldx RD, INDEX_BASE		is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=8 & INDEX_BASE {
-    RD = *[ram]:8 INDEX_BASE;
-}
-@endif
-
-:lhx RD, INDEX_BASE		is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=4 & INDEX_BASE {
-    RD = sext(*[ram]:2 INDEX_BASE);
-}
 
 :lhux RD, INDEX_BASE		is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=20 & INDEX_BASE {
     RD = zext(*[ram]:2 INDEX_BASE);
 }
 
-:lwx RD, INDEX_BASE		is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=0 & INDEX_BASE {
-@ifdef MIPS64
-    RD = sext(*[ram]:4 INDEX_BASE);
-@else
-    RD = *[ram]:4 INDEX_BASE;
-@endif
-}
-
 @ifdef MIPS64
 :lwux RD, INDEX_BASE		is $(AMODE) & prime=0x1F & RD & fct=10 & fct2=16 & INDEX_BASE {
     RD = zext(*[ram]:4 INDEX_BASE);
@@ -1140,7 +1119,7 @@ define pcodeop SYNC;
 @endif
 
 # 0111 00ss ssst tttt 000a a000 0000 0000
-:madd RS32src, RT32src              is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x0 & RS32src & RT32src & achi & aclo {
+:madd RS32src, RT32src              is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x0 & RS32src & RT32src & ac=0 & achi & aclo {
     tmp1:8 = sext(RS32src);
     tmp2:8 = sext(RT32src);
     prod:8 = tmp1 * tmp2;
@@ -1152,7 +1131,7 @@ define pcodeop SYNC;
 }
 
 # 0111 00ss ssst tttt 000a a000 0000 0001
-:maddu RS32src, RT32src             is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x01 & RS32src & RT32src & achi & aclo {
+:maddu RS32src, RT32src             is $(AMODE) & REL6=0 & prime=0x1C & zero1315=0x0 & fct2=0x0 & fct=0x01 & RS32src & RT32src & ac=0 & achi & aclo {
     tmp1:8 = zext(RS32src);
     tmp2:8 = zext(RT32src);
     prod:8 = tmp1 * tmp2;
@@ -1164,12 +1143,12 @@ define pcodeop SYNC;
 }
 
 # 0000 0000 0aa0 0000 dddd d000 0001 0000
-:mfhi RD                        is $(AMODE) & REL6=0 & prime=0 & fct=0x10 & RD & zero5=0 & zero1620=0 & zero2325=0 & acfhi {
+:mfhi RD                        is $(AMODE) & REL6=0 & prime=0 & fct=0x10 & RD & zero5=0 & zero1620=0 & zero2325=0 & acf=0 & acfhi {
     RD = acfhi;
 }
 
 # 0000 0000 0aa0 0000 dddd d000 0001 0010
-:mflo RD                        is $(AMODE) & REL6=0 & prime=0 & fct=0x12 & RD & zero5=0 & zero1620=0 & zero2325=0 & acflo {
+:mflo RD                        is $(AMODE) & REL6=0 & prime=0 & fct=0x12 & RD & zero5=0 & zero1620=0 & zero2325=0 & acf=0 & acflo {
     RD = acflo;
 }
 
@@ -1201,7 +1180,7 @@ define pcodeop SYNC;
 }
 
 # 0111 00ss ssst tttt 000a a000 0000 0101
-:msubu RS32src, RT32src             is $(AMODE) & REL6=0 & prime=0x1C & fct2=0 & fct=0x05 & RS32src & RT32src & zero1315=0 & aclo & achi {
+:msubu RS32src, RT32src             is $(AMODE) & REL6=0 & prime=0x1C & fct2=0 & fct=0x05 & RS32src & RT32src & zero1315=0 & ac=0 & aclo & achi {
     tmp1:8 = zext(RS32src);
     tmp2:8 = zext(RT32src);
     prod:8 = tmp1 * tmp2;
@@ -1213,12 +1192,12 @@ define pcodeop SYNC;
 }
 
 # 0000 00ss sss0 0000 000a a000 0001 0001
-:mthi RSsrc                     is $(AMODE) & REL6=0 & prime=0 & fct=0x11 & RSsrc & zero5=0 & zero1320=0 & achi {
+:mthi RSsrc                     is $(AMODE) & REL6=0 & prime=0 & fct=0x11 & RSsrc & zero5=0 & zero1320=0 & ac=0 & achi {
     achi = RSsrc;
 }
 
 # 0000 00ss sss0 0000 000a a000 0001 0011
-:mtlo RSsrc                     is $(AMODE) & REL6=0 & prime=0 & fct=0x13 & RSsrc & zero5=0 & zero1320=0 & aclo {
+:mtlo RSsrc                     is $(AMODE) & REL6=0 & prime=0 & fct=0x13 & RSsrc & zero5=0 & zero1320=0 & ac=0 & aclo {
     aclo = RSsrc;
 }
 

Ghidra/Processors/MIPS/data/languages/mips32R6be.slaspec

@@ -8,4 +8,4 @@
 @include "mips32Instructions.sinc"
 @include "mips16.sinc"
 @include "mipsmicro.sinc"
-
+@include "mips_dsp.sinc"

Ghidra/Processors/MIPS/data/languages/mips32R6le.slaspec

@@ -8,3 +8,4 @@
 @include "mips32Instructions.sinc"
 @include "mips16.sinc"
 @include "mipsmicro.sinc"
+@include "mips_dsp.sinc"

Ghidra/Processors/MIPS/data/languages/mips32be.slaspec

@@ -8,4 +8,5 @@
 @include "mips32Instructions.sinc"
 @include "mips16.sinc"
 @include "mipsmicro.sinc"
-
+@include "mips_mt.sinc"
+@include "mips_dsp.sinc"

Ghidra/Processors/MIPS/data/languages/mips32le.slaspec

@@ -8,3 +8,5 @@
 @include "mips32Instructions.sinc"
 @include "mips16.sinc"
 @include "mipsmicro.sinc"
+@include "mips_mt.sinc"
+@include "mips_dsp.sinc"

Ghidra/Processors/MIPS/data/languages/mips64be.slaspec

@@ -9,3 +9,4 @@
 @include "mips16.sinc"
 @include "mipsmicro.sinc"
 @include "mips64Instructions.sinc"
+@include "mips_dsp.sinc"

Ghidra/Processors/MIPS/data/languages/mips64le.slaspec

@@ -9,3 +9,5 @@
 @include "mips16.sinc"
 @include "mipsmicro.sinc"
 @include "mips64Instructions.sinc"
+@include "mips_dsp.sinc"
+

Ghidra/Processors/MIPS/data/languages/mips_mt.sinc

@@ -0,0 +1,152 @@
+define pcodeop fork;
+define pcodeop move_from_thread_context;
+define pcodeop move_from_thread_cp0;
+define pcodeop move_from_thread_gpr;
+define pcodeop move_from_thread_dsp;
+define pcodeop move_from_thread_fpr;
+define pcodeop move_from_thread_fpcr;
+define pcodeop move_from_thread_cop2_data;
+define pcodeop move_from_thread_cop2_control;
+define pcodeop move_to_thread_context;
+define pcodeop move_to_thread_cp0;
+define pcodeop move_to_thread_gpr;
+define pcodeop move_to_thread_dsp;
+define pcodeop move_to_thread_fpr;
+define pcodeop move_to_thread_fpcr;
+define pcodeop move_to_thread_cop2_data;
+define pcodeop move_to_thread_cop2_control;
+define pcodeop yield;
+
+# Disable multi-threaded execution. Returns VPEControl
+:dmt RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x1 & zero5=0xF & fct=0x1 & RT {
+	# Clear VPEControl IE bit (bit 15)
+	RT = VPEControl; VPEControl = VPEControl & ~0x8000; #VPEControl[15,1] = 0;
+}
+
+# Disable Virtual Processor Execution. Returns VPEControl
+:dvpe RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x0 & zero5=0x0 & fct=0x1 & RT {
+	# Clear MVPControl EVP bit (bit 0)
+	RT = MVPControl; MVPControl = MVPControl & ~0x1;
+}
+
+# Enable multi-threaded execution. Returns VPEControl
+:emt RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x1 & zero5=0xF & fct=0x21 & RT {
+	# Set VPEControl TE bit (bit 15)
+	RT = VPEControl; VPEControl = VPEControl | 0x8000; # VPEControl[15,1] = 1;
+} 
+
+# Enable Virtual Processor Execution. Returns VPEControl
+:evpe RT is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xB & rd32=0x0 & zero5=0x0 & fct=0x21 & RT {
+# Set MVPControl EVP bit (bit 0)h
+	RT = MVPControl;
+	MVPControl = MVPControl | 0x1;
+}
+
+:fork "Thread_GPR["^RDsrc^"]", RSsrc, RTsrc is $(AMODE) & REL6=0 & prime=0x1F & zero5=0x0 & fct=0x8 & RDsrc & RSsrc & RTsrc {
+	fork(RDsrc, RSsrc, RTsrc);
+}
+
+# Move From Thread Context
+# MFTR general instruction
+:mftr RD, RTsrc, bit5, sel, h is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5 & h & bit3=0 & sel & RD & RTsrc {
+	tmp:$(REGSIZE) = move_from_thread_context(RTsrc, bit5:1, sel:1, h:1);
+	RD = tmp;
+}
+
+# MFTR instructions have many idioms for sub-decodings
+# Move from coprocessor 0 register rt, sel=sel
+:mftc0 RD, "Thread_Co0["^RT0thread^"]", sel is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=0 & bit3=0 & RD & RT0thread & sel {
+	RD = move_from_thread_cp0(RT0thread:1, sel:1);
+}
+
+:mftc0 RD, "Thread_Co0["^RT0thread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=0 & bit3=0 & RD & RT0thread & sel=0 {
+	RD = move_from_thread_cp0(RT0thread:1, 0:1);
+}
+
+# Move from GPR[rt]
+:mftgpr RD, "Thread_GPR["^RTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x0 & RD & RTthread {
+	RD = move_from_thread_gpr(RTthread);
+}
+
+RtDSP: "lo"  is lohiacx=0 { }
+RtDSP: "hi"  is lohiacx=1 { }
+RtDSP: "acx" is lohiacx=2 { }
+RtDSP: "dsp" is rtmtdsp=16 { }
+
+
+:mft^RtDSP RD, rtmtdsp is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x1 & RD & RtDSP & rtmtdsp {
+	RD = move_from_thread_dsp(rtmtdsp);
+}
+
+# Move from FPR[rt]
+:mftc1 RD, "Thread_FPR["^FTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & h=0 & bit3=0 & sel=0x2 & RD & FTthread {
+	RD = move_from_thread_fpr(FTthread, 0:1);
+}
+
+:mfthc1 RD, "Thread_FPR["^FTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & h=1 & bit3=0 & sel=0x2 & RD & FTthread {
+	RD = move_from_thread_fpr(FTthread, 1:1);
+}
+
+# Move from FPCR[rt]
+:cftc1 RD, "Thread_FPCR["^FCTthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0x8 & bit5=1 & bit3=0 & sel=0x3 & RD & FCTthread {
+	RD = move_from_thread_fpcr(FCTthread);
+}
+
+# Skipping for now: MFTR for C0P2 Data and C0P2 Control (bit5=1, sel=4/5)
+
+# Move to Thread Context
+# MTTR general instruction
+:mttr RDsrc, RTsrc, bit5, sel, h is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5 & h & bit3=0 & sel & RDsrc & RTsrc {
+	move_to_thread_context(RDsrc, RTsrc, bit5:1, sel:1, h:1);
+}
+
+# MTTR instructions have many idioms for sub-decodings
+# Move rt to coprocessor 0 register rd, sel=sel
+:mttc0 RTsrc, "Thread_Co0["^RD0thread^"]", sel is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=0 & bit3=0 & RTsrc & RD0thread & sel {
+	move_to_thread_cp0(RD0thread:1, RTsrc, sel:1);
+}
+
+:mttc0 RTsrc, "Thread_Co0["^RD0thread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=0 & bit3=0 & RTsrc & RD0thread & sel=0 {
+	move_to_thread_cp0(RD0thread:1, RTsrc, 0:1);
+}
+
+# Move to GPR[rd]
+:mttgpr RTsrc, "Thread_GPR["^RDthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=1 & bit3=0 & sel=0x0 & RTsrc & RDthread {
+	move_to_thread_gpr(RDthread, RTsrc);
+}
+
+RdDSP: "lo"  is lohiacx2=0 { }
+RdDSP: "hi"  is lohiacx2=1 { }
+RdDSP: "acx" is lohiacx2=2 { }
+RdDSP: "dsp" is rdmtdsp=16 { }
+
+# Move to DSP[rd]
+:mtt^RdDSP RTsrc, rdmtdsp is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xc & bit5=1 & bit3=0 & sel=0x1 & RTsrc & RdDSP & rdmtdsp {
+	move_to_thread_dsp(rdmtdsp, RTsrc);
+}
+
+# Move to FPR[rd]
+:mttc1 RTsrc, "Thread_FPR["^FDthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & h=0 & bit3=0 & sel=0x2 & RTsrc & FDthread {
+	move_to_thread_fpr(FDthread, RTsrc, 0:1);
+}
+
+:mtthc1 RTsrc, "Thread_FPR["^FDthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & h=1 & bit3=0 & sel=0x2 & RTsrc & FDthread {
+	move_to_thread_fpr(FDthread, RTsrc, 1:1);
+}
+
+# Move to FPCR[rd]
+:cttc1 RTsrc, "Thread_FPCR["^FCRthread^"]" is $(AMODE) & REL6=0 & prime=0x10 & mfmc0=0xC & bit5=1 & bit3=0 & sel=0x3 & RTsrc & FCRthread {
+	move_to_thread_fpcr(FCRthread, RTsrc);
+}
+
+# Skipping for now: MTTR for C0P2 Data and C0P2 control (bit5=1, sel=4/5)
+
+# Conditionally Deschedule or Deallocate the Current Thread
+:yield RD, RSsrc is $(AMODE) & REL6=0 & prime=0x1F & op=0 & zero5=0x0 & fct=0x9 & RD & RSsrc {
+	yield(RSsrc);
+	RD = RSsrc & YQMask;
+}
+
+:yield RSsrc is $(AMODE) & REL6=0 & prime=0x1F & op=0 & zero5=0x0 & fct=0x9 & rd=0 & RSsrc {
+	yield(RSsrc);
+}