diff --git a/Ghidra/Features/Base/data/typeinfo/generic/generic_clib.gdt b/Ghidra/Features/Base/data/typeinfo/generic/generic_clib.gdt index cd95c3cdf4..7c14bee456 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/generic/generic_clib.gdt and b/Ghidra/Features/Base/data/typeinfo/generic/generic_clib.gdt differ diff --git a/Ghidra/Features/Base/data/typeinfo/generic/generic_clib_64.gdt b/Ghidra/Features/Base/data/typeinfo/generic/generic_clib_64.gdt index 0d330c818b..1ff3dc9f36 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/generic/generic_clib_64.gdt and b/Ghidra/Features/Base/data/typeinfo/generic/generic_clib_64.gdt differ diff --git a/Ghidra/Features/Base/data/typeinfo/golang/golang_1.21_anybit_any.gdt b/Ghidra/Features/Base/data/typeinfo/golang/golang_1.21_anybit_any.gdt index 55ae6c9ca6..363b41847b 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/golang/golang_1.21_anybit_any.gdt and b/Ghidra/Features/Base/data/typeinfo/golang/golang_1.21_anybit_any.gdt differ diff --git a/Ghidra/Features/Base/data/typeinfo/golang/golang_1.22_anybit_any.gdt b/Ghidra/Features/Base/data/typeinfo/golang/golang_1.22_anybit_any.gdt index b4a63fd290..1317e6a17c 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/golang/golang_1.22_anybit_any.gdt and b/Ghidra/Features/Base/data/typeinfo/golang/golang_1.22_anybit_any.gdt differ diff --git a/Ghidra/Features/Base/data/typeinfo/rust/rust-common.gdt b/Ghidra/Features/Base/data/typeinfo/rust/rust-common.gdt index 1ebeeff1b7..d02355fae0 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/rust/rust-common.gdt and b/Ghidra/Features/Base/data/typeinfo/rust/rust-common.gdt differ diff --git a/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_32.gdt b/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_32.gdt index 00eef9871a..2c6620350f 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_32.gdt and b/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_32.gdt differ diff --git a/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_64.gdt b/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_64.gdt index 64e07cd901..8686366157 100644 Binary files a/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_64.gdt and b/Ghidra/Features/Base/data/typeinfo/win32/windows_vs12_64.gdt differ diff --git a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/golang/rtti/GoRttiMapper.java b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/golang/rtti/GoRttiMapper.java index f006453c9f..5c465aa99c 100644 --- a/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/golang/rtti/GoRttiMapper.java +++ b/Ghidra/Features/Base/src/main/java/ghidra/app/util/bin/format/golang/rtti/GoRttiMapper.java @@ -22,8 +22,6 @@ import java.io.IOException; import java.util.*; import java.util.Map.Entry; -import javax.help.UnsupportedOperationException; - import generic.jar.ResourceFile; import ghidra.app.plugin.core.analysis.AutoAnalysisManager; import ghidra.app.plugin.core.analysis.TransientProgramProperties; @@ -37,13 +35,13 @@ import ghidra.app.util.bin.format.golang.structmapping.*; import ghidra.app.util.importer.MessageLog; import ghidra.app.util.opinion.*; import ghidra.framework.Platform; -import ghidra.framework.store.LockException; import ghidra.program.model.address.*; import ghidra.program.model.data.*; import ghidra.program.model.data.DataTypeConflictHandler.ConflictResult; -import ghidra.program.model.data.StandAloneDataTypeManager.LanguageUpdateOption; -import ghidra.program.model.lang.*; -import ghidra.program.model.listing.*; +import ghidra.program.model.lang.Endian; +import ghidra.program.model.lang.LanguageID; +import ghidra.program.model.listing.Function; +import ghidra.program.model.listing.Program; import ghidra.program.model.mem.MemoryBlock; import ghidra.program.model.symbol.Symbol; import ghidra.program.model.symbol.SymbolType; @@ -843,8 +841,7 @@ public class GoRttiMapper extends DataTypeMapper implements DataTypeMapperContex // to avoid traces of the original program name as a deleted source archive link in the // gdt data base. This method only leaves the target gdt filename + ".step1" in the db. File tmpGDTFile = new File(gdtFile.getParentFile(), gdtFile.getName() + ".step1.gdt"); - FileDataTypeManager tmpFdtm = createFileArchive(tmpGDTFile, program.getLanguage(), - program.getCompilerSpec().getCompilerSpecID(), monitor); + FileDataTypeManager tmpFdtm = FileDataTypeManager.createFileArchive(tmpGDTFile); int tx = -1; try { tx = tmpFdtm.startTransaction("Import"); @@ -889,8 +886,7 @@ public class GoRttiMapper extends DataTypeMapper implements DataTypeMapperContex tmpFdtm.save(); - FileDataTypeManager fdtm = createFileArchive(gdtFile, program.getLanguage(), - program.getCompilerSpec().getCompilerSpecID(), monitor); + FileDataTypeManager fdtm = FileDataTypeManager.createFileArchive(gdtFile); tx = -1; try { tx = fdtm.startTransaction("Import"); @@ -915,19 +911,6 @@ public class GoRttiMapper extends DataTypeMapper implements DataTypeMapperContex tmpGDTFile.delete(); } - private FileDataTypeManager createFileArchive(File gdtFile, Language lang, - CompilerSpecID compilerId, TaskMonitor monitor) throws IOException { - try { - FileDataTypeManager fdtm = FileDataTypeManager.createFileArchive(gdtFile); - fdtm.setProgramArchitecture(lang, compilerId, LanguageUpdateOption.CLEAR, monitor); - return fdtm; - } - catch (IOException | CancelledException | LockException | UnsupportedOperationException - | IncompatibleLanguageException e) { - throw new IOException("Failed to create file data type manager: " + gdtFile, e); - } - } - private DataType structMappingInfoToDataType(StructureMappingInfo smi) { if (smi.getStructureDataType() == null) { return null; diff --git a/Ghidra/Features/Base/src/test.slow/java/ghidra/app/plugin/core/datamgr/DataTypeArchiveIDTest.java b/Ghidra/Features/Base/src/test.slow/java/ghidra/app/plugin/core/datamgr/DataTypeArchiveIDTest.java index 2406b9079d..4cbcc7b02b 100644 --- a/Ghidra/Features/Base/src/test.slow/java/ghidra/app/plugin/core/datamgr/DataTypeArchiveIDTest.java +++ b/Ghidra/Features/Base/src/test.slow/java/ghidra/app/plugin/core/datamgr/DataTypeArchiveIDTest.java @@ -67,7 +67,7 @@ public class DataTypeArchiveIDTest extends AbstractGenericTest { FileDataTypeManager dtm = null; try { dtm = FileDataTypeManager.openFileArchive(gdtFile, false); - assertEquals(ArchiveWarning.NONE, dtm.getWarning()); + assertEquals(dtm.getWarningMessage(true), ArchiveWarning.NONE, dtm.getWarning()); return dtm.getUniversalID().toString(); } catch (IOException e) { diff --git a/Ghidra/Processors/x86/data/languages/avx512.sinc b/Ghidra/Processors/x86/data/languages/avx512.sinc index a595ea668d..0791af6105 100644 --- a/Ghidra/Processors/x86/data/languages/avx512.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512.sinc @@ -4,7 +4,7 @@ # ADDPD 3-33 PAGE 603 LINE 33411 define pcodeop vaddpd_avx512vl ; -:VADDPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VADDPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vaddpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -12,7 +12,7 @@ define pcodeop vaddpd_avx512vl ; } # ADDPD 3-33 PAGE 603 LINE 33414 -:VADDPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VADDPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vaddpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -21,7 +21,7 @@ define pcodeop vaddpd_avx512vl ; # ADDPD 3-33 PAGE 603 LINE 33417 define pcodeop vaddpd_avx512f ; -:VADDPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x58; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VADDPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x58; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vaddpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -29,7 +29,7 @@ define pcodeop vaddpd_avx512f ; # ADDPS 3-36 PAGE 606 LINE 33562 define pcodeop vaddps_avx512vl ; -:VADDPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VADDPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vaddps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -37,7 +37,7 @@ define pcodeop vaddps_avx512vl ; } # ADDPS 3-36 PAGE 606 LINE 33565 -:VADDPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VADDPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x58; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vaddps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -46,7 +46,7 @@ define pcodeop vaddps_avx512vl ; # ADDPS 3-36 PAGE 606 LINE 33568 define pcodeop vaddps_avx512f ; -:VADDPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x58; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VADDPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x58; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vaddps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -54,7 +54,7 @@ define pcodeop vaddps_avx512f ; # ADDSD 3-39 PAGE 609 LINE 33721 define pcodeop vaddsd_avx512f ; -:VADDSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VADDSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vaddsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -63,7 +63,7 @@ define pcodeop vaddsd_avx512f ; # ADDSS 3-41 PAGE 611 LINE 33815 define pcodeop vaddss_avx512f ; -:VADDSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VADDSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vaddss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -72,7 +72,7 @@ define pcodeop vaddss_avx512f ; # ANDPD 3-64 PAGE 634 LINE 34827 define pcodeop vandpd_avx512vl ; -:VANDPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VANDPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vandpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -80,7 +80,7 @@ define pcodeop vandpd_avx512vl ; } # ANDPD 3-64 PAGE 634 LINE 34830 -:VANDPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VANDPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vandpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -89,7 +89,7 @@ define pcodeop vandpd_avx512vl ; # ANDPD 3-64 PAGE 634 LINE 34833 define pcodeop vandpd_avx512dq ; -:VANDPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VANDPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vandpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -97,7 +97,7 @@ define pcodeop vandpd_avx512dq ; # ANDPS 3-67 PAGE 637 LINE 34953 define pcodeop vandps_avx512vl ; -:VANDPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VANDPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vandps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -105,7 +105,7 @@ define pcodeop vandps_avx512vl ; } # ANDPS 3-67 PAGE 637 LINE 34956 -:VANDPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VANDPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vandps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -114,7 +114,7 @@ define pcodeop vandps_avx512vl ; # ANDPS 3-67 PAGE 637 LINE 34959 define pcodeop vandps_avx512dq ; -:VANDPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VANDPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vandps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -122,7 +122,7 @@ define pcodeop vandps_avx512dq ; # ANDNPD 3-70 PAGE 640 LINE 35087 define pcodeop vandnpd_avx512vl ; -:VANDNPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VANDNPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vandnpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -130,7 +130,7 @@ define pcodeop vandnpd_avx512vl ; } # ANDNPD 3-70 PAGE 640 LINE 35090 -:VANDNPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VANDNPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vandnpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -139,7 +139,7 @@ define pcodeop vandnpd_avx512vl ; # ANDNPD 3-70 PAGE 640 LINE 35093 define pcodeop vandnpd_avx512dq ; -:VANDNPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VANDNPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vandnpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -147,7 +147,7 @@ define pcodeop vandnpd_avx512dq ; # ANDNPS 3-73 PAGE 643 LINE 35213 define pcodeop vandnps_avx512vl ; -:VANDNPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VANDNPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vandnps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -155,7 +155,7 @@ define pcodeop vandnps_avx512vl ; } # ANDNPS 3-73 PAGE 643 LINE 35216 -:VANDNPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VANDNPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x55; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vandnps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -164,7 +164,7 @@ define pcodeop vandnps_avx512vl ; # ANDNPS 3-73 PAGE 643 LINE 35219 define pcodeop vandnps_avx512dq ; -:VANDNPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VANDNPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x55; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vandnps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -172,14 +172,14 @@ define pcodeop vandnps_avx512dq ; # CMPPD 3-155 PAGE 725 LINE 39246 define pcodeop vcmppd_avx512vl ; -:^VCMPPD_mon KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m64bcst; VCMPPD_mon & VCMPPD_op +:^VCMPPD_mon KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m64bcst; VCMPPD_mon & VCMPPD_op [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vcmppd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, VCMPPD_op ); } # CMPPD 3-155 PAGE 725 LINE 39250 -:^VCMPPD_mon KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m64bcst; VCMPPD_mon & VCMPPD_op +:^VCMPPD_mon KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m64bcst; VCMPPD_mon & VCMPPD_op [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vcmppd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, VCMPPD_op ); @@ -187,7 +187,7 @@ define pcodeop vcmppd_avx512vl ; # CMPPD 3-155 PAGE 725 LINE 39254 define pcodeop vcmppd_avx512f ; -:^VCMPPD_mon KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m64bcst; VCMPPD_mon & VCMPPD_op +:^VCMPPD_mon KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst^VCMPPD_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m64bcst; VCMPPD_mon & VCMPPD_op [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vcmppd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, VCMPPD_op ); @@ -195,14 +195,14 @@ define pcodeop vcmppd_avx512f ; # CMPPS 3-162 PAGE 732 LINE 39613 define pcodeop vcmpps_avx512vl ; -:^VCMPPS_mon KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m32bcst; VCMPPS_mon & VCMPPS_op +:^VCMPPS_mon KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m128_m32bcst; VCMPPS_mon & VCMPPS_op [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vcmpps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, VCMPPS_op ); } # CMPPS 3-162 PAGE 732 LINE 39617 -:^VCMPPS_mon KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m32bcst; VCMPPS_mon & VCMPPS_op +:^VCMPPS_mon KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xC2; KReg_reg ... & YmmReg2_m256_m32bcst; VCMPPS_mon & VCMPPS_op [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vcmpps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, VCMPPS_op ); @@ -210,7 +210,7 @@ define pcodeop vcmpps_avx512vl ; # CMPPS 3-162 PAGE 732 LINE 39621 define pcodeop vcmpps_avx512f ; -:^VCMPPS_mon KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m32bcst; VCMPPS_mon & VCMPPS_op +:^VCMPPS_mon KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst^VCMPPS_op is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xC2; KReg_reg ... & ZmmReg2_m512_m32bcst; VCMPPS_mon & VCMPPS_op [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vcmpps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, VCMPPS_op ); @@ -218,7 +218,7 @@ define pcodeop vcmpps_avx512f ; # CMPSD 3-173 PAGE 743 LINE 40157 define pcodeop vcmpsd_avx512f ; -:^VCMPSD_mon KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m64^VCMPSD_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op +:^VCMPSD_mon KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64^VCMPSD_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m64; VCMPSD_mon & VCMPSD_op [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { KReg_reg = vcmpsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64, VCMPSD_op ); @@ -226,7 +226,7 @@ define pcodeop vcmpsd_avx512f ; # CMPSS 3-177 PAGE 747 LINE 40393 define pcodeop vcmpss_avx512f ; -:^VCMPSS_mon KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m32^VCMPSS_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op +:^VCMPSS_mon KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32^VCMPSS_op is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xC2; KReg_reg ... & XmmReg2_m32; VCMPSS_mon & VCMPSS_op [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { KReg_reg = vcmpss_avx512f( vexVVVV_XmmReg, XmmReg2_m32, VCMPSS_op ); @@ -252,7 +252,7 @@ define pcodeop vcomiss_avx512f ; # CVTDQ2PD 3-228 PAGE 798 LINE 43080 define pcodeop vcvtdq2pd_avx512vl ; -:VCVTDQ2PD XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTDQ2PD XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -260,7 +260,7 @@ define pcodeop vcvtdq2pd_avx512vl ; } # CVTDQ2PD 3-228 PAGE 798 LINE 43083 -:VCVTDQ2PD YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTDQ2PD YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvtdq2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -269,7 +269,7 @@ define pcodeop vcvtdq2pd_avx512vl ; # CVTDQ2PD 3-228 PAGE 798 LINE 43086 define pcodeop vcvtdq2pd_avx512f ; -:VCVTDQ2PD ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0xE6; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTDQ2PD ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0xE6; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvtdq2pd_avx512f( YmmReg2_m256_m32bcst ); @@ -277,7 +277,7 @@ define pcodeop vcvtdq2pd_avx512f ; # CVTDQ2PS 3-232 PAGE 802 LINE 43248 define pcodeop vcvtdq2ps_avx512vl ; -:VCVTDQ2PS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTDQ2PS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtdq2ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -285,7 +285,7 @@ define pcodeop vcvtdq2ps_avx512vl ; } # CVTDQ2PS 3-232 PAGE 802 LINE 43251 -:VCVTDQ2PS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VCVTDQ2PS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtdq2ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -294,7 +294,7 @@ define pcodeop vcvtdq2ps_avx512vl ; # CVTDQ2PS 3-232 PAGE 802 LINE 43254 define pcodeop vcvtdq2ps_avx512f ; -:VCVTDQ2PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VCVTDQ2PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtdq2ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -302,7 +302,7 @@ define pcodeop vcvtdq2ps_avx512f ; # CVTPD2DQ 3-235 PAGE 805 LINE 43414 define pcodeop vcvtpd2dq_avx512vl ; -:VCVTPD2DQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTPD2DQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2dq_avx512vl( XmmReg2_m128_m64bcst ); @@ -310,7 +310,7 @@ define pcodeop vcvtpd2dq_avx512vl ; } # CVTPD2DQ 3-235 PAGE 805 LINE 43417 -:VCVTPD2DQ XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTPD2DQ XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2dq_avx512vl( YmmReg2_m256_m64bcst ); @@ -319,7 +319,7 @@ define pcodeop vcvtpd2dq_avx512vl ; # CVTPD2DQ 3-235 PAGE 805 LINE 43420 define pcodeop vcvtpd2dq_avx512f ; -:VCVTPD2DQ YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTPD2DQ YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtpd2dq_avx512f( ZmmReg2_m512_m64bcst ); @@ -328,7 +328,7 @@ define pcodeop vcvtpd2dq_avx512f ; # CVTPD2PS 3-240 PAGE 810 LINE 43649 define pcodeop vcvtpd2ps_avx512vl ; -:VCVTPD2PS XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTPD2PS XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2ps_avx512vl( XmmReg2_m128_m64bcst ); @@ -336,7 +336,7 @@ define pcodeop vcvtpd2ps_avx512vl ; } # CVTPD2PS 3-240 PAGE 810 LINE 43653 -:VCVTPD2PS XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTPD2PS XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2ps_avx512vl( YmmReg2_m256_m64bcst ); @@ -345,7 +345,7 @@ define pcodeop vcvtpd2ps_avx512vl ; # CVTPD2PS 3-240 PAGE 810 LINE 43657 define pcodeop vcvtpd2ps_avx512f ; -:VCVTPD2PS YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTPD2PS YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtpd2ps_avx512f( ZmmReg2_m512_m64bcst ); @@ -354,7 +354,7 @@ define pcodeop vcvtpd2ps_avx512f ; # CVTPS2DQ 3-246 PAGE 816 LINE 43933 define pcodeop vcvtps2dq_avx512vl ; -:VCVTPS2DQ XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTPS2DQ XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtps2dq_avx512vl( XmmReg2_m128_m32bcst ); @@ -362,7 +362,7 @@ define pcodeop vcvtps2dq_avx512vl ; } # CVTPS2DQ 3-246 PAGE 816 LINE 43936 -:VCVTPS2DQ YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VCVTPS2DQ YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtps2dq_avx512vl( YmmReg2_m256_m32bcst ); @@ -371,7 +371,7 @@ define pcodeop vcvtps2dq_avx512vl ; # CVTPS2DQ 3-246 PAGE 816 LINE 43939 define pcodeop vcvtps2dq_avx512f ; -:VCVTPS2DQ ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VCVTPS2DQ ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtps2dq_avx512f( ZmmReg2_m512_m32bcst ); @@ -379,7 +379,7 @@ define pcodeop vcvtps2dq_avx512f ; # CVTPS2PD 3-249 PAGE 819 LINE 44104 define pcodeop vcvtps2pd_avx512vl ; -:VCVTPS2PD XmmReg1 KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst +:VCVTPS2PD XmmReg1^KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvtps2pd_avx512vl( XmmReg2_m64_m32bcst ); @@ -387,7 +387,7 @@ define pcodeop vcvtps2pd_avx512vl ; } # CVTPS2PD 3-249 PAGE 819 LINE 44107 -:VCVTPS2PD YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTPS2PD YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvtps2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -396,7 +396,7 @@ define pcodeop vcvtps2pd_avx512vl ; # CVTPS2PD 3-249 PAGE 819 LINE 44110 define pcodeop vcvtps2pd_avx512f ; -:VCVTPS2PD ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5A; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTPS2PD ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5A; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvtps2pd_avx512f( YmmReg2_m256_m32bcst ); @@ -422,7 +422,7 @@ define pcodeop vcvtsd2si_avx512f ; # CVTSD2SS 3-255 PAGE 825 LINE 44417 define pcodeop vcvtsd2ss_avx512f ; -:VCVTSD2SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VCVTSD2SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vcvtsd2ss_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -469,7 +469,7 @@ define pcodeop vcvtsi2ss_avx512f ; # CVTSS2SD 3-261 PAGE 831 LINE 44747 define pcodeop vcvtss2sd_avx512f ; -:VCVTSS2SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VCVTSS2SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vcvtss2sd_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -496,7 +496,7 @@ define pcodeop vcvtss2si_avx512f ; # CVTTPD2DQ 3-265 PAGE 835 LINE 44936 define pcodeop vcvttpd2dq_avx512vl ; -:VCVTTPD2DQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTTPD2DQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttpd2dq_avx512vl( XmmReg2_m128_m64bcst ); @@ -504,7 +504,7 @@ define pcodeop vcvttpd2dq_avx512vl ; } # CVTTPD2DQ 3-265 PAGE 835 LINE 44940 -:VCVTTPD2DQ XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTTPD2DQ XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttpd2dq_avx512vl( YmmReg2_m256_m64bcst ); @@ -513,7 +513,7 @@ define pcodeop vcvttpd2dq_avx512vl ; # CVTTPD2DQ 3-265 PAGE 835 LINE 44944 define pcodeop vcvttpd2dq_avx512f ; -:VCVTTPD2DQ YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTTPD2DQ YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvttpd2dq_avx512f( ZmmReg2_m512_m64bcst ); @@ -522,7 +522,7 @@ define pcodeop vcvttpd2dq_avx512f ; # CVTTPS2DQ 3-270 PAGE 840 LINE 45169 define pcodeop vcvttps2dq_avx512vl ; -:VCVTTPS2DQ XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTTPS2DQ XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttps2dq_avx512vl( XmmReg2_m128_m32bcst ); @@ -530,7 +530,7 @@ define pcodeop vcvttps2dq_avx512vl ; } # CVTTPS2DQ 3-270 PAGE 840 LINE 45173 -:VCVTTPS2DQ YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VCVTTPS2DQ YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvttps2dq_avx512vl( YmmReg2_m256_m32bcst ); @@ -539,7 +539,7 @@ define pcodeop vcvttps2dq_avx512vl ; # CVTTPS2DQ 3-270 PAGE 840 LINE 45177 define pcodeop vcvttps2dq_avx512f ; -:VCVTTPS2DQ ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VCVTTPS2DQ ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvttps2dq_avx512f( ZmmReg2_m512_m32bcst ); @@ -583,7 +583,7 @@ define pcodeop vcvttss2si_avx512f ; # DIVPD 3-288 PAGE 858 LINE 46029 define pcodeop vdivpd_avx512vl ; -:VDIVPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VDIVPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vdivpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -591,7 +591,7 @@ define pcodeop vdivpd_avx512vl ; } # DIVPD 3-288 PAGE 858 LINE 46033 -:VDIVPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VDIVPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vdivpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -600,7 +600,7 @@ define pcodeop vdivpd_avx512vl ; # DIVPD 3-288 PAGE 858 LINE 46037 define pcodeop vdivpd_avx512f ; -:VDIVPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5E; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VDIVPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5E; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vdivpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -608,7 +608,7 @@ define pcodeop vdivpd_avx512f ; # DIVPS 3-291 PAGE 861 LINE 46170 define pcodeop vdivps_avx512vl ; -:VDIVPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VDIVPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vdivps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -616,7 +616,7 @@ define pcodeop vdivps_avx512vl ; } # DIVPS 3-291 PAGE 861 LINE 46174 -:VDIVPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VDIVPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vdivps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -625,7 +625,7 @@ define pcodeop vdivps_avx512vl ; # DIVPS 3-291 PAGE 861 LINE 46178 define pcodeop vdivps_avx512f ; -:VDIVPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5E; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VDIVPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5E; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vdivps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -633,7 +633,7 @@ define pcodeop vdivps_avx512f ; # DIVSD 3-294 PAGE 864 LINE 46315 define pcodeop vdivsd_avx512f ; -:VDIVSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VDIVSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vdivsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -642,7 +642,7 @@ define pcodeop vdivsd_avx512f ; # DIVSS 3-296 PAGE 866 LINE 46413 define pcodeop vdivss_avx512f ; -:VDIVSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VDIVSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vdivss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -1007,7 +1007,7 @@ define pcodeop kxord_avx512bw ; # MAXPD 4-12 PAGE 1132 LINE 59206 define pcodeop vmaxpd_avx512vl ; -:VMAXPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VMAXPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vmaxpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -1015,7 +1015,7 @@ define pcodeop vmaxpd_avx512vl ; } # MAXPD 4-12 PAGE 1132 LINE 59210 -:VMAXPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VMAXPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vmaxpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -1024,7 +1024,7 @@ define pcodeop vmaxpd_avx512vl ; # MAXPD 4-12 PAGE 1132 LINE 59214 define pcodeop vmaxpd_avx512f ; -:VMAXPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5F; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VMAXPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5F; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vmaxpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -1032,7 +1032,7 @@ define pcodeop vmaxpd_avx512f ; # MAXPS 4-15 PAGE 1135 LINE 59356 define pcodeop vmaxps_avx512vl ; -:VMAXPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VMAXPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vmaxps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -1040,7 +1040,7 @@ define pcodeop vmaxps_avx512vl ; } # MAXPS 4-15 PAGE 1135 LINE 59359 -:VMAXPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VMAXPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vmaxps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -1049,7 +1049,7 @@ define pcodeop vmaxps_avx512vl ; # MAXPS 4-15 PAGE 1135 LINE 59362 define pcodeop vmaxps_avx512f ; -:VMAXPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5F; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VMAXPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5F; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vmaxps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -1057,7 +1057,7 @@ define pcodeop vmaxps_avx512f ; # MAXSD 4-18 PAGE 1138 LINE 59506 define pcodeop vmaxsd_avx512f ; -:VMAXSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VMAXSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vmaxsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -1066,7 +1066,7 @@ define pcodeop vmaxsd_avx512f ; # MAXSS 4-20 PAGE 1140 LINE 59609 define pcodeop vmaxss_avx512f ; -:VMAXSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VMAXSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vmaxss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -1075,7 +1075,7 @@ define pcodeop vmaxss_avx512f ; # MINPD 4-23 PAGE 1143 LINE 59771 define pcodeop vminpd_avx512vl ; -:VMINPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VMINPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vminpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -1083,7 +1083,7 @@ define pcodeop vminpd_avx512vl ; } # MINPD 4-23 PAGE 1143 LINE 59774 -:VMINPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VMINPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vminpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -1092,7 +1092,7 @@ define pcodeop vminpd_avx512vl ; # MINPD 4-23 PAGE 1143 LINE 59777 define pcodeop vminpd_avx512f ; -:VMINPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5D; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VMINPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5D; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vminpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -1100,7 +1100,7 @@ define pcodeop vminpd_avx512f ; # MINPS 4-26 PAGE 1146 LINE 59915 define pcodeop vminps_avx512vl ; -:VMINPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VMINPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vminps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -1108,7 +1108,7 @@ define pcodeop vminps_avx512vl ; } # MINPS 4-26 PAGE 1146 LINE 59918 -:VMINPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VMINPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vminps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -1117,7 +1117,7 @@ define pcodeop vminps_avx512vl ; # MINPS 4-26 PAGE 1146 LINE 59921 define pcodeop vminps_avx512f ; -:VMINPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5D; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VMINPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5D; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vminps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -1125,7 +1125,7 @@ define pcodeop vminps_avx512f ; # MINSD 4-29 PAGE 1149 LINE 60063 define pcodeop vminsd_avx512f ; -:VMINSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VMINSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vminsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -1134,7 +1134,7 @@ define pcodeop vminsd_avx512f ; # MINSS 4-31 PAGE 1151 LINE 60166 define pcodeop vminss_avx512f ; -:VMINSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VMINSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vminss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -1143,7 +1143,7 @@ define pcodeop vminss_avx512f ; # MOVAPD 4-45 PAGE 1165 LINE 60852 define pcodeop vmovapd_avx512vl ; -:VMOVAPD XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVAPD XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovapd_avx512vl( XmmReg2_m128 ); @@ -1151,7 +1151,7 @@ define pcodeop vmovapd_avx512vl ; } # MOVAPD 4-45 PAGE 1165 LINE 60855 -:VMOVAPD YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVAPD YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovapd_avx512vl( YmmReg2_m256 ); @@ -1160,28 +1160,28 @@ define pcodeop vmovapd_avx512vl ; # MOVAPD 4-45 PAGE 1165 LINE 60858 define pcodeop vmovapd_avx512f ; -:VMOVAPD ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x28; ZmmReg1 ... & ZmmReg2_m512 +:VMOVAPD ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x28; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovapd_avx512f( ZmmReg2_m512 ); } # MOVAPD 4-45 PAGE 1165 LINE 60861 -:VMOVAPD XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x29; XmmReg1 ... & XmmReg2_m128 +:VMOVAPD XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x29; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovapd_avx512vl( XmmReg1 ); } # MOVAPD 4-45 PAGE 1165 LINE 60864 -:VMOVAPD YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x29; YmmReg1 ... & YmmReg2_m256 +:VMOVAPD YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x29; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovapd_avx512vl( YmmReg1 ); } # MOVAPD 4-45 PAGE 1165 LINE 60867 -:VMOVAPD ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x29; ZmmReg1 ... & ZmmReg2_m512 +:VMOVAPD ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x29; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovapd_avx512f( ZmmReg1 ); @@ -1189,7 +1189,7 @@ define pcodeop vmovapd_avx512f ; # MOVAPS 4-49 PAGE 1169 LINE 61047 define pcodeop vmovaps_avx512vl ; -:VMOVAPS XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVAPS XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovaps_avx512vl( XmmReg2_m128 ); @@ -1197,7 +1197,7 @@ define pcodeop vmovaps_avx512vl ; } # MOVAPS 4-49 PAGE 1169 LINE 61050 -:VMOVAPS YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVAPS YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovaps_avx512vl( YmmReg2_m256 ); @@ -1206,28 +1206,28 @@ define pcodeop vmovaps_avx512vl ; # MOVAPS 4-49 PAGE 1169 LINE 61053 define pcodeop vmovaps_avx512f ; -:VMOVAPS ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x28; ZmmReg1 ... & ZmmReg2_m512 +:VMOVAPS ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x28; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovaps_avx512f( ZmmReg2_m512 ); } # MOVAPS 4-49 PAGE 1169 LINE 61056 -:VMOVAPS XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x29; XmmReg1 ... & XmmReg2_m128 +:VMOVAPS XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x29; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovaps_avx512vl( XmmReg1 ); } # MOVAPS 4-49 PAGE 1169 LINE 61059 -:VMOVAPS YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x29; YmmReg1 ... & YmmReg2_m256 +:VMOVAPS YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x29; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovaps_avx512vl( YmmReg1 ); } # MOVAPS 4-49 PAGE 1169 LINE 61062 -:VMOVAPS ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x29; ZmmReg1 ... & ZmmReg2_m512 +:VMOVAPS ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x29; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovaps_avx512f( ZmmReg1 ); @@ -1271,7 +1271,7 @@ define pcodeop vmovq_avx512f ; # MOVDDUP 4-59 PAGE 1179 LINE 61526 define pcodeop vmovddup_avx512vl ; -:VMOVDDUP XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VMOVDDUP XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM) { local tmp:16 = vmovddup_avx512vl( XmmReg2_m64 ); @@ -1279,7 +1279,7 @@ define pcodeop vmovddup_avx512vl ; } # MOVDDUP 4-59 PAGE 1179 LINE 61529 -:VMOVDDUP YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDDUP YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM) { local tmp:32 = vmovddup_avx512vl( YmmReg2_m256 ); @@ -1288,7 +1288,7 @@ define pcodeop vmovddup_avx512vl ; # MOVDDUP 4-59 PAGE 1179 LINE 61532 define pcodeop vmovddup_avx512f ; -:VMOVDDUP ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x12; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDDUP ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x12; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 13; ] # (TupleType DUP-RM) { ZmmReg1 = vmovddup_avx512f( ZmmReg2_m512 ); @@ -1296,7 +1296,7 @@ define pcodeop vmovddup_avx512f ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61675 define pcodeop vmovdqa32_avx512vl ; -:VMOVDQA32 XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVDQA32 XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovdqa32_avx512vl( XmmReg2_m128 ); @@ -1304,7 +1304,7 @@ define pcodeop vmovdqa32_avx512vl ; } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61678 -:VMOVDQA32 YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDQA32 YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovdqa32_avx512vl( YmmReg2_m256 ); @@ -1313,28 +1313,28 @@ define pcodeop vmovdqa32_avx512vl ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61681 define pcodeop vmovdqa32_avx512f ; -:VMOVDQA32 ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQA32 ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovdqa32_avx512f( ZmmReg2_m512 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61684 -:VMOVDQA32 XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 +:VMOVDQA32 XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqa32_avx512vl( XmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61687 -:VMOVDQA32 YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 +:VMOVDQA32 YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqa32_avx512vl( YmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61690 -:VMOVDQA32 ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQA32 ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqa32_avx512f( ZmmReg1 ); @@ -1342,7 +1342,7 @@ define pcodeop vmovdqa32_avx512f ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61693 define pcodeop vmovdqa64_avx512vl ; -:VMOVDQA64 XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVDQA64 XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovdqa64_avx512vl( XmmReg2_m128 ); @@ -1350,7 +1350,7 @@ define pcodeop vmovdqa64_avx512vl ; } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61696 -:VMOVDQA64 YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDQA64 YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovdqa64_avx512vl( YmmReg2_m256 ); @@ -1359,28 +1359,28 @@ define pcodeop vmovdqa64_avx512vl ; # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61699 define pcodeop vmovdqa64_avx512f ; -:VMOVDQA64 ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQA64 ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovdqa64_avx512f( ZmmReg2_m512 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61702 -:VMOVDQA64 XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 +:VMOVDQA64 XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqa64_avx512vl( XmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61705 -:VMOVDQA64 YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 +:VMOVDQA64 YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqa64_avx512vl( YmmReg1 ); } # MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61708 -:VMOVDQA64 ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQA64 ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqa64_avx512f( ZmmReg1 ); @@ -1388,7 +1388,7 @@ define pcodeop vmovdqa64_avx512f ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61938 define pcodeop vmovdqu8_avx512vl ; -:VMOVDQU8 XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVDQU8 XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovdqu8_avx512vl( XmmReg2_m128 ); @@ -1396,7 +1396,7 @@ define pcodeop vmovdqu8_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61941 -:VMOVDQU8 YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDQU8 YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovdqu8_avx512vl( YmmReg2_m256 ); @@ -1405,28 +1405,28 @@ define pcodeop vmovdqu8_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61944 define pcodeop vmovdqu8_avx512bw ; -:VMOVDQU8 ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU8 ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovdqu8_avx512bw( ZmmReg2_m512 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61947 -:VMOVDQU8 XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 +:VMOVDQU8 XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu8_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61950 -:VMOVDQU8 YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 +:VMOVDQU8 YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu8_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61953 -:VMOVDQU8 ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU8 ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu8_avx512bw( ZmmReg1 ); @@ -1434,7 +1434,7 @@ define pcodeop vmovdqu8_avx512bw ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61956 define pcodeop vmovdqu16_avx512vl ; -:VMOVDQU16 XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVDQU16 XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovdqu16_avx512vl( XmmReg2_m128 ); @@ -1442,7 +1442,7 @@ define pcodeop vmovdqu16_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61959 -:VMOVDQU16 YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDQU16 YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovdqu16_avx512vl( YmmReg2_m256 ); @@ -1451,28 +1451,28 @@ define pcodeop vmovdqu16_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61962 define pcodeop vmovdqu16_avx512bw ; -:VMOVDQU16 ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU16 ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovdqu16_avx512bw( ZmmReg2_m512 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61965 -:VMOVDQU16 XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 +:VMOVDQU16 XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu16_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61968 -:VMOVDQU16 YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 +:VMOVDQU16 YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu16_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61971 -:VMOVDQU16 ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU16 ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu16_avx512bw( ZmmReg1 ); @@ -1480,7 +1480,7 @@ define pcodeop vmovdqu16_avx512bw ; # MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61974 define pcodeop vmovdqu32_avx512vl ; -:VMOVDQU32 XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVDQU32 XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovdqu32_avx512vl( XmmReg2_m128 ); @@ -1488,7 +1488,7 @@ define pcodeop vmovdqu32_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61987 -:VMOVDQU32 YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDQU32 YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovdqu32_avx512vl( YmmReg2_m256 ); @@ -1497,28 +1497,28 @@ define pcodeop vmovdqu32_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61990 define pcodeop vmovdqu32_avx512f ; -:VMOVDQU32 ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU32 ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovdqu32_avx512f( ZmmReg2_m512 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61993 -:VMOVDQU32 XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 +:VMOVDQU32 XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu32_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61996 -:VMOVDQU32 YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 +:VMOVDQU32 YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu32_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 61999 -:VMOVDQU32 ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU32 ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu32_avx512f( ZmmReg1 ); @@ -1526,7 +1526,7 @@ define pcodeop vmovdqu32_avx512f ; # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62002 define pcodeop vmovdqu64_avx512vl ; -:VMOVDQU64 XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVDQU64 XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovdqu64_avx512vl( XmmReg2_m128 ); @@ -1534,7 +1534,7 @@ define pcodeop vmovdqu64_avx512vl ; } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62005 -:VMOVDQU64 YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVDQU64 YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovdqu64_avx512vl( YmmReg2_m256 ); @@ -1543,28 +1543,28 @@ define pcodeop vmovdqu64_avx512vl ; # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62008 define pcodeop vmovdqu64_avx512f ; -:VMOVDQU64 ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU64 ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x6F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovdqu64_avx512f( ZmmReg2_m512 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62011 -:VMOVDQU64 XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 +:VMOVDQU64 XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovdqu64_avx512vl( XmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62014 -:VMOVDQU64 YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 +:VMOVDQU64 YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovdqu64_avx512vl( YmmReg1 ); } # MOVDQU,VMOVDQU8/16/32/64 4-68 PAGE 1188 LINE 62017 -:VMOVDQU64 ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 +:VMOVDQU64 ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovdqu64_avx512f( ZmmReg1 ); @@ -1763,14 +1763,14 @@ define pcodeop vmovntps_avx512f ; # MOVSD 4-111 PAGE 1231 LINE 63978 define pcodeop vmovsd_avx512f ; -:VMOVSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2) +:VMOVSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2) { local tmp:16 = vmovsd_avx512f( vexVVVV_XmmReg, XmmReg2 ); ZmmReg1 = zext(tmp); } # MOVSD 4-111 PAGE 1231 LINE 63981 -:VMOVSD XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & m64 +:VMOVSD XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM) { local tmp:16 = vmovsd_avx512f( XmmReg1, m64 ); @@ -1778,14 +1778,14 @@ define pcodeop vmovsd_avx512f ; } # MOVSD 4-111 PAGE 1231 LINE 63983 -:VMOVSD XmmReg2 KWriteMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2)) +:VMOVSD XmmReg2^KWriteMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2)) { local tmp:16 = vmovsd_avx512f( vexVVVV_XmmReg, XmmReg1 ); ZmmReg2 = zext(tmp); } # MOVSD 4-111 PAGE 1231 LINE 63986 -:VMOVSD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; XmmReg1 ... & m64 +:VMOVSD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR) { m64 = vmovsd_avx512f( XmmReg1 ); @@ -1793,7 +1793,7 @@ define pcodeop vmovsd_avx512f ; # MOVSHDUP 4-114 PAGE 1234 LINE 64130 define pcodeop vmovshdup_avx512vl ; -:VMOVSHDUP XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x16; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVSHDUP XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x16; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vmovshdup_avx512vl( XmmReg2_m128 ); @@ -1801,7 +1801,7 @@ define pcodeop vmovshdup_avx512vl ; } # MOVSHDUP 4-114 PAGE 1234 LINE 64133 -:VMOVSHDUP YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVSHDUP YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vmovshdup_avx512vl( YmmReg2_m256 ); @@ -1810,7 +1810,7 @@ define pcodeop vmovshdup_avx512vl ; # MOVSHDUP 4-114 PAGE 1234 LINE 64136 define pcodeop vmovshdup_avx512f ; -:VMOVSHDUP ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x16; ZmmReg1 ... & ZmmReg2_m512 +:VMOVSHDUP ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x16; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vmovshdup_avx512f( ZmmReg2_m512 ); @@ -1818,7 +1818,7 @@ define pcodeop vmovshdup_avx512f ; # MOVSLDUP 4-117 PAGE 1237 LINE 64284 define pcodeop vmovsldup_avx512vl ; -:VMOVSLDUP XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVSLDUP XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vmovsldup_avx512vl( XmmReg2_m128 ); @@ -1826,7 +1826,7 @@ define pcodeop vmovsldup_avx512vl ; } # MOVSLDUP 4-117 PAGE 1237 LINE 64287 -:VMOVSLDUP YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVSLDUP YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vmovsldup_avx512vl( YmmReg2_m256 ); @@ -1835,7 +1835,7 @@ define pcodeop vmovsldup_avx512vl ; # MOVSLDUP 4-117 PAGE 1237 LINE 64290 define pcodeop vmovsldup_avx512f ; -:VMOVSLDUP ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x12; ZmmReg1 ... & ZmmReg2_m512 +:VMOVSLDUP ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x12; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vmovsldup_avx512f( ZmmReg2_m512 ); @@ -1843,14 +1843,14 @@ define pcodeop vmovsldup_avx512f ; # MOVSS 4-120 PAGE 1240 LINE 64443 define pcodeop vmovss_avx512f ; -:VMOVSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2) +:VMOVSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) & (mod=0x3 & XmmReg2) { local tmp:16 = vmovss_avx512f( vexVVVV_XmmReg, XmmReg2 ); ZmmReg1 = zext(tmp); } # MOVSS 4-120 PAGE 1240 LINE 64446 -:VMOVSS XmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & m32 +:VMOVSS XmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-RM) { local tmp:16 = vmovss_avx512f( XmmReg1, m32 ); @@ -1858,14 +1858,14 @@ define pcodeop vmovss_avx512f ; } # MOVSS 4-120 PAGE 1240 LINE 64448 -:VMOVSS XmmReg2 KWriteMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2)) +:VMOVSS XmmReg2^KWriteMask, vexVVVV_XmmReg, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & ZmmReg2)) { local tmp:16 = vmovss_avx512f( vexVVVV_XmmReg, XmmReg1 ); ZmmReg2 = zext(tmp); } # MOVSS 4-120 PAGE 1240 LINE 64451 -:VMOVSS m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & m32 +:VMOVSS m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S-MR) { m32 = vmovss_avx512f( XmmReg1 ); @@ -1873,7 +1873,7 @@ define pcodeop vmovss_avx512f ; # MOVUPD 4-126 PAGE 1246 LINE 64695 define pcodeop vmovupd_avx512vl ; -:VMOVUPD XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVUPD XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovupd_avx512vl( XmmReg2_m128 ); @@ -1881,14 +1881,14 @@ define pcodeop vmovupd_avx512vl ; } # MOVUPD 4-126 PAGE 1246 LINE 64698 -:VMOVUPD XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; XmmReg1 ... & XmmReg2_m128 +:VMOVUPD XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovupd_avx512vl( XmmReg1 ); } # MOVUPD 4-126 PAGE 1246 LINE 64701 -:VMOVUPD YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVUPD YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovupd_avx512vl( YmmReg2_m256 ); @@ -1896,7 +1896,7 @@ define pcodeop vmovupd_avx512vl ; } # MOVUPD 4-126 PAGE 1246 LINE 64704 -:VMOVUPD YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; YmmReg1 ... & YmmReg2_m256 +:VMOVUPD YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovupd_avx512vl( YmmReg1 ); @@ -1904,14 +1904,14 @@ define pcodeop vmovupd_avx512vl ; # MOVUPD 4-126 PAGE 1246 LINE 64707 define pcodeop vmovupd_avx512f ; -:VMOVUPD ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; ZmmReg1 ... & ZmmReg2_m512 +:VMOVUPD ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x10; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovupd_avx512f( ZmmReg2_m512 ); } # MOVUPD 4-126 PAGE 1246 LINE 64710 -:VMOVUPD ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 +:VMOVUPD ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovupd_avx512f( ZmmReg1 ); @@ -1919,7 +1919,7 @@ define pcodeop vmovupd_avx512f ; # MOVUPS 4-130 PAGE 1250 LINE 64880 define pcodeop vmovups_avx512vl ; -:VMOVUPS XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VMOVUPS XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:16 = vmovups_avx512vl( XmmReg2_m128 ); @@ -1927,7 +1927,7 @@ define pcodeop vmovups_avx512vl ; } # MOVUPS 4-130 PAGE 1250 LINE 64883 -:VMOVUPS YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VMOVUPS YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { local tmp:32 = vmovups_avx512vl( YmmReg2_m256 ); @@ -1936,28 +1936,28 @@ define pcodeop vmovups_avx512vl ; # MOVUPS 4-130 PAGE 1250 LINE 64886 define pcodeop vmovups_avx512f ; -:VMOVUPS ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; ZmmReg1 ... & ZmmReg2_m512 +:VMOVUPS ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x10; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-RM) { ZmmReg1 = vmovups_avx512f( ZmmReg2_m512 ); } # MOVUPS 4-130 PAGE 1250 LINE 64889 -:VMOVUPS XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & XmmReg2_m128 +:VMOVUPS XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { XmmReg2_m128 = vmovups_avx512vl( XmmReg1 ); } # MOVUPS 4-130 PAGE 1250 LINE 64892 -:VMOVUPS YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; YmmReg1 ... & YmmReg2_m256 +:VMOVUPS YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { YmmReg2_m256 = vmovups_avx512vl( YmmReg1 ); } # MOVUPS 4-130 PAGE 1250 LINE 64895 -:VMOVUPS ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 +:VMOVUPS ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM-MR) { ZmmReg2_m512 = vmovups_avx512f( ZmmReg1 ); @@ -1965,7 +1965,7 @@ define pcodeop vmovups_avx512f ; # MULPD 4-146 PAGE 1266 LINE 65686 define pcodeop vmulpd_avx512vl ; -:VMULPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VMULPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vmulpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -1973,7 +1973,7 @@ define pcodeop vmulpd_avx512vl ; } # MULPD 4-146 PAGE 1266 LINE 65689 -:VMULPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VMULPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vmulpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -1982,7 +1982,7 @@ define pcodeop vmulpd_avx512vl ; # MULPD 4-146 PAGE 1266 LINE 65692 define pcodeop vmulpd_avx512f ; -:VMULPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x59; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VMULPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x59; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vmulpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -1990,7 +1990,7 @@ define pcodeop vmulpd_avx512f ; # MULPS 4-149 PAGE 1269 LINE 65817 define pcodeop vmulps_avx512vl ; -:VMULPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VMULPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vmulps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -1998,7 +1998,7 @@ define pcodeop vmulps_avx512vl ; } # MULPS 4-149 PAGE 1269 LINE 65820 -:VMULPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VMULPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x59; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vmulps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2007,7 +2007,7 @@ define pcodeop vmulps_avx512vl ; # MULPS 4-149 PAGE 1269 LINE 65823 define pcodeop vmulps_avx512f ; -:VMULPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x59; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VMULPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x59; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vmulps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2015,7 +2015,7 @@ define pcodeop vmulps_avx512f ; # MULSD 4-152 PAGE 1272 LINE 65959 define pcodeop vmulsd_avx512f ; -:VMULSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VMULSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vmulsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -2024,7 +2024,7 @@ define pcodeop vmulsd_avx512f ; # MULSS 4-154 PAGE 1274 LINE 66055 define pcodeop vmulss_avx512f ; -:VMULSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VMULSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vmulss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -2033,7 +2033,7 @@ define pcodeop vmulss_avx512f ; # ORPD 4-168 PAGE 1288 LINE 66724 define pcodeop vorpd_avx512vl ; -:VORPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VORPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vorpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2041,7 +2041,7 @@ define pcodeop vorpd_avx512vl ; } # ORPD 4-168 PAGE 1288 LINE 66727 -:VORPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VORPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vorpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2050,7 +2050,7 @@ define pcodeop vorpd_avx512vl ; # ORPD 4-168 PAGE 1288 LINE 66730 define pcodeop vorpd_avx512dq ; -:VORPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VORPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2058,7 +2058,7 @@ define pcodeop vorpd_avx512dq ; # ORPS 4-171 PAGE 1291 LINE 66850 define pcodeop vorps_avx512vl ; -:VORPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VORPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vorps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2066,7 +2066,7 @@ define pcodeop vorps_avx512vl ; } # ORPS 4-171 PAGE 1291 LINE 66853 -:VORPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VORPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vorps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2075,7 +2075,7 @@ define pcodeop vorps_avx512vl ; # ORPS 4-171 PAGE 1291 LINE 66856 define pcodeop vorps_avx512dq ; -:VORPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VORPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2083,7 +2083,7 @@ define pcodeop vorps_avx512dq ; # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67320 define pcodeop vpabsb_avx512vl ; -:VPABSB XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPABSB XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpabsb_avx512vl( XmmReg2_m128 ); @@ -2091,7 +2091,7 @@ define pcodeop vpabsb_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67323 -:VPABSB YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPABSB YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpabsb_avx512vl( YmmReg2_m256 ); @@ -2100,7 +2100,7 @@ define pcodeop vpabsb_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67326 define pcodeop vpabsb_avx512bw ; -:VPABSB ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1C; ZmmReg1 ... & ZmmReg2_m512 +:VPABSB ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1C; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpabsb_avx512bw( ZmmReg2_m512 ); @@ -2108,7 +2108,7 @@ define pcodeop vpabsb_avx512bw ; # PABSB/PABSW/PABSD/PABSQ 4-180 PAGE 1300 LINE 67329 define pcodeop vpabsw_avx512vl ; -:VPABSW XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPABSW XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpabsw_avx512vl( XmmReg2_m128 ); @@ -2116,7 +2116,7 @@ define pcodeop vpabsw_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67344 -:VPABSW YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPABSW YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpabsw_avx512vl( YmmReg2_m256 ); @@ -2125,7 +2125,7 @@ define pcodeop vpabsw_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67347 define pcodeop vpabsw_avx512bw ; -:VPABSW ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1D; ZmmReg1 ... & ZmmReg2_m512 +:VPABSW ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x1D; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpabsw_avx512bw( ZmmReg2_m512 ); @@ -2133,7 +2133,7 @@ define pcodeop vpabsw_avx512bw ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67350 define pcodeop vpabsd_avx512vl ; -:VPABSD XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPABSD XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpabsd_avx512vl( XmmReg2_m128_m32bcst ); @@ -2141,7 +2141,7 @@ define pcodeop vpabsd_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67353 -:VPABSD YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPABSD YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpabsd_avx512vl( YmmReg2_m256_m32bcst ); @@ -2150,7 +2150,7 @@ define pcodeop vpabsd_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67357 define pcodeop vpabsd_avx512f ; -:VPABSD ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1E; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPABSD ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1E; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpabsd_avx512f( ZmmReg2_m512_m32bcst ); @@ -2158,7 +2158,7 @@ define pcodeop vpabsd_avx512f ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67360 define pcodeop vpabsq_avx512vl ; -:VPABSQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPABSQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpabsq_avx512vl( XmmReg2_m128_m64bcst ); @@ -2166,7 +2166,7 @@ define pcodeop vpabsq_avx512vl ; } # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67363 -:VPABSQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPABSQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpabsq_avx512vl( YmmReg2_m256_m64bcst ); @@ -2175,7 +2175,7 @@ define pcodeop vpabsq_avx512vl ; # PABSB/PABSW/PABSD/PABSQ 4-181 PAGE 1301 LINE 67366 define pcodeop vpabsq_avx512f ; -:VPABSQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1F; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPABSQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1F; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpabsq_avx512f( ZmmReg2_m512_m64bcst ); @@ -2183,7 +2183,7 @@ define pcodeop vpabsq_avx512f ; # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67645 define pcodeop vpacksswb_avx512vl ; -:VPACKSSWB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPACKSSWB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x63; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpacksswb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2191,7 +2191,7 @@ define pcodeop vpacksswb_avx512vl ; } # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67649 -:VPACKSSWB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPACKSSWB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x63; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpacksswb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2200,7 +2200,7 @@ define pcodeop vpacksswb_avx512vl ; # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67653 define pcodeop vpacksswb_avx512bw ; -:VPACKSSWB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x63; ZmmReg1 ... & ZmmReg2_m512 +:VPACKSSWB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x63; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpacksswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2208,7 +2208,7 @@ define pcodeop vpacksswb_avx512bw ; # PACKSSWB/PACKSSDW 4-186 PAGE 1306 LINE 67657 define pcodeop vpackssdw_avx512vl ; -:VPACKSSDW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPACKSSDW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x6B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpackssdw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2216,7 +2216,7 @@ define pcodeop vpackssdw_avx512vl ; } # PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67674 -:VPACKSSDW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPACKSSDW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x6B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpackssdw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2225,7 +2225,7 @@ define pcodeop vpackssdw_avx512vl ; # PACKSSWB/PACKSSDW 4-187 PAGE 1307 LINE 67678 define pcodeop vpackssdw_avx512bw ; -:VPACKSSDW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x6B; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPACKSSDW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x6B; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpackssdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2233,7 +2233,7 @@ define pcodeop vpackssdw_avx512bw ; # PACKUSDW 4-194 PAGE 1314 LINE 68094 define pcodeop vpackusdw_avx512vl ; -:VPACKUSDW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPACKUSDW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x2B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpackusdw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2241,7 +2241,7 @@ define pcodeop vpackusdw_avx512vl ; } # PACKUSDW 4-194 PAGE 1314 LINE 68098 -:VPACKUSDW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPACKUSDW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x2B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpackusdw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2250,7 +2250,7 @@ define pcodeop vpackusdw_avx512vl ; # PACKUSDW 4-194 PAGE 1314 LINE 68103 define pcodeop vpackusdw_avx512bw ; -:VPACKUSDW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x2B; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPACKUSDW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x2B; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpackusdw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2258,7 +2258,7 @@ define pcodeop vpackusdw_avx512bw ; # PACKUSWB 4-199 PAGE 1319 LINE 68374 define pcodeop vpackuswb_avx512vl ; -:VPACKUSWB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPACKUSWB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x67; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpackuswb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2266,7 +2266,7 @@ define pcodeop vpackuswb_avx512vl ; } # PACKUSWB 4-199 PAGE 1319 LINE 68378 -:VPACKUSWB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPACKUSWB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x67; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpackuswb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2275,7 +2275,7 @@ define pcodeop vpackuswb_avx512vl ; # PACKUSWB 4-199 PAGE 1319 LINE 68382 define pcodeop vpackuswb_avx512bw ; -:VPACKUSWB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x67; ZmmReg1 ... & ZmmReg2_m512 +:VPACKUSWB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x67; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpackuswb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2283,7 +2283,7 @@ define pcodeop vpackuswb_avx512bw ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68674 define pcodeop vpaddb_avx512vl ; -:VPADDB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPADDB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xFC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpaddb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2292,7 +2292,7 @@ define pcodeop vpaddb_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68677 define pcodeop vpaddw_avx512vl ; -:VPADDW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPADDW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xFD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpaddw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2301,7 +2301,7 @@ define pcodeop vpaddw_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68680 define pcodeop vpaddd_avx512vl ; -:VPADDD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPADDD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xFE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpaddd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2310,7 +2310,7 @@ define pcodeop vpaddd_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68683 define pcodeop vpaddq_avx512vl ; -:VPADDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPADDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xD4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpaddq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2318,7 +2318,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68686 -:VPADDB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPADDB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xFC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpaddb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2326,7 +2326,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68689 -:VPADDW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPADDW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xFD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpaddw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2334,7 +2334,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-204 PAGE 1324 LINE 68692 -:VPADDD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPADDD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xFE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpaddd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2342,7 +2342,7 @@ define pcodeop vpaddq_avx512vl ; } # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68707 -:VPADDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPADDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xD4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpaddq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2351,7 +2351,7 @@ define pcodeop vpaddq_avx512vl ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68710 define pcodeop vpaddb_avx512bw ; -:VPADDB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xFC; ZmmReg1 ... & ZmmReg2_m512 +:VPADDB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xFC; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpaddb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2359,7 +2359,7 @@ define pcodeop vpaddb_avx512bw ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68713 define pcodeop vpaddw_avx512bw ; -:VPADDW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xFD; ZmmReg1 ... & ZmmReg2_m512 +:VPADDW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xFD; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpaddw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2367,7 +2367,7 @@ define pcodeop vpaddw_avx512bw ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68716 define pcodeop vpaddd_avx512f ; -:VPADDD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xFE; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPADDD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xFE; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpaddd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2375,7 +2375,7 @@ define pcodeop vpaddd_avx512f ; # PADDB/PADDW/PADDD/PADDQ 4-205 PAGE 1325 LINE 68719 define pcodeop vpaddq_avx512f ; -:VPADDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xD4; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPADDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xD4; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpaddq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2383,7 +2383,7 @@ define pcodeop vpaddq_avx512f ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69051 define pcodeop vpaddsb_avx512vl ; -:VPADDSB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPADDSB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xEC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpaddsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2391,7 +2391,7 @@ define pcodeop vpaddsb_avx512vl ; } # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69054 -:VPADDSB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPADDSB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xEC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpaddsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2400,7 +2400,7 @@ define pcodeop vpaddsb_avx512vl ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69057 define pcodeop vpaddsb_avx512bw ; -:VPADDSB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xEC; ZmmReg1 ... & ZmmReg2_m512 +:VPADDSB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xEC; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpaddsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2408,7 +2408,7 @@ define pcodeop vpaddsb_avx512bw ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69060 define pcodeop vpaddsw_avx512vl ; -:VPADDSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPADDSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xED; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpaddsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2416,7 +2416,7 @@ define pcodeop vpaddsw_avx512vl ; } # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69063 -:VPADDSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPADDSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xED; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpaddsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2425,7 +2425,7 @@ define pcodeop vpaddsw_avx512vl ; # PADDSB/PADDSW 4-211 PAGE 1331 LINE 69066 define pcodeop vpaddsw_avx512bw ; -:VPADDSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xED; ZmmReg1 ... & ZmmReg2_m512 +:VPADDSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xED; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpaddsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2433,7 +2433,7 @@ define pcodeop vpaddsw_avx512bw ; # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69269 define pcodeop vpaddusb_avx512vl ; -:VPADDUSB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPADDUSB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xDC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpaddusb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2441,7 +2441,7 @@ define pcodeop vpaddusb_avx512vl ; } # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69273 -:VPADDUSB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPADDUSB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xDC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpaddusb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2450,7 +2450,7 @@ define pcodeop vpaddusb_avx512vl ; # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69277 define pcodeop vpaddusb_avx512bw ; -:VPADDUSB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xDC; ZmmReg1 ... & ZmmReg2_m512 +:VPADDUSB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xDC; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpaddusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2458,7 +2458,7 @@ define pcodeop vpaddusb_avx512bw ; # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69281 define pcodeop vpaddusw_avx512vl ; -:VPADDUSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPADDUSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xDD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpaddusw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2466,7 +2466,7 @@ define pcodeop vpaddusw_avx512vl ; } # PADDUSB/PADDUSW 4-215 PAGE 1335 LINE 69285 -:VPADDUSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPADDUSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xDD; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpaddusw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2475,7 +2475,7 @@ define pcodeop vpaddusw_avx512vl ; # PADDUSB/PADDUSW 4-216 PAGE 1336 LINE 69302 define pcodeop vpaddusw_avx512bw ; -:VPADDUSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xDD; ZmmReg1 ... & ZmmReg2_m512 +:VPADDUSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xDD; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpaddusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2483,7 +2483,7 @@ define pcodeop vpaddusw_avx512bw ; # PALIGNR 4-219 PAGE 1339 LINE 69495 define pcodeop vpalignr_avx512vl ; -:VPALIGNR XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPALIGNR XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x0F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpalignr_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2491,7 +2491,7 @@ define pcodeop vpalignr_avx512vl ; } # PALIGNR 4-219 PAGE 1339 LINE 69499 -:VPALIGNR YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPALIGNR YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x0F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpalignr_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2500,7 +2500,7 @@ define pcodeop vpalignr_avx512vl ; # PALIGNR 4-219 PAGE 1339 LINE 69505 define pcodeop vpalignr_avx512bw ; -:VPALIGNR ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x0F; ZmmReg1 ... & ZmmReg2_m512 +:VPALIGNR ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x0F; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpalignr_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2508,7 +2508,7 @@ define pcodeop vpalignr_avx512bw ; # PAND 4-223 PAGE 1343 LINE 69684 define pcodeop vpandd_avx512vl ; -:VPANDD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPANDD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpandd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2516,7 +2516,7 @@ define pcodeop vpandd_avx512vl ; } # PAND 4-223 PAGE 1343 LINE 69687 -:VPANDD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPANDD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpandd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2525,7 +2525,7 @@ define pcodeop vpandd_avx512vl ; # PAND 4-223 PAGE 1343 LINE 69690 define pcodeop vpandd_avx512f ; -:VPANDD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xDB; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPANDD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xDB; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpandd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2533,7 +2533,7 @@ define pcodeop vpandd_avx512f ; # PAND 4-223 PAGE 1343 LINE 69693 define pcodeop vpandq_avx512vl ; -:VPANDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPANDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xDB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpandq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2541,7 +2541,7 @@ define pcodeop vpandq_avx512vl ; } # PAND 4-223 PAGE 1343 LINE 69696 -:VPANDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPANDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xDB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpandq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2550,7 +2550,7 @@ define pcodeop vpandq_avx512vl ; # PAND 4-223 PAGE 1343 LINE 69699 define pcodeop vpandq_avx512f ; -:VPANDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xDB; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPANDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xDB; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpandq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2558,7 +2558,7 @@ define pcodeop vpandq_avx512f ; # PANDN 4-226 PAGE 1346 LINE 69859 define pcodeop vpandnd_avx512vl ; -:VPANDND XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPANDND XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpandnd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -2566,7 +2566,7 @@ define pcodeop vpandnd_avx512vl ; } # PANDN 4-226 PAGE 1346 LINE 69862 -:VPANDND YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPANDND YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpandnd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2575,7 +2575,7 @@ define pcodeop vpandnd_avx512vl ; # PANDN 4-226 PAGE 1346 LINE 69865 define pcodeop vpandnd_avx512f ; -:VPANDND ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xDF; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPANDND ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xDF; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpandnd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2583,7 +2583,7 @@ define pcodeop vpandnd_avx512f ; # PANDN 4-226 PAGE 1346 LINE 69868 define pcodeop vpandnq_avx512vl ; -:VPANDNQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPANDNQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xDF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpandnq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -2591,7 +2591,7 @@ define pcodeop vpandnq_avx512vl ; } # PANDN 4-226 PAGE 1346 LINE 69871 -:VPANDNQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPANDNQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xDF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpandnq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2600,7 +2600,7 @@ define pcodeop vpandnq_avx512vl ; # PANDN 4-226 PAGE 1346 LINE 69874 define pcodeop vpandnq_avx512f ; -:VPANDNQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xDF; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPANDNQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xDF; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpandnq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2608,7 +2608,7 @@ define pcodeop vpandnq_avx512f ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70097 define pcodeop vpavgb_avx512vl ; -:VPAVGB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPAVGB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE0; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpavgb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2616,7 +2616,7 @@ define pcodeop vpavgb_avx512vl ; } # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70100 -:VPAVGB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPAVGB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE0; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpavgb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2625,7 +2625,7 @@ define pcodeop vpavgb_avx512vl ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70103 define pcodeop vpavgb_avx512bw ; -:VPAVGB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE0; ZmmReg1 ... & ZmmReg2_m512 +:VPAVGB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE0; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpavgb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2633,7 +2633,7 @@ define pcodeop vpavgb_avx512bw ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70106 define pcodeop vpavgw_avx512vl ; -:VPAVGW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPAVGW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpavgw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2641,7 +2641,7 @@ define pcodeop vpavgw_avx512vl ; } # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70109 -:VPAVGW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPAVGW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE3; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpavgw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2650,7 +2650,7 @@ define pcodeop vpavgw_avx512vl ; # PAVGB/PAVGW 4-230 PAGE 1350 LINE 70112 define pcodeop vpavgw_avx512bw ; -:VPAVGW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE3; ZmmReg1 ... & ZmmReg2_m512 +:VPAVGW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE3; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpavgw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2658,14 +2658,14 @@ define pcodeop vpavgw_avx512bw ; # PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70841 define pcodeop vpcmpeqd_avx512vl ; -:VPCMPEQD KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x76; KReg_reg ... & XmmReg2_m128_m32bcst +:VPCMPEQD KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x76; KReg_reg ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpeqd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); } # PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70846 -:VPCMPEQD KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x76; KReg_reg ... & YmmReg2_m256_m32bcst +:VPCMPEQD KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x76; KReg_reg ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpeqd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2673,7 +2673,7 @@ define pcodeop vpcmpeqd_avx512vl ; # PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70851 define pcodeop vpcmpeqd_avx512f ; -:VPCMPEQD KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x76; KReg_reg ... & ZmmReg2_m512_m32bcst +:VPCMPEQD KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x76; KReg_reg ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpeqd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2681,14 +2681,14 @@ define pcodeop vpcmpeqd_avx512f ; # PCMPEQB/PCMPEQW/PCMPEQD 4-244 PAGE 1364 LINE 70855 define pcodeop vpcmpeqb_avx512vl ; -:VPCMPEQB KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x74; KReg_reg ... & XmmReg2_m128 +:VPCMPEQB KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x74; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpeqb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70873 -:VPCMPEQB KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x74; KReg_reg ... & YmmReg2_m256 +:VPCMPEQB KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x74; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpeqb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2696,7 +2696,7 @@ define pcodeop vpcmpeqb_avx512vl ; # PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70878 define pcodeop vpcmpeqb_avx512bw ; -:VPCMPEQB KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x74; KReg_reg ... & ZmmReg2_m512 +:VPCMPEQB KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x74; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpeqb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2704,14 +2704,14 @@ define pcodeop vpcmpeqb_avx512bw ; # PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70883 define pcodeop vpcmpeqw_avx512vl ; -:VPCMPEQW KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x75; KReg_reg ... & XmmReg2_m128 +:VPCMPEQW KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x75; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpeqw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70888 -:VPCMPEQW KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x75; KReg_reg ... & YmmReg2_m256 +:VPCMPEQW KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x75; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpeqw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2719,7 +2719,7 @@ define pcodeop vpcmpeqw_avx512vl ; # PCMPEQB/PCMPEQW/PCMPEQD 4-245 PAGE 1365 LINE 70893 define pcodeop vpcmpeqw_avx512bw ; -:VPCMPEQW KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x75; KReg_reg ... & ZmmReg2_m512 +:VPCMPEQW KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x75; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpeqw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2727,14 +2727,14 @@ define pcodeop vpcmpeqw_avx512bw ; # PCMPEQQ 4-250 PAGE 1370 LINE 71174 define pcodeop vpcmpeqq_avx512vl ; -:VPCMPEQQ KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x29; KReg_reg ... & XmmReg2_m128_m64bcst +:VPCMPEQQ KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x29; KReg_reg ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpeqq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); } # PCMPEQQ 4-250 PAGE 1370 LINE 71179 -:VPCMPEQQ KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x29; KReg_reg ... & YmmReg2_m256_m64bcst +:VPCMPEQQ KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x29; KReg_reg ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpeqq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2742,7 +2742,7 @@ define pcodeop vpcmpeqq_avx512vl ; # PCMPEQQ 4-250 PAGE 1370 LINE 71184 define pcodeop vpcmpeqq_avx512f ; -:VPCMPEQQ KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x29; KReg_reg ... & ZmmReg2_m512_m64bcst +:VPCMPEQQ KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x29; KReg_reg ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpeqq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2750,14 +2750,14 @@ define pcodeop vpcmpeqq_avx512f ; # PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71517 define pcodeop vpcmpgtd_avx512vl ; -:VPCMPGTD KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst +:VPCMPGTD KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpgtd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); } # PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71521 -:VPCMPGTD KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst +:VPCMPGTD KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpgtd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -2765,7 +2765,7 @@ define pcodeop vpcmpgtd_avx512vl ; # PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71525 define pcodeop vpcmpgtd_avx512f ; -:VPCMPGTD KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst +:VPCMPGTD KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpgtd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -2773,14 +2773,14 @@ define pcodeop vpcmpgtd_avx512f ; # PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71529 define pcodeop vpcmpgtb_avx512vl ; -:VPCMPGTB KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x64; KReg_reg ... & XmmReg2_m128 +:VPCMPGTB KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x64; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpgtb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71533 -:VPCMPGTB KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x64; KReg_reg ... & YmmReg2_m256 +:VPCMPGTB KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x64; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpgtb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2788,7 +2788,7 @@ define pcodeop vpcmpgtb_avx512vl ; # PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71545 define pcodeop vpcmpgtb_avx512bw ; -:VPCMPGTB KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x64; KReg_reg ... & ZmmReg2_m512 +:VPCMPGTB KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x64; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpgtb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2796,14 +2796,14 @@ define pcodeop vpcmpgtb_avx512bw ; # PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71549 define pcodeop vpcmpgtw_avx512vl ; -:VPCMPGTW KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x65; KReg_reg ... & XmmReg2_m128 +:VPCMPGTW KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x65; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpgtw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71553 -:VPCMPGTW KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x65; KReg_reg ... & YmmReg2_m256 +:VPCMPGTW KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x65; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpgtw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2811,7 +2811,7 @@ define pcodeop vpcmpgtw_avx512vl ; # PCMPGTB/PCMPGTW/PCMPGTD 4-258 PAGE 1378 LINE 71557 define pcodeop vpcmpgtw_avx512bw ; -:VPCMPGTW KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x65; KReg_reg ... & ZmmReg2_m512 +:VPCMPGTW KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x65; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpgtw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2819,14 +2819,14 @@ define pcodeop vpcmpgtw_avx512bw ; # PCMPGTQ 4-263 PAGE 1383 LINE 71837 define pcodeop vpcmpgtq_avx512vl ; -:VPCMPGTQ KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x37; KReg_reg ... & XmmReg2_m128_m64bcst +:VPCMPGTQ KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x37; KReg_reg ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpgtq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); } # PCMPGTQ 4-263 PAGE 1383 LINE 71841 -:VPCMPGTQ KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x37; KReg_reg ... & YmmReg2_m256_m64bcst +:VPCMPGTQ KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x37; KReg_reg ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpgtq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -2834,7 +2834,7 @@ define pcodeop vpcmpgtq_avx512vl ; # PCMPGTQ 4-263 PAGE 1383 LINE 71849 define pcodeop vpcmpgtq_avx512f ; -:VPCMPGTQ KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x37; KReg_reg ... & ZmmReg2_m512_m64bcst +:VPCMPGTQ KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x37; KReg_reg ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpgtq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -2919,7 +2919,7 @@ define pcodeop vpinsrw_avx512bw ; # PMADDUBSW 4-298 PAGE 1418 LINE 73558 define pcodeop vpmaddubsw_avx512vl ; -:VPMADDUBSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMADDUBSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmaddubsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2927,7 +2927,7 @@ define pcodeop vpmaddubsw_avx512vl ; } # PMADDUBSW 4-298 PAGE 1418 LINE 73562 -:VPMADDUBSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMADDUBSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmaddubsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2936,7 +2936,7 @@ define pcodeop vpmaddubsw_avx512vl ; # PMADDUBSW 4-298 PAGE 1418 LINE 73566 define pcodeop vpmaddubsw_avx512bw ; -:VPMADDUBSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x04; ZmmReg1 ... & ZmmReg2_m512 +:VPMADDUBSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x04; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmaddubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2944,7 +2944,7 @@ define pcodeop vpmaddubsw_avx512bw ; # PMADDWD 4-301 PAGE 1421 LINE 73708 define pcodeop vpmaddwd_avx512vl ; -:VPMADDWD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMADDWD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmaddwd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2952,7 +2952,7 @@ define pcodeop vpmaddwd_avx512vl ; } # PMADDWD 4-301 PAGE 1421 LINE 73712 -:VPMADDWD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMADDWD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmaddwd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2961,7 +2961,7 @@ define pcodeop vpmaddwd_avx512vl ; # PMADDWD 4-301 PAGE 1421 LINE 73716 define pcodeop vpmaddwd_avx512bw ; -:VPMADDWD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF5; ZmmReg1 ... & ZmmReg2_m512 +:VPMADDWD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF5; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmaddwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2969,7 +2969,7 @@ define pcodeop vpmaddwd_avx512bw ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73900 define pcodeop vpmaxsb_avx512vl ; -:VPMAXSB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMAXSB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x3C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmaxsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -2977,7 +2977,7 @@ define pcodeop vpmaxsb_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73903 -:VPMAXSB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMAXSB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x3C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmaxsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -2986,7 +2986,7 @@ define pcodeop vpmaxsb_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73906 define pcodeop vpmaxsb_avx512bw ; -:VPMAXSB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x3C; ZmmReg1 ... & ZmmReg2_m512 +:VPMAXSB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x3C; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmaxsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -2994,7 +2994,7 @@ define pcodeop vpmaxsb_avx512bw ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73909 define pcodeop vpmaxsw_avx512vl ; -:VPMAXSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMAXSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xEE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmaxsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3002,7 +3002,7 @@ define pcodeop vpmaxsw_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73912 -:VPMAXSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMAXSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xEE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmaxsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3011,7 +3011,7 @@ define pcodeop vpmaxsw_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73915 define pcodeop vpmaxsw_avx512bw ; -:VPMAXSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xEE; ZmmReg1 ... & ZmmReg2_m512 +:VPMAXSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xEE; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmaxsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3019,7 +3019,7 @@ define pcodeop vpmaxsw_avx512bw ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-304 PAGE 1424 LINE 73918 define pcodeop vpmaxsd_avx512vl ; -:VPMAXSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPMAXSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmaxsd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3027,7 +3027,7 @@ define pcodeop vpmaxsd_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73933 -:VPMAXSD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPMAXSD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmaxsd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3036,7 +3036,7 @@ define pcodeop vpmaxsd_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73936 define pcodeop vpmaxsd_avx512f ; -:VPMAXSD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3D; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPMAXSD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3D; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmaxsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3044,7 +3044,7 @@ define pcodeop vpmaxsd_avx512f ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73939 define pcodeop vpmaxsq_avx512vl ; -:VPMAXSQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMAXSQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmaxsq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3052,7 +3052,7 @@ define pcodeop vpmaxsq_avx512vl ; } # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73942 -:VPMAXSQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMAXSQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmaxsq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3061,7 +3061,7 @@ define pcodeop vpmaxsq_avx512vl ; # PMAXSB/PMAXSW/PMAXSD/PMAXSQ 4-305 PAGE 1425 LINE 73945 define pcodeop vpmaxsq_avx512f ; -:VPMAXSQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3D; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMAXSQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3D; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmaxsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3069,7 +3069,7 @@ define pcodeop vpmaxsq_avx512f ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74295 define pcodeop vpmaxub_avx512vl ; -:VPMAXUB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMAXUB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xDE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmaxub_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3077,7 +3077,7 @@ define pcodeop vpmaxub_avx512vl ; } # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74298 -:VPMAXUB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMAXUB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xDE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmaxub_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3086,7 +3086,7 @@ define pcodeop vpmaxub_avx512vl ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74301 define pcodeop vpmaxub_avx512bw ; -:VPMAXUB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xDE; ZmmReg1 ... & ZmmReg2_m512 +:VPMAXUB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xDE; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmaxub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3094,7 +3094,7 @@ define pcodeop vpmaxub_avx512bw ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74304 define pcodeop vpmaxuw_avx512vl ; -:VPMAXUW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMAXUW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x3E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmaxuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3102,7 +3102,7 @@ define pcodeop vpmaxuw_avx512vl ; } # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74307 -:VPMAXUW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMAXUW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x3E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmaxuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3111,7 +3111,7 @@ define pcodeop vpmaxuw_avx512vl ; # PMAXUB/PMAXUW 4-311 PAGE 1431 LINE 74310 define pcodeop vpmaxuw_avx512bw ; -:VPMAXUW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x3E; ZmmReg1 ... & ZmmReg2_m512 +:VPMAXUW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x3E; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmaxuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3119,7 +3119,7 @@ define pcodeop vpmaxuw_avx512bw ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74540 define pcodeop vpmaxud_avx512vl ; -:VPMAXUD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPMAXUD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmaxud_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3127,7 +3127,7 @@ define pcodeop vpmaxud_avx512vl ; } # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74543 -:VPMAXUD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPMAXUD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmaxud_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3136,7 +3136,7 @@ define pcodeop vpmaxud_avx512vl ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74546 define pcodeop vpmaxud_avx512f ; -:VPMAXUD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3F; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPMAXUD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3F; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmaxud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3144,7 +3144,7 @@ define pcodeop vpmaxud_avx512f ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74549 define pcodeop vpmaxuq_avx512vl ; -:VPMAXUQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMAXUQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmaxuq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3152,7 +3152,7 @@ define pcodeop vpmaxuq_avx512vl ; } # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74552 -:VPMAXUQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMAXUQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmaxuq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3161,7 +3161,7 @@ define pcodeop vpmaxuq_avx512vl ; # PMAXUD/PMAXUQ 4-316 PAGE 1436 LINE 74555 define pcodeop vpmaxuq_avx512f ; -:VPMAXUQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3F; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMAXUQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3F; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmaxuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3169,7 +3169,7 @@ define pcodeop vpmaxuq_avx512f ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74748 define pcodeop vpminsb_avx512vl ; -:VPMINSB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMINSB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x38; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpminsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3177,7 +3177,7 @@ define pcodeop vpminsb_avx512vl ; } # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74751 -:VPMINSB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMINSB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpminsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3186,7 +3186,7 @@ define pcodeop vpminsb_avx512vl ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74754 define pcodeop vpminsb_avx512bw ; -:VPMINSB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x38; ZmmReg1 ... & ZmmReg2_m512 +:VPMINSB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x38; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpminsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3194,7 +3194,7 @@ define pcodeop vpminsb_avx512bw ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74757 define pcodeop vpminsw_avx512vl ; -:VPMINSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMINSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xEA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpminsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3202,7 +3202,7 @@ define pcodeop vpminsw_avx512vl ; } # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74760 -:VPMINSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMINSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xEA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpminsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3211,7 +3211,7 @@ define pcodeop vpminsw_avx512vl ; # PMINSB/PMINSW 4-320 PAGE 1440 LINE 74763 define pcodeop vpminsw_avx512bw ; -:VPMINSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xEA; ZmmReg1 ... & ZmmReg2_m512 +:VPMINSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xEA; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpminsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3219,7 +3219,7 @@ define pcodeop vpminsw_avx512bw ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74995 define pcodeop vpminsd_avx512vl ; -:VPMINSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPMINSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpminsd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3227,7 +3227,7 @@ define pcodeop vpminsd_avx512vl ; } # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 74998 -:VPMINSD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPMINSD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpminsd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3236,7 +3236,7 @@ define pcodeop vpminsd_avx512vl ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75001 define pcodeop vpminsd_avx512f ; -:VPMINSD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x39; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPMINSD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x39; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpminsd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3244,7 +3244,7 @@ define pcodeop vpminsd_avx512f ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75004 define pcodeop vpminsq_avx512vl ; -:VPMINSQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMINSQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x39; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpminsq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3252,7 +3252,7 @@ define pcodeop vpminsq_avx512vl ; } # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75007 -:VPMINSQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMINSQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x39; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpminsq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3261,7 +3261,7 @@ define pcodeop vpminsq_avx512vl ; # PMINSD/PMINSQ 4-325 PAGE 1445 LINE 75010 define pcodeop vpminsq_avx512f ; -:VPMINSQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x39; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMINSQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x39; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpminsq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3269,7 +3269,7 @@ define pcodeop vpminsq_avx512f ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75207 define pcodeop vpminub_avx512vl ; -:VPMINUB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & KWriteMask & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMINUB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & KWriteMask & vexVVVV_XmmReg; byte=0xDA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpminub_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3277,7 +3277,7 @@ define pcodeop vpminub_avx512vl ; } # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75210 -:VPMINUB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & KWriteMask & vexVVVV_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMINUB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & KWriteMask & vexVVVV_YmmReg; byte=0xDA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpminub_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3286,7 +3286,7 @@ define pcodeop vpminub_avx512vl ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75213 define pcodeop vpminub_avx512bw ; -:VPMINUB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & KWriteMask & evexV5_ZmmReg; byte=0xDA; ZmmReg1 ... & ZmmReg2_m512 +:VPMINUB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & KWriteMask & evexV5_ZmmReg; byte=0xDA; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpminub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3294,7 +3294,7 @@ define pcodeop vpminub_avx512bw ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75216 define pcodeop vpminuw_avx512vl ; -:VPMINUW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & KWriteMask & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMINUW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & KWriteMask & vexVVVV_XmmReg; byte=0x3A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpminuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3302,7 +3302,7 @@ define pcodeop vpminuw_avx512vl ; } # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75219 -:VPMINUW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & KWriteMask & vexVVVV_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMINUW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & KWriteMask & vexVVVV_YmmReg; byte=0x3A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpminuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3311,7 +3311,7 @@ define pcodeop vpminuw_avx512vl ; # PMINUB/PMINUW 4-329 PAGE 1449 LINE 75222 define pcodeop vpminuw_avx512bw ; -:VPMINUW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & KWriteMask & evexV5_ZmmReg; byte=0x3A; ZmmReg1 ... & ZmmReg2_m512 +:VPMINUW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & KWriteMask & evexV5_ZmmReg; byte=0x3A; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpminuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3319,7 +3319,7 @@ define pcodeop vpminuw_avx512bw ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75451 define pcodeop vpminud_avx512vl ; -:VPMINUD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPMINUD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpminud_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3327,7 +3327,7 @@ define pcodeop vpminud_avx512vl ; } # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75454 -:VPMINUD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPMINUD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpminud_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3336,7 +3336,7 @@ define pcodeop vpminud_avx512vl ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75457 define pcodeop vpminud_avx512f ; -:VPMINUD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3B; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPMINUD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3B; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpminud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3344,7 +3344,7 @@ define pcodeop vpminud_avx512f ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75460 define pcodeop vpminuq_avx512vl ; -:VPMINUQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMINUQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpminuq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3352,7 +3352,7 @@ define pcodeop vpminuq_avx512vl ; } # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75463 -:VPMINUQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMINUQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpminuq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3361,7 +3361,7 @@ define pcodeop vpminuq_avx512vl ; # PMINUD/PMINUQ 4-334 PAGE 1454 LINE 75466 define pcodeop vpminuq_avx512f ; -:VPMINUQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3B; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMINUQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3B; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpminuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3369,7 +3369,7 @@ define pcodeop vpminuq_avx512f ; # PMOVSX 4-340 PAGE 1460 LINE 75796 define pcodeop vpmovsxbw_avx512vl ; -:VPMOVSXBW XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x20; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVSXBW XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x20; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovsxbw_avx512vl( XmmReg2_m64 ); @@ -3377,7 +3377,7 @@ define pcodeop vpmovsxbw_avx512vl ; } # PMOVSX 4-340 PAGE 1460 LINE 75799 -:VPMOVSXBW YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x20; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMOVSXBW YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x20; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovsxbw_avx512vl( XmmReg2_m128 ); @@ -3386,7 +3386,7 @@ define pcodeop vpmovsxbw_avx512vl ; # PMOVSX 4-340 PAGE 1460 LINE 75802 define pcodeop vpmovsxbw_avx512bw ; -:VPMOVSXBW ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x20; ZmmReg1 ... & YmmReg2_m256 +:VPMOVSXBW ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x20; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovsxbw_avx512bw( YmmReg2_m256 ); @@ -3394,7 +3394,7 @@ define pcodeop vpmovsxbw_avx512bw ; # PMOVSX 4-340 PAGE 1460 LINE 75805 define pcodeop vpmovsxbd_avx512vl ; -:VPMOVSXBD XmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPMOVSXBD XmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x21; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovsxbd_avx512vl( XmmReg2_m32 ); @@ -3402,7 +3402,7 @@ define pcodeop vpmovsxbd_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75819 -:VPMOVSXBD YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x21; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVSXBD YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x21; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovsxbd_avx512vl( XmmReg2_m64 ); @@ -3411,7 +3411,7 @@ define pcodeop vpmovsxbd_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75822 define pcodeop vpmovsxbd_avx512f ; -:VPMOVSXBD ZmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x21; ZmmReg1 ... & XmmReg2_m128 +:VPMOVSXBD ZmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x21; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovsxbd_avx512f( XmmReg2_m128 ); @@ -3419,7 +3419,7 @@ define pcodeop vpmovsxbd_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75825 define pcodeop vpmovsxbq_avx512vl ; -:VPMOVSXBQ XmmReg1 KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x22; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 +:VPMOVSXBQ XmmReg1^KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x22; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovsxbq_avx512vl( XmmReg2_m16 ); @@ -3427,7 +3427,7 @@ define pcodeop vpmovsxbq_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75828 -:VPMOVSXBQ YmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x22; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPMOVSXBQ YmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x22; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovsxbq_avx512vl( XmmReg2_m32 ); @@ -3436,7 +3436,7 @@ define pcodeop vpmovsxbq_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75831 define pcodeop vpmovsxbq_avx512f ; -:VPMOVSXBQ ZmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x22; ZmmReg1 ... & XmmReg2_m64 +:VPMOVSXBQ ZmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x22; ZmmReg1 ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovsxbq_avx512f( XmmReg2_m64 ); @@ -3444,7 +3444,7 @@ define pcodeop vpmovsxbq_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75834 define pcodeop vpmovsxwd_avx512vl ; -:VPMOVSXWD XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x23; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVSXWD XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x23; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovsxwd_avx512vl( XmmReg2_m64 ); @@ -3452,7 +3452,7 @@ define pcodeop vpmovsxwd_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75837 -:VPMOVSXWD YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x23; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMOVSXWD YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x23; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovsxwd_avx512vl( XmmReg2_m128 ); @@ -3461,7 +3461,7 @@ define pcodeop vpmovsxwd_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75840 define pcodeop vpmovsxwd_avx512f ; -:VPMOVSXWD ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x23; ZmmReg1 ... & YmmReg2_m256 +:VPMOVSXWD ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x23; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovsxwd_avx512f( YmmReg2_m256 ); @@ -3469,7 +3469,7 @@ define pcodeop vpmovsxwd_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75843 define pcodeop vpmovsxwq_avx512vl ; -:VPMOVSXWQ XmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x24; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPMOVSXWQ XmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x24; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovsxwq_avx512vl( XmmReg2_m32 ); @@ -3477,7 +3477,7 @@ define pcodeop vpmovsxwq_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75846 -:VPMOVSXWQ YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x24; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVSXWQ YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x24; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovsxwq_avx512vl( XmmReg2_m64 ); @@ -3486,7 +3486,7 @@ define pcodeop vpmovsxwq_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75849 define pcodeop vpmovsxwq_avx512f ; -:VPMOVSXWQ ZmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x24; ZmmReg1 ... & XmmReg2_m128 +:VPMOVSXWQ ZmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x24; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovsxwq_avx512f( XmmReg2_m128 ); @@ -3494,7 +3494,7 @@ define pcodeop vpmovsxwq_avx512f ; # PMOVSX 4-341 PAGE 1461 LINE 75852 define pcodeop vpmovsxdq_avx512vl ; -:VPMOVSXDQ XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVSXDQ XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovsxdq_avx512vl( XmmReg2_m64 ); @@ -3502,7 +3502,7 @@ define pcodeop vpmovsxdq_avx512vl ; } # PMOVSX 4-341 PAGE 1461 LINE 75855 -:VPMOVSXDQ YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMOVSXDQ YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovsxdq_avx512vl( XmmReg2_m128 ); @@ -3511,7 +3511,7 @@ define pcodeop vpmovsxdq_avx512vl ; # PMOVSX 4-341 PAGE 1461 LINE 75858 define pcodeop vpmovsxdq_avx512f ; -:VPMOVSXDQ ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; ZmmReg1 ... & YmmReg2_m256 +:VPMOVSXDQ ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovsxdq_avx512f( YmmReg2_m256 ); @@ -3519,7 +3519,7 @@ define pcodeop vpmovsxdq_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76329 define pcodeop vpmovzxbw_avx512vl ; -:VPMOVZXBW XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x30; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVZXBW XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x30; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovzxbw_avx512vl( XmmReg2_m64 ); @@ -3527,7 +3527,7 @@ define pcodeop vpmovzxbw_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76332 -:VPMOVZXBW YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x30; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMOVZXBW YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x30; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovzxbw_avx512vl( XmmReg2_m128 ); @@ -3536,7 +3536,7 @@ define pcodeop vpmovzxbw_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76335 define pcodeop vpmovzxbw_avx512bw ; -:VPMOVZXBW ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x30; ZmmReg1 ... & YmmReg2_m256 +:VPMOVZXBW ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x30; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovzxbw_avx512bw( YmmReg2_m256 ); @@ -3544,7 +3544,7 @@ define pcodeop vpmovzxbw_avx512bw ; # PMOVZX 4-351 PAGE 1471 LINE 76338 define pcodeop vpmovzxbd_avx512vl ; -:VPMOVZXBD XmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x31; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPMOVZXBD XmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x31; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovzxbd_avx512vl( XmmReg2_m32 ); @@ -3552,7 +3552,7 @@ define pcodeop vpmovzxbd_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76341 -:VPMOVZXBD YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x31; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVZXBD YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x31; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovzxbd_avx512vl( XmmReg2_m64 ); @@ -3561,7 +3561,7 @@ define pcodeop vpmovzxbd_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76344 define pcodeop vpmovzxbd_avx512f ; -:VPMOVZXBD ZmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x31; ZmmReg1 ... & XmmReg2_m128 +:VPMOVZXBD ZmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x31; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovzxbd_avx512f( XmmReg2_m128 ); @@ -3569,7 +3569,7 @@ define pcodeop vpmovzxbd_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76347 define pcodeop vpmovzxbq_avx512vl ; -:VPMOVZXBQ XmmReg1 KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x32; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 +:VPMOVZXBQ XmmReg1^KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x32; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovzxbq_avx512vl( XmmReg2_m16 ); @@ -3577,7 +3577,7 @@ define pcodeop vpmovzxbq_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76350 -:VPMOVZXBQ YmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x32; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPMOVZXBQ YmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x32; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovzxbq_avx512vl( XmmReg2_m32 ); @@ -3586,7 +3586,7 @@ define pcodeop vpmovzxbq_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76353 define pcodeop vpmovzxbq_avx512f ; -:VPMOVZXBQ ZmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x32; ZmmReg1 ... & XmmReg2_m64 +:VPMOVZXBQ ZmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x32; ZmmReg1 ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovzxbq_avx512f( XmmReg2_m64 ); @@ -3594,7 +3594,7 @@ define pcodeop vpmovzxbq_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76356 define pcodeop vpmovzxwd_avx512vl ; -:VPMOVZXWD XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x33; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVZXWD XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x33; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovzxwd_avx512vl( XmmReg2_m64 ); @@ -3602,7 +3602,7 @@ define pcodeop vpmovzxwd_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76359 -:VPMOVZXWD YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x33; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMOVZXWD YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x33; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovzxwd_avx512vl( XmmReg2_m128 ); @@ -3611,7 +3611,7 @@ define pcodeop vpmovzxwd_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76362 define pcodeop vpmovzxwd_avx512f ; -:VPMOVZXWD ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x33; ZmmReg1 ... & YmmReg2_m256 +:VPMOVZXWD ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x33; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovzxwd_avx512f( YmmReg2_m256 ); @@ -3619,7 +3619,7 @@ define pcodeop vpmovzxwd_avx512f ; # PMOVZX 4-351 PAGE 1471 LINE 76365 define pcodeop vpmovzxwq_avx512vl ; -:VPMOVZXWQ XmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x34; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPMOVZXWQ XmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x34; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovzxwq_avx512vl( XmmReg2_m32 ); @@ -3627,7 +3627,7 @@ define pcodeop vpmovzxwq_avx512vl ; } # PMOVZX 4-351 PAGE 1471 LINE 76368 -:VPMOVZXWQ YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x34; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVZXWQ YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x34; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovzxwq_avx512vl( XmmReg2_m64 ); @@ -3636,7 +3636,7 @@ define pcodeop vpmovzxwq_avx512vl ; # PMOVZX 4-351 PAGE 1471 LINE 76371 define pcodeop vpmovzxwq_avx512f ; -:VPMOVZXWQ ZmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x34; ZmmReg1 ... & XmmReg2_m128 +:VPMOVZXWQ ZmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask; byte=0x34; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovzxwq_avx512f( XmmReg2_m128 ); @@ -3644,7 +3644,7 @@ define pcodeop vpmovzxwq_avx512f ; # PMOVZX 4-352 PAGE 1472 LINE 76386 define pcodeop vpmovzxdq_avx512vl ; -:VPMOVZXDQ XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPMOVZXDQ XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:16 = vpmovzxdq_avx512vl( XmmReg2_m64 ); @@ -3652,7 +3652,7 @@ define pcodeop vpmovzxdq_avx512vl ; } # PMOVZX 4-352 PAGE 1472 LINE 76389 -:VPMOVZXDQ YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMOVZXDQ YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { local tmp:32 = vpmovzxdq_avx512vl( XmmReg2_m128 ); @@ -3661,7 +3661,7 @@ define pcodeop vpmovzxdq_avx512vl ; # PMOVZX 4-352 PAGE 1472 LINE 76392 define pcodeop vpmovzxdq_avx512f ; -:VPMOVZXDQ ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; ZmmReg1 ... & YmmReg2_m256 +:VPMOVZXDQ ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM,QVM,OVM) { ZmmReg1 = vpmovzxdq_avx512f( YmmReg2_m256 ); @@ -3669,7 +3669,7 @@ define pcodeop vpmovzxdq_avx512f ; # PMULDQ 4-359 PAGE 1479 LINE 76794 define pcodeop vpmuldq_avx512vl ; -:VPMULDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMULDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x28; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmuldq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3677,7 +3677,7 @@ define pcodeop vpmuldq_avx512vl ; } # PMULDQ 4-359 PAGE 1479 LINE 76798 -:VPMULDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMULDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x28; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmuldq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3686,7 +3686,7 @@ define pcodeop vpmuldq_avx512vl ; # PMULDQ 4-359 PAGE 1479 LINE 76802 define pcodeop vpmuldq_avx512f ; -:VPMULDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x28; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMULDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x28; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmuldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3694,7 +3694,7 @@ define pcodeop vpmuldq_avx512f ; # PMULHRSW 4-362 PAGE 1482 LINE 76934 define pcodeop vpmulhrsw_avx512vl ; -:VPMULHRSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMULHRSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmulhrsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3702,7 +3702,7 @@ define pcodeop vpmulhrsw_avx512vl ; } # PMULHRSW 4-362 PAGE 1482 LINE 76937 -:VPMULHRSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMULHRSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x0B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmulhrsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3711,7 +3711,7 @@ define pcodeop vpmulhrsw_avx512vl ; # PMULHRSW 4-362 PAGE 1482 LINE 76940 define pcodeop vpmulhrsw_avx512bw ; -:VPMULHRSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x0B; ZmmReg1 ... & ZmmReg2_m512 +:VPMULHRSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x0B; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmulhrsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3719,7 +3719,7 @@ define pcodeop vpmulhrsw_avx512bw ; # PMULHUW 4-366 PAGE 1486 LINE 77147 define pcodeop vpmulhuw_avx512vl ; -:VPMULHUW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMULHUW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmulhuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3727,7 +3727,7 @@ define pcodeop vpmulhuw_avx512vl ; } # PMULHUW 4-366 PAGE 1486 LINE 77151 -:VPMULHUW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMULHUW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmulhuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3736,7 +3736,7 @@ define pcodeop vpmulhuw_avx512vl ; # PMULHUW 4-366 PAGE 1486 LINE 77155 define pcodeop vpmulhuw_avx512bw ; -:VPMULHUW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE4; ZmmReg1 ... & ZmmReg2_m512 +:VPMULHUW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE4; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmulhuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3744,7 +3744,7 @@ define pcodeop vpmulhuw_avx512bw ; # PMULHW 4-370 PAGE 1490 LINE 77376 define pcodeop vpmulhw_avx512vl ; -:VPMULHW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMULHW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmulhw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3752,7 +3752,7 @@ define pcodeop vpmulhw_avx512vl ; } # PMULHW 4-370 PAGE 1490 LINE 77379 -:VPMULHW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMULHW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmulhw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3761,7 +3761,7 @@ define pcodeop vpmulhw_avx512vl ; # PMULHW 4-370 PAGE 1490 LINE 77382 define pcodeop vpmulhw_avx512bw ; -:VPMULHW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE5; ZmmReg1 ... & ZmmReg2_m512 +:VPMULHW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE5; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmulhw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3769,7 +3769,7 @@ define pcodeop vpmulhw_avx512bw ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77582 define pcodeop vpmulld_avx512vl ; -:VPMULLD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPMULLD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmulld_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3777,7 +3777,7 @@ define pcodeop vpmulld_avx512vl ; } # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77585 -:VPMULLD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPMULLD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmulld_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3786,7 +3786,7 @@ define pcodeop vpmulld_avx512vl ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77588 define pcodeop vpmulld_avx512f ; -:VPMULLD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x40; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPMULLD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x40; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmulld_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3794,7 +3794,7 @@ define pcodeop vpmulld_avx512f ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77591 define pcodeop vpmullq_avx512vl ; -:VPMULLQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMULLQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x40; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmullq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3802,7 +3802,7 @@ define pcodeop vpmullq_avx512vl ; } # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77594 -:VPMULLQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMULLQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x40; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmullq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3811,7 +3811,7 @@ define pcodeop vpmullq_avx512vl ; # PMULLD/PMULLQ 4-374 PAGE 1494 LINE 77597 define pcodeop vpmullq_avx512dq ; -:VPMULLQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x40; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMULLQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x40; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmullq_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3819,7 +3819,7 @@ define pcodeop vpmullq_avx512dq ; # PMULLW 4-378 PAGE 1498 LINE 77781 define pcodeop vpmullw_avx512vl ; -:VPMULLW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPMULLW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD5; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpmullw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3827,7 +3827,7 @@ define pcodeop vpmullw_avx512vl ; } # PMULLW 4-378 PAGE 1498 LINE 77784 -:VPMULLW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPMULLW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD5; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpmullw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3836,7 +3836,7 @@ define pcodeop vpmullw_avx512vl ; # PMULLW 4-378 PAGE 1498 LINE 77787 define pcodeop vpmullw_avx512bw ; -:VPMULLW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD5; ZmmReg1 ... & ZmmReg2_m512 +:VPMULLW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD5; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpmullw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3844,7 +3844,7 @@ define pcodeop vpmullw_avx512bw ; # PMULUDQ 4-382 PAGE 1502 LINE 77977 define pcodeop vpmuludq_avx512vl ; -:VPMULUDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPMULUDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xF4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpmuludq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3852,7 +3852,7 @@ define pcodeop vpmuludq_avx512vl ; } # PMULUDQ 4-382 PAGE 1502 LINE 77981 -:VPMULUDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPMULUDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xF4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpmuludq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3861,7 +3861,7 @@ define pcodeop vpmuludq_avx512vl ; # PMULUDQ 4-382 PAGE 1502 LINE 77985 define pcodeop vpmuludq_avx512f ; -:VPMULUDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xF4; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPMULUDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xF4; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpmuludq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3869,7 +3869,7 @@ define pcodeop vpmuludq_avx512f ; # POR 4-399 PAGE 1519 LINE 78854 define pcodeop vpord_avx512vl ; -:VPORD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPORD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpord_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -3877,7 +3877,7 @@ define pcodeop vpord_avx512vl ; } # POR 4-399 PAGE 1519 LINE 78857 -:VPORD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPORD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpord_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -3886,7 +3886,7 @@ define pcodeop vpord_avx512vl ; # POR 4-399 PAGE 1519 LINE 78860 define pcodeop vpord_avx512f ; -:VPORD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xEB; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPORD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xEB; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -3894,7 +3894,7 @@ define pcodeop vpord_avx512f ; # POR 4-399 PAGE 1519 LINE 78863 define pcodeop vporq_avx512vl ; -:VPORQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPORQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xEB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vporq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -3902,7 +3902,7 @@ define pcodeop vporq_avx512vl ; } # POR 4-399 PAGE 1519 LINE 78866 -:VPORQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPORQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xEB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vporq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -3911,7 +3911,7 @@ define pcodeop vporq_avx512vl ; # POR 4-399 PAGE 1519 LINE 78869 define pcodeop vporq_avx512f ; -:VPORQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xEB; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPORQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xEB; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vporq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -3944,7 +3944,7 @@ define pcodeop vpsadbw_avx512bw ; # PSHUFB 4-412 PAGE 1532 LINE 79466 define pcodeop vpshufb_avx512vl ; -:VPSHUFB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSHUFB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x00; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpshufb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -3952,7 +3952,7 @@ define pcodeop vpshufb_avx512vl ; } # PSHUFB 4-412 PAGE 1532 LINE 79468 -:VPSHUFB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSHUFB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x00; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpshufb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -3961,7 +3961,7 @@ define pcodeop vpshufb_avx512vl ; # PSHUFB 4-412 PAGE 1532 LINE 79470 define pcodeop vpshufb_avx512bw ; -:VPSHUFB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x00; ZmmReg1 ... & ZmmReg2_m512 +:VPSHUFB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x00; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpshufb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -3969,7 +3969,7 @@ define pcodeop vpshufb_avx512bw ; # PSHUFD 4-416 PAGE 1536 LINE 79656 define pcodeop vpshufd_avx512vl ; -:VPSHUFD XmmReg1 KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VPSHUFD XmmReg1^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpshufd_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -3977,7 +3977,7 @@ define pcodeop vpshufd_avx512vl ; } # PSHUFD 4-416 PAGE 1536 LINE 79659 -:VPSHUFD YmmReg1 KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VPSHUFD YmmReg1^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpshufd_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -3986,7 +3986,7 @@ define pcodeop vpshufd_avx512vl ; # PSHUFD 4-416 PAGE 1536 LINE 79662 define pcodeop vpshufd_avx512f ; -:VPSHUFD ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x70; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSHUFD ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x70; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpshufd_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -3994,7 +3994,7 @@ define pcodeop vpshufd_avx512f ; # PSHUFHW 4-420 PAGE 1540 LINE 79863 define pcodeop vpshufhw_avx512vl ; -:VPSHUFHW XmmReg1 KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VPSHUFHW XmmReg1^KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpshufhw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4002,7 +4002,7 @@ define pcodeop vpshufhw_avx512vl ; } # PSHUFHW 4-420 PAGE 1540 LINE 79866 -:VPSHUFHW YmmReg1 KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 +:VPSHUFHW YmmReg1^KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpshufhw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4011,7 +4011,7 @@ define pcodeop vpshufhw_avx512vl ; # PSHUFHW 4-420 PAGE 1540 LINE 79869 define pcodeop vpshufhw_avx512bw ; -:VPSHUFHW ZmmReg1 KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; ZmmReg1 ... & ZmmReg2_m512; imm8 +:VPSHUFHW ZmmReg1^KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; ZmmReg1 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpshufhw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4019,7 +4019,7 @@ define pcodeop vpshufhw_avx512bw ; # PSHUFLW 4-423 PAGE 1543 LINE 80038 define pcodeop vpshuflw_avx512vl ; -:VPSHUFLW XmmReg1 KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VPSHUFLW XmmReg1^KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpshuflw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4027,7 +4027,7 @@ define pcodeop vpshuflw_avx512vl ; } # PSHUFLW 4-423 PAGE 1543 LINE 80041 -:VPSHUFLW YmmReg1 KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 +:VPSHUFLW YmmReg1^KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpshuflw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4036,7 +4036,7 @@ define pcodeop vpshuflw_avx512vl ; # PSHUFLW 4-423 PAGE 1543 LINE 80044 define pcodeop vpshuflw_avx512bw ; -:VPSHUFLW ZmmReg1 KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; ZmmReg1 ... & ZmmReg2_m512; imm8 +:VPSHUFLW ZmmReg1^KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & KWriteMask; byte=0x70; ZmmReg1 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpshuflw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4069,7 +4069,7 @@ define pcodeop vpslldq_avx512bw ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80667 define pcodeop vpsllw_avx512vl ; -:VPSLLW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsllw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4077,7 +4077,7 @@ define pcodeop vpsllw_avx512vl ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80670 -:VPSLLW YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLW YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsllw_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4086,14 +4086,14 @@ define pcodeop vpsllw_avx512vl ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80673 define pcodeop vpsllw_avx512bw ; -:VPSLLW ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF1; ZmmReg1 ... & XmmReg2_m128 +:VPSLLW ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF1; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsllw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 ); } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80676 -:VPSLLW vexVVVV_XmmReg KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=6 ... & XmmReg2_m128; imm8 +:VPSLLW vexVVVV_XmmReg^KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=6 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { local tmp:64 = vpsllw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4101,7 +4101,7 @@ define pcodeop vpsllw_avx512bw ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80678 -:VPSLLW vexVVVV_YmmReg KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=6 ... & YmmReg2_m256; imm8 +:VPSLLW vexVVVV_YmmReg^KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=6 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { local tmp:64 = vpsllw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4109,7 +4109,7 @@ define pcodeop vpsllw_avx512bw ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80680 -:VPSLLW evexV5_ZmmReg KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & KWriteMask; byte=0x71; reg_opcode=6 ... & ZmmReg2_m512; imm8 +:VPSLLW evexV5_ZmmReg^KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & KWriteMask; byte=0x71; reg_opcode=6 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { evexV5_ZmmReg = vpsllw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4117,7 +4117,7 @@ define pcodeop vpsllw_avx512bw ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80682 define pcodeop vpslld_avx512vl ; -:VPSLLD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xF2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpslld_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4125,7 +4125,7 @@ define pcodeop vpslld_avx512vl ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80685 -:VPSLLD YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLD YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xF2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpslld_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4134,14 +4134,14 @@ define pcodeop vpslld_avx512vl ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80688 define pcodeop vpslld_avx512f ; -:VPSLLD ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xF2; ZmmReg1 ... & XmmReg2_m128 +:VPSLLD ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xF2; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpslld_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80691 -:VPSLLD vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=6 ... & XmmReg2_m128_m32bcst; imm8 +:VPSLLD vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=6 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpslld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -4149,7 +4149,7 @@ define pcodeop vpslld_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80694 -:VPSLLD vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=6 ... & YmmReg2_m256_m32bcst; imm8 +:VPSLLD vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=6 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpslld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -4157,7 +4157,7 @@ define pcodeop vpslld_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80697 -:VPSLLD evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=6 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSLLD evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=6 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { evexV5_ZmmReg = vpslld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -4165,7 +4165,7 @@ define pcodeop vpslld_avx512f ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80700 define pcodeop vpsllq_avx512vl ; -:VPSLLQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xF3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsllq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4173,7 +4173,7 @@ define pcodeop vpsllq_avx512vl ; } # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80703 -:VPSLLQ YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLQ YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xF3; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsllq_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4182,14 +4182,14 @@ define pcodeop vpsllq_avx512vl ; # PSLLW/PSLLD/PSLLQ 4-434 PAGE 1554 LINE 80706 define pcodeop vpsllq_avx512f ; -:VPSLLQ ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xF3; ZmmReg1 ... & XmmReg2_m128 +:VPSLLQ ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xF3; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsllq_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); } # PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80721 -:VPSLLQ vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=6 ... & XmmReg2_m128_m64bcst; imm8 +:VPSLLQ vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=6 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsllq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -4197,7 +4197,7 @@ define pcodeop vpsllq_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80724 -:VPSLLQ vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=6 ... & YmmReg2_m256_m64bcst; imm8 +:VPSLLQ vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=6 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsllq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -4205,7 +4205,7 @@ define pcodeop vpsllq_avx512f ; } # PSLLW/PSLLD/PSLLQ 4-435 PAGE 1555 LINE 80727 -:VPSLLQ evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x73; reg_opcode=6 ... & ZmmReg2_m512_m64bcst; imm8 +:VPSLLQ evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x73; reg_opcode=6 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { evexV5_ZmmReg = vpsllq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -4213,7 +4213,7 @@ define pcodeop vpsllq_avx512f ; # PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81329 define pcodeop vpsraw_avx512vl ; -:VPSRAW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsraw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4221,7 +4221,7 @@ define pcodeop vpsraw_avx512vl ; } # PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81332 -:VPSRAW YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAW YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsraw_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4230,14 +4230,14 @@ define pcodeop vpsraw_avx512vl ; # PSRAW/PSRAD/PSRAQ 4-445 PAGE 1565 LINE 81335 define pcodeop vpsraw_avx512bw ; -:VPSRAW ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE1; ZmmReg1 ... & XmmReg2_m128 +:VPSRAW ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE1; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsraw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 ); } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81350 -:VPSRAW vexVVVV_XmmReg KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=4 ... & XmmReg2_m128; imm8 +:VPSRAW vexVVVV_XmmReg^KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=4 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { local tmp:64 = vpsraw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4245,7 +4245,7 @@ define pcodeop vpsraw_avx512bw ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81352 -:VPSRAW vexVVVV_YmmReg KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=4 ... & YmmReg2_m256; imm8 +:VPSRAW vexVVVV_YmmReg^KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=4 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { local tmp:64 = vpsraw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4253,7 +4253,7 @@ define pcodeop vpsraw_avx512bw ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81354 -:VPSRAW evexV5_ZmmReg KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & KWriteMask; byte=0x71; reg_opcode=4 ... & ZmmReg2_m512; imm8 +:VPSRAW evexV5_ZmmReg^KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & KWriteMask; byte=0x71; reg_opcode=4 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVMI) { evexV5_ZmmReg = vpsraw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4261,7 +4261,7 @@ define pcodeop vpsraw_avx512bw ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81356 define pcodeop vpsrad_avx512vl ; -:VPSRAD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsrad_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4269,7 +4269,7 @@ define pcodeop vpsrad_avx512vl ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81359 -:VPSRAD YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAD YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsrad_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4278,14 +4278,14 @@ define pcodeop vpsrad_avx512vl ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81362 define pcodeop vpsrad_avx512f ; -:VPSRAD ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xE2; ZmmReg1 ... & XmmReg2_m128 +:VPSRAD ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xE2; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsrad_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81365 -:VPSRAD vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m32bcst; imm8 +:VPSRAD vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsrad_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -4293,7 +4293,7 @@ define pcodeop vpsrad_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81368 -:VPSRAD vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m32bcst; imm8 +:VPSRAD vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsrad_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -4301,7 +4301,7 @@ define pcodeop vpsrad_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81371 -:VPSRAD evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSRAD evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { evexV5_ZmmReg = vpsrad_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -4309,7 +4309,7 @@ define pcodeop vpsrad_avx512f ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81374 define pcodeop vpsraq_avx512vl ; -:VPSRAQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xE2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsraq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4317,7 +4317,7 @@ define pcodeop vpsraq_avx512vl ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81377 -:VPSRAQ YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAQ YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xE2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsraq_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4326,14 +4326,14 @@ define pcodeop vpsraq_avx512vl ; # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81380 define pcodeop vpsraq_avx512f ; -:VPSRAQ ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xE2; ZmmReg1 ... & XmmReg2_m128 +:VPSRAQ ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xE2; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsraq_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81383 -:VPSRAQ vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m64bcst; imm8 +:VPSRAQ vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsraq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -4341,7 +4341,7 @@ define pcodeop vpsraq_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81386 -:VPSRAQ vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m64bcst; imm8 +:VPSRAQ vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=4 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsraq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -4349,7 +4349,7 @@ define pcodeop vpsraq_avx512f ; } # PSRAW/PSRAD/PSRAQ 4-446 PAGE 1566 LINE 81389 -:VPSRAQ evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m64bcst; imm8 +:VPSRAQ evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=4 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { evexV5_ZmmReg = vpsraq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -4382,7 +4382,7 @@ define pcodeop vpsrldq_avx512bw ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82059 define pcodeop vpsrlw_avx512vl ; -:VPSRLW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD1; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsrlw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4390,7 +4390,7 @@ define pcodeop vpsrlw_avx512vl ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82062 -:VPSRLW YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLW YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD1; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsrlw_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4399,14 +4399,14 @@ define pcodeop vpsrlw_avx512vl ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82065 define pcodeop vpsrlw_avx512bw ; -:VPSRLW ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD1; ZmmReg1 ... & XmmReg2_m128 +:VPSRLW ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD1; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsrlw_avx512bw( evexV5_ZmmReg, XmmReg2_m128 ); } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82068 -:VPSRLW vexVVVV_XmmReg KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=2 ... & XmmReg2_m128; imm8 +:VPSRLW vexVVVV_XmmReg^KWriteMask, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=2 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:64 = vpsrlw_avx512vl( XmmReg2_m128, imm8:1 ); @@ -4414,7 +4414,7 @@ define pcodeop vpsrlw_avx512bw ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82070 -:VPSRLW vexVVVV_YmmReg KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=2 ... & YmmReg2_m256; imm8 +:VPSRLW vexVVVV_YmmReg^KWriteMask, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x71; reg_opcode=2 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:64 = vpsrlw_avx512vl( YmmReg2_m256, imm8:1 ); @@ -4422,7 +4422,7 @@ define pcodeop vpsrlw_avx512bw ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82072 -:VPSRLW evexV5_ZmmReg KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & KWriteMask; byte=0x71; reg_opcode=2 ... & ZmmReg2_m512; imm8 +:VPSRLW evexV5_ZmmReg^KWriteMask, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & evexV5_ZmmReg & KWriteMask; byte=0x71; reg_opcode=2 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { evexV5_ZmmReg = vpsrlw_avx512bw( ZmmReg2_m512, imm8:1 ); @@ -4430,7 +4430,7 @@ define pcodeop vpsrlw_avx512bw ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82074 define pcodeop vpsrld_avx512vl ; -:VPSRLD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xD2; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsrld_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4438,7 +4438,7 @@ define pcodeop vpsrld_avx512vl ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82077 -:VPSRLD YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLD YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xD2; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsrld_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4447,14 +4447,14 @@ define pcodeop vpsrld_avx512vl ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82080 define pcodeop vpsrld_avx512f ; -:VPSRLD ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xD2; ZmmReg1 ... & XmmReg2_m128 +:VPSRLD ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xD2; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsrld_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82084 -:VPSRLD vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=2 ... & XmmReg2_m128_m32bcst; imm8 +:VPSRLD vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=2 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsrld_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -4462,7 +4462,7 @@ define pcodeop vpsrld_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82088 -:VPSRLD vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=2 ... & YmmReg2_m256_m32bcst; imm8 +:VPSRLD vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=2 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsrld_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -4470,7 +4470,7 @@ define pcodeop vpsrld_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82091 -:VPSRLD evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=2 ... & ZmmReg2_m512_m32bcst; imm8 +:VPSRLD evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=2 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { evexV5_ZmmReg = vpsrld_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -4478,7 +4478,7 @@ define pcodeop vpsrld_avx512f ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82094 define pcodeop vpsrlq_avx512vl ; -:VPSRLQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xD3; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:16 = vpsrlq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4486,7 +4486,7 @@ define pcodeop vpsrlq_avx512vl ; } # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82097 -:VPSRLQ YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLQ YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xD3; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { local tmp:32 = vpsrlq_avx512vl( vexVVVV_YmmReg, XmmReg2_m128 ); @@ -4495,14 +4495,14 @@ define pcodeop vpsrlq_avx512vl ; # PSRLW/PSRLD/PSRLQ 4-458 PAGE 1578 LINE 82100 define pcodeop vpsrlq_avx512f ; -:VPSRLQ ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xD3; ZmmReg1 ... & XmmReg2_m128 +:VPSRLQ ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xD3; ZmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 12; ] # (TupleType M128) { ZmmReg1 = vpsrlq_avx512f( evexV5_ZmmReg, XmmReg2_m128 ); } # PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82115 -:VPSRLQ vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=2 ... & XmmReg2_m128_m64bcst; imm8 +:VPSRLQ vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=2 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsrlq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -4510,7 +4510,7 @@ define pcodeop vpsrlq_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82119 -:VPSRLQ vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=2 ... & YmmReg2_m256_m64bcst; imm8 +:VPSRLQ vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x73; reg_opcode=2 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:64 = vpsrlq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -4518,7 +4518,7 @@ define pcodeop vpsrlq_avx512f ; } # PSRLW/PSRLD/PSRLQ 4-459 PAGE 1579 LINE 82122 -:VPSRLQ evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x73; reg_opcode=2 ... & ZmmReg2_m512_m64bcst; imm8 +:VPSRLQ evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x73; reg_opcode=2 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { evexV5_ZmmReg = vpsrlq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -4526,7 +4526,7 @@ define pcodeop vpsrlq_avx512f ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82702 define pcodeop vpsubb_avx512vl ; -:VPSUBB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSUBB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsubb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4534,7 +4534,7 @@ define pcodeop vpsubb_avx512vl ; } # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82705 -:VPSUBB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSUBB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsubb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4543,7 +4543,7 @@ define pcodeop vpsubb_avx512vl ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82708 define pcodeop vpsubb_avx512bw ; -:VPSUBB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF8; ZmmReg1 ... & ZmmReg2_m512 +:VPSUBB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF8; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsubb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4551,7 +4551,7 @@ define pcodeop vpsubb_avx512bw ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82711 define pcodeop vpsubw_avx512vl ; -:VPSUBW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSUBW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xF9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsubw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4559,7 +4559,7 @@ define pcodeop vpsubw_avx512vl ; } # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82714 -:VPSUBW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSUBW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xF9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsubw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4568,7 +4568,7 @@ define pcodeop vpsubw_avx512vl ; # PSUBB/PSUBW/PSUBD 4-469 PAGE 1589 LINE 82717 define pcodeop vpsubw_avx512bw ; -:VPSUBW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF9; ZmmReg1 ... & ZmmReg2_m512 +:VPSUBW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xF9; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsubw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4576,7 +4576,7 @@ define pcodeop vpsubw_avx512bw ; # PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82733 define pcodeop vpsubd_avx512vl ; -:VPSUBD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPSUBD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xFA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsubd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -4584,7 +4584,7 @@ define pcodeop vpsubd_avx512vl ; } # PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82736 -:VPSUBD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPSUBD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xFA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsubd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -4593,7 +4593,7 @@ define pcodeop vpsubd_avx512vl ; # PSUBB/PSUBW/PSUBD 4-470 PAGE 1590 LINE 82743 define pcodeop vpsubd_avx512f ; -:VPSUBD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xFA; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPSUBD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xFA; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsubd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -4601,7 +4601,7 @@ define pcodeop vpsubd_avx512f ; # PSUBQ 4-476 PAGE 1596 LINE 83111 define pcodeop vpsubq_avx512vl ; -:VPSUBQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPSUBQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xFB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsubq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4609,7 +4609,7 @@ define pcodeop vpsubq_avx512vl ; } # PSUBQ 4-476 PAGE 1596 LINE 83114 -:VPSUBQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPSUBQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xFB; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsubq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4618,7 +4618,7 @@ define pcodeop vpsubq_avx512vl ; # PSUBQ 4-476 PAGE 1596 LINE 83117 define pcodeop vpsubq_avx512f ; -:VPSUBQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xFB; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPSUBQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xFB; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsubq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4626,7 +4626,7 @@ define pcodeop vpsubq_avx512f ; # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83270 define pcodeop vpsubsb_avx512vl ; -:VPSUBSB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSUBSB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsubsb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4634,7 +4634,7 @@ define pcodeop vpsubsb_avx512vl ; } # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83274 -:VPSUBSB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSUBSB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsubsb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4643,7 +4643,7 @@ define pcodeop vpsubsb_avx512vl ; # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83278 define pcodeop vpsubsb_avx512bw ; -:VPSUBSB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE8; ZmmReg1 ... & ZmmReg2_m512 +:VPSUBSB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE8; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsubsb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4651,7 +4651,7 @@ define pcodeop vpsubsb_avx512bw ; # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83282 define pcodeop vpsubsw_avx512vl ; -:VPSUBSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSUBSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xE9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsubsw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4659,7 +4659,7 @@ define pcodeop vpsubsw_avx512vl ; } # PSUBSB/PSUBSW 4-479 PAGE 1599 LINE 83286 -:VPSUBSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSUBSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xE9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsubsw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4669,14 +4669,14 @@ define pcodeop vpsubsw_avx512vl ; # PSUBSB/PSUBSW 4-480 PAGE 1600 LINE 83302 # WARNING: did not recognize VEX field 512 for "PSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512" define pcodeop psubsw_avx512bw ; -:PSUBSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE9; ZmmReg1 ... & ZmmReg2_m512 +:PSUBSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(VEX_NDS) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xE9; ZmmReg1 ... & ZmmReg2_m512 { ZmmReg1 = psubsw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); } # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83510 define pcodeop vpsubusb_avx512vl ; -:VPSUBUSB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSUBUSB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsubusb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4684,7 +4684,7 @@ define pcodeop vpsubusb_avx512vl ; } # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83514 -:VPSUBUSB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSUBUSB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsubusb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4693,7 +4693,7 @@ define pcodeop vpsubusb_avx512vl ; # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83518 define pcodeop vpsubusb_avx512bw ; -:VPSUBUSB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD8; ZmmReg1 ... & ZmmReg2_m512 +:VPSUBUSB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD8; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsubusb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4701,7 +4701,7 @@ define pcodeop vpsubusb_avx512bw ; # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83522 define pcodeop vpsubusw_avx512vl ; -:VPSUBUSW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSUBUSW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0xD9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsubusw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4709,7 +4709,7 @@ define pcodeop vpsubusw_avx512vl ; } # PSUBUSB/PSUBUSW 4-483 PAGE 1603 LINE 83526 -:VPSUBUSW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSUBUSW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0xD9; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsubusw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4718,7 +4718,7 @@ define pcodeop vpsubusw_avx512vl ; # PSUBUSB/PSUBUSW 4-484 PAGE 1604 LINE 83543 define pcodeop vpsubusw_avx512bw ; -:VPSUBUSW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD9; ZmmReg1 ... & ZmmReg2_m512 +:VPSUBUSW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0xD9; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsubusw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4726,7 +4726,7 @@ define pcodeop vpsubusw_avx512bw ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83948 define pcodeop vpunpckhbw_avx512vl ; -:VPUNPCKHBW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPUNPCKHBW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x68; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpunpckhbw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4735,7 +4735,7 @@ define pcodeop vpunpckhbw_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83952 define pcodeop vpunpckhwd_avx512vl ; -:VPUNPCKHWD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPUNPCKHWD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x69; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpunpckhwd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4744,7 +4744,7 @@ define pcodeop vpunpckhwd_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83955 define pcodeop vpunpckhdq_avx512vl ; -:VPUNPCKHDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPUNPCKHDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x6A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpunpckhdq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -4753,7 +4753,7 @@ define pcodeop vpunpckhdq_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-491 PAGE 1611 LINE 83958 define pcodeop vpunpckhqdq_avx512vl ; -:VPUNPCKHQDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPUNPCKHQDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x6D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpunpckhqdq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4761,7 +4761,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83974 -:VPUNPCKHBW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPUNPCKHBW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x68; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpunpckhbw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4769,7 +4769,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83977 -:VPUNPCKHWD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPUNPCKHWD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x69; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpunpckhwd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4777,7 +4777,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83980 -:VPUNPCKHDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPUNPCKHDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x6A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpunpckhdq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -4785,7 +4785,7 @@ define pcodeop vpunpckhqdq_avx512vl ; } # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83984 -:VPUNPCKHQDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPUNPCKHQDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x6D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpunpckhqdq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4794,7 +4794,7 @@ define pcodeop vpunpckhqdq_avx512vl ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83988 define pcodeop vpunpckhbw_avx512bw ; -:VPUNPCKHBW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x68; ZmmReg1 ... & ZmmReg2_m512 +:VPUNPCKHBW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x68; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpunpckhbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4802,7 +4802,7 @@ define pcodeop vpunpckhbw_avx512bw ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83991 define pcodeop vpunpckhwd_avx512bw ; -:VPUNPCKHWD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x69; ZmmReg1 ... & ZmmReg2_m512 +:VPUNPCKHWD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x69; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpunpckhwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4810,7 +4810,7 @@ define pcodeop vpunpckhwd_avx512bw ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83994 define pcodeop vpunpckhdq_avx512f ; -:VPUNPCKHDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x6A; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPUNPCKHDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x6A; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpunpckhdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -4818,7 +4818,7 @@ define pcodeop vpunpckhdq_avx512f ; # PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ 4-492 PAGE 1612 LINE 83997 define pcodeop vpunpckhqdq_avx512f ; -:VPUNPCKHQDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x6D; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPUNPCKHQDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x6D; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpunpckhqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4826,7 +4826,7 @@ define pcodeop vpunpckhqdq_avx512f ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84553 define pcodeop vpunpcklbw_avx512vl ; -:VPUNPCKLBW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPUNPCKLBW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x60; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpunpcklbw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4835,7 +4835,7 @@ define pcodeop vpunpcklbw_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84556 define pcodeop vpunpcklwd_avx512vl ; -:VPUNPCKLWD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPUNPCKLWD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_XmmReg; byte=0x61; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpunpcklwd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -4844,7 +4844,7 @@ define pcodeop vpunpcklwd_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84559 define pcodeop vpunpckldq_avx512vl ; -:VPUNPCKLDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPUNPCKLDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x62; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpunpckldq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -4853,7 +4853,7 @@ define pcodeop vpunpckldq_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-501 PAGE 1621 LINE 84562 define pcodeop vpunpcklqdq_avx512vl ; -:VPUNPCKLQDQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPUNPCKLQDQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x6C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpunpcklqdq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4861,7 +4861,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84578 -:VPUNPCKLBW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPUNPCKLBW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x60; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpunpcklbw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4869,7 +4869,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84581 -:VPUNPCKLWD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPUNPCKLWD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & vexVVVV_YmmReg; byte=0x61; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpunpcklwd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -4877,7 +4877,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84584 -:VPUNPCKLDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPUNPCKLDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x62; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpunpckldq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -4885,7 +4885,7 @@ define pcodeop vpunpcklqdq_avx512vl ; } # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84587 -:VPUNPCKLQDQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPUNPCKLQDQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x6C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpunpcklqdq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4894,7 +4894,7 @@ define pcodeop vpunpcklqdq_avx512vl ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84590 define pcodeop vpunpcklbw_avx512bw ; -:VPUNPCKLBW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x60; ZmmReg1 ... & ZmmReg2_m512 +:VPUNPCKLBW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x60; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpunpcklbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4902,7 +4902,7 @@ define pcodeop vpunpcklbw_avx512bw ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84593 define pcodeop vpunpcklwd_avx512bw ; -:VPUNPCKLWD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x61; ZmmReg1 ... & ZmmReg2_m512 +:VPUNPCKLWD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & KWriteMask & evexV5_ZmmReg; byte=0x61; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpunpcklwd_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -4910,7 +4910,7 @@ define pcodeop vpunpcklwd_avx512bw ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84596 define pcodeop vpunpckldq_avx512f ; -:VPUNPCKLDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x62; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPUNPCKLDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x62; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpunpckldq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -4918,7 +4918,7 @@ define pcodeop vpunpckldq_avx512f ; # PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ 4-502 PAGE 1622 LINE 84599 define pcodeop vpunpcklqdq_avx512f ; -:VPUNPCKLQDQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x6C; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPUNPCKLQDQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x6C; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpunpcklqdq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4926,7 +4926,7 @@ define pcodeop vpunpcklqdq_avx512f ; # PXOR 4-518 PAGE 1638 LINE 85503 define pcodeop vpxord_avx512vl ; -:VPXORD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPXORD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpxord_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -4934,7 +4934,7 @@ define pcodeop vpxord_avx512vl ; } # PXOR 4-518 PAGE 1638 LINE 85505 -:VPXORD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPXORD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpxord_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -4943,7 +4943,7 @@ define pcodeop vpxord_avx512vl ; # PXOR 4-518 PAGE 1638 LINE 85507 define pcodeop vpxord_avx512f ; -:VPXORD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xEF; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPXORD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xEF; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpxord_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -4951,7 +4951,7 @@ define pcodeop vpxord_avx512f ; # PXOR 4-518 PAGE 1638 LINE 85514 define pcodeop vpxorq_avx512vl ; -:VPXORQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPXORQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xEF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpxorq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -4959,7 +4959,7 @@ define pcodeop vpxorq_avx512vl ; } # PXOR 4-518 PAGE 1638 LINE 85521 -:VPXORQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPXORQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xEF; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpxorq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -4968,7 +4968,7 @@ define pcodeop vpxorq_avx512vl ; # PXOR 4-518 PAGE 1638 LINE 85523 define pcodeop vpxorq_avx512f ; -:VPXORQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xEF; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPXORQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xEF; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpxorq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -4976,7 +4976,7 @@ define pcodeop vpxorq_avx512f ; # SHUFPD 4-617 PAGE 1737 LINE 90231 define pcodeop vshufpd_avx512vl ; -:VSHUFPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VSHUFPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vshufpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -4984,7 +4984,7 @@ define pcodeop vshufpd_avx512vl ; } # SHUFPD 4-617 PAGE 1737 LINE 90235 -:VSHUFPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VSHUFPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vshufpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -4993,7 +4993,7 @@ define pcodeop vshufpd_avx512vl ; # SHUFPD 4-617 PAGE 1737 LINE 90239 define pcodeop vshufpd_avx512f ; -:VSHUFPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xC6; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VSHUFPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xC6; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vshufpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -5001,7 +5001,7 @@ define pcodeop vshufpd_avx512f ; # SHUFPS 4-622 PAGE 1742 LINE 90489 define pcodeop vshufps_avx512vl ; -:VSHUFPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VSHUFPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xC6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vshufps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -5009,7 +5009,7 @@ define pcodeop vshufps_avx512vl ; } # SHUFPS 4-622 PAGE 1742 LINE 90493 -:VSHUFPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VSHUFPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xC6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vshufps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -5018,7 +5018,7 @@ define pcodeop vshufps_avx512vl ; # SHUFPS 4-622 PAGE 1742 LINE 90497 define pcodeop vshufps_avx512f ; -:VSHUFPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xC6; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VSHUFPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xC6; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vshufps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -5026,7 +5026,7 @@ define pcodeop vshufps_avx512f ; # SQRTPD 4-632 PAGE 1752 LINE 91007 define pcodeop vsqrtpd_avx512vl ; -:VSQRTPD XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VSQRTPD XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vsqrtpd_avx512vl( XmmReg2_m128_m32bcst ); @@ -5034,7 +5034,7 @@ define pcodeop vsqrtpd_avx512vl ; } # SQRTPD 4-632 PAGE 1752 LINE 91010 -:VSQRTPD YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VSQRTPD YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vsqrtpd_avx512vl( YmmReg2_m256_m32bcst ); @@ -5043,7 +5043,7 @@ define pcodeop vsqrtpd_avx512vl ; # SQRTPD 4-632 PAGE 1752 LINE 91013 define pcodeop vsqrtpd_avx512f ; -:VSQRTPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VSQRTPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vsqrtpd_avx512f( ZmmReg2_m512_m64bcst ); @@ -5051,7 +5051,7 @@ define pcodeop vsqrtpd_avx512f ; # SQRTPS 4-635 PAGE 1755 LINE 91139 define pcodeop vsqrtps_avx512vl ; -:VSQRTPS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VSQRTPS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vsqrtps_avx512vl( XmmReg2_m128_m32bcst ); @@ -5059,7 +5059,7 @@ define pcodeop vsqrtps_avx512vl ; } # SQRTPS 4-635 PAGE 1755 LINE 91142 -:VSQRTPS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VSQRTPS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x51; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vsqrtps_avx512vl( YmmReg2_m256_m32bcst ); @@ -5068,7 +5068,7 @@ define pcodeop vsqrtps_avx512vl ; # SQRTPS 4-635 PAGE 1755 LINE 91145 define pcodeop vsqrtps_avx512f ; -:VSQRTPS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VSQRTPS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x51; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vsqrtps_avx512f( ZmmReg2_m512_m32bcst ); @@ -5076,7 +5076,7 @@ define pcodeop vsqrtps_avx512f ; # SQRTSD 4-638 PAGE 1758 LINE 91276 define pcodeop vsqrtsd_avx512f ; -:VSQRTSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VSQRTSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vsqrtsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -5085,7 +5085,7 @@ define pcodeop vsqrtsd_avx512f ; # SQRTSS 4-640 PAGE 1760 LINE 91371 define pcodeop vsqrtss_avx512f ; -:VSQRTSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VSQRTSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vsqrtss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -5094,7 +5094,7 @@ define pcodeop vsqrtss_avx512f ; # SUBPD 4-656 PAGE 1776 LINE 92120 define pcodeop vsubpd_avx512vl ; -:VSUBPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VSUBPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vsubpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5102,7 +5102,7 @@ define pcodeop vsubpd_avx512vl ; } # SUBPD 4-656 PAGE 1776 LINE 92123 -:VSUBPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VSUBPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vsubpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5111,7 +5111,7 @@ define pcodeop vsubpd_avx512vl ; # SUBPD 4-656 PAGE 1776 LINE 92126 define pcodeop vsubpd_avx512f ; -:VSUBPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5C; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VSUBPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x5C; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vsubpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5119,7 +5119,7 @@ define pcodeop vsubpd_avx512f ; # SUBPS 4-659 PAGE 1779 LINE 92269 define pcodeop vsubps_avx512vl ; -:VSUBPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VSUBPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vsubps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5127,7 +5127,7 @@ define pcodeop vsubps_avx512vl ; } # SUBPS 4-659 PAGE 1779 LINE 92272 -:VSUBPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VSUBPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x5C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vsubps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5136,7 +5136,7 @@ define pcodeop vsubps_avx512vl ; # SUBPS 4-659 PAGE 1779 LINE 92275 define pcodeop vsubps_avx512f ; -:VSUBPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5C; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VSUBPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x5C; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vsubps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5144,7 +5144,7 @@ define pcodeop vsubps_avx512f ; # SUBSD 4-662 PAGE 1782 LINE 92421 define pcodeop vsubsd_avx512f ; -:VSUBSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VSUBSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vsubsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -5153,7 +5153,7 @@ define pcodeop vsubsd_avx512f ; # SUBSS 4-664 PAGE 1784 LINE 92514 define pcodeop vsubss_avx512f ; -:VSUBSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VSUBSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x5C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vsubss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -5182,7 +5182,7 @@ define pcodeop vucomiss_avx512f ; # UNPCKHPD 4-688 PAGE 1808 LINE 93629 define pcodeop vunpckhpd_avx512vl ; -:VUNPCKHPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VUNPCKHPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vunpckhpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5190,7 +5190,7 @@ define pcodeop vunpckhpd_avx512vl ; } # UNPCKHPD 4-688 PAGE 1808 LINE 93632 -:VUNPCKHPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VUNPCKHPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vunpckhpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5199,7 +5199,7 @@ define pcodeop vunpckhpd_avx512vl ; # UNPCKHPD 4-688 PAGE 1808 LINE 93635 define pcodeop vunpckhpd_avx512f ; -:VUNPCKHPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VUNPCKHPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vunpckhpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5207,7 +5207,7 @@ define pcodeop vunpckhpd_avx512f ; # UNPCKHPS 4-692 PAGE 1812 LINE 93813 define pcodeop vunpckhps_avx512vl ; -:VUNPCKHPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VUNPCKHPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vunpckhps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5215,7 +5215,7 @@ define pcodeop vunpckhps_avx512vl ; } # UNPCKHPS 4-692 PAGE 1812 LINE 93817 -:VUNPCKHPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VUNPCKHPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vunpckhps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5224,7 +5224,7 @@ define pcodeop vunpckhps_avx512vl ; # UNPCKHPS 4-692 PAGE 1812 LINE 93821 define pcodeop vunpckhps_avx512f ; -:VUNPCKHPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VUNPCKHPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vunpckhps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5232,7 +5232,7 @@ define pcodeop vunpckhps_avx512f ; # UNPCKLPD 4-696 PAGE 1816 LINE 94045 define pcodeop vunpcklpd_avx512vl ; -:VUNPCKLPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VUNPCKLPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vunpcklpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5240,7 +5240,7 @@ define pcodeop vunpcklpd_avx512vl ; } # UNPCKLPD 4-696 PAGE 1816 LINE 94048 -:VUNPCKLPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VUNPCKLPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vunpcklpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5249,7 +5249,7 @@ define pcodeop vunpcklpd_avx512vl ; # UNPCKLPD 4-696 PAGE 1816 LINE 94051 define pcodeop vunpcklpd_avx512f ; -:VUNPCKLPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VUNPCKLPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vunpcklpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5257,7 +5257,7 @@ define pcodeop vunpcklpd_avx512f ; # UNPCKLPS 4-700 PAGE 1820 LINE 94231 define pcodeop vunpcklps_avx512vl ; -:VUNPCKLPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VUNPCKLPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vunpcklps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5265,7 +5265,7 @@ define pcodeop vunpcklps_avx512vl ; } # UNPCKLPS 4-700 PAGE 1820 LINE 94234 -:VUNPCKLPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VUNPCKLPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vunpcklps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5274,7 +5274,7 @@ define pcodeop vunpcklps_avx512vl ; # UNPCKLPS 4-700 PAGE 1820 LINE 94237 define pcodeop vunpcklps_avx512f ; -:VUNPCKLPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VUNPCKLPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vunpcklps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5282,7 +5282,7 @@ define pcodeop vunpcklps_avx512f ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94615 define pcodeop valignd_avx512vl ; -:VALIGND XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VALIGND XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = valignd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5291,7 +5291,7 @@ define pcodeop valignd_avx512vl ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94619 define pcodeop valignq_avx512vl ; -:VALIGNQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VALIGNQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x03; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = valignq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5299,7 +5299,7 @@ define pcodeop valignq_avx512vl ; } # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94623 -:VALIGND YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VALIGND YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = valignd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5307,7 +5307,7 @@ define pcodeop valignq_avx512vl ; } # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94627 -:VALIGNQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VALIGNQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x03; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = valignq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5316,7 +5316,7 @@ define pcodeop valignq_avx512vl ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94631 define pcodeop valignd_avx512f ; -:VALIGND ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x03; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VALIGND ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x03; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = valignd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5324,7 +5324,7 @@ define pcodeop valignd_avx512f ; # VALIGND/VALIGNQ 5-5 PAGE 1829 LINE 94635 define pcodeop valignq_avx512f ; -:VALIGNQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x03; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VALIGNQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x03; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = valignq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5332,7 +5332,7 @@ define pcodeop valignq_avx512f ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94787 define pcodeop vblendmpd_avx512vl ; -:VBLENDMPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VBLENDMPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vblendmpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -5340,7 +5340,7 @@ define pcodeop vblendmpd_avx512vl ; } # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94790 -:VBLENDMPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VBLENDMPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vblendmpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -5349,7 +5349,7 @@ define pcodeop vblendmpd_avx512vl ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94793 define pcodeop vblendmpd_avx512f ; -:VBLENDMPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x65; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VBLENDMPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x65; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vblendmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -5357,7 +5357,7 @@ define pcodeop vblendmpd_avx512f ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94796 define pcodeop vblendmps_avx512vl ; -:VBLENDMPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VBLENDMPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x65; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vblendmps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -5365,7 +5365,7 @@ define pcodeop vblendmps_avx512vl ; } # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94799 -:VBLENDMPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VBLENDMPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x65; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vblendmps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -5374,7 +5374,7 @@ define pcodeop vblendmps_avx512vl ; # VBLENDMPD/VBLENDMPS 5-9 PAGE 1833 LINE 94802 define pcodeop vblendmps_avx512f ; -:VBLENDMPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x65; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VBLENDMPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x65; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vblendmps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -5382,7 +5382,7 @@ define pcodeop vblendmps_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94917 define pcodeop vbroadcastsd_avx512vl ; -:VBROADCASTSD YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x19; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VBROADCASTSD YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x19; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcastsd_avx512vl( XmmReg2_m64 ); @@ -5391,7 +5391,7 @@ define pcodeop vbroadcastsd_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94920 define pcodeop vbroadcastsd_avx512f ; -:VBROADCASTSD ZmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m64 +:VBROADCASTSD ZmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastsd_avx512f( XmmReg2_m64 ); @@ -5399,7 +5399,7 @@ define pcodeop vbroadcastsd_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94923 define pcodeop vbroadcastf32x2_avx512vl ; -:VBROADCASTF32X2 YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x19; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VBROADCASTF32X2 YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x19; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcastf32x2_avx512vl( XmmReg2_m64 ); @@ -5408,7 +5408,7 @@ define pcodeop vbroadcastf32x2_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94926 define pcodeop vbroadcastf32x2_avx512dq ; -:VBROADCASTF32X2 ZmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m64 +:VBROADCASTF32X2 ZmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastf32x2_avx512dq( XmmReg2_m64 ); @@ -5416,7 +5416,7 @@ define pcodeop vbroadcastf32x2_avx512dq ; # VBROADCAST 5-12 PAGE 1836 LINE 94929 define pcodeop vbroadcastss_avx512vl ; -:VBROADCASTSS XmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x18; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VBROADCASTSS XmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x18; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:16 = vbroadcastss_avx512vl( XmmReg2_m32 ); @@ -5424,7 +5424,7 @@ define pcodeop vbroadcastss_avx512vl ; } # VBROADCAST 5-12 PAGE 1836 LINE 94932 -:VBROADCASTSS YmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VBROADCASTSS YmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcastss_avx512vl( XmmReg2_m32 ); @@ -5433,7 +5433,7 @@ define pcodeop vbroadcastss_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94935 define pcodeop vbroadcastss_avx512f ; -:VBROADCASTSS ZmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x18; ZmmReg1 ... & XmmReg2_m32 +:VBROADCASTSS ZmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x18; ZmmReg1 ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastss_avx512f( XmmReg2_m32 ); @@ -5441,7 +5441,7 @@ define pcodeop vbroadcastss_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94938 define pcodeop vbroadcastf32x4_avx512vl ; -:VBROADCASTF32X4 YmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1A; (YmmReg1 & ZmmReg1) ... & m128 +:VBROADCASTF32X4 YmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1A; (YmmReg1 & ZmmReg1) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcastf32x4_avx512vl( m128 ); @@ -5450,7 +5450,7 @@ define pcodeop vbroadcastf32x4_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94941 define pcodeop vbroadcastf32x4_avx512f ; -:VBROADCASTF32X4 ZmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1A; ZmmReg1 ... & m128 +:VBROADCASTF32X4 ZmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1A; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastf32x4_avx512f( m128 ); @@ -5458,7 +5458,7 @@ define pcodeop vbroadcastf32x4_avx512f ; # VBROADCAST 5-12 PAGE 1836 LINE 94944 define pcodeop vbroadcastf64x2_avx512vl ; -:VBROADCASTF64X2 YmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1A; (YmmReg1 & ZmmReg1) ... & m128 +:VBROADCASTF64X2 YmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1A; (YmmReg1 & ZmmReg1) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcastf64x2_avx512vl( m128 ); @@ -5467,7 +5467,7 @@ define pcodeop vbroadcastf64x2_avx512vl ; # VBROADCAST 5-12 PAGE 1836 LINE 94947 define pcodeop vbroadcastf64x2_avx512dq ; -:VBROADCASTF64X2 ZmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1A; ZmmReg1 ... & m128 +:VBROADCASTF64X2 ZmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1A; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastf64x2_avx512dq( m128 ); @@ -5475,7 +5475,7 @@ define pcodeop vbroadcastf64x2_avx512dq ; # VBROADCAST 5-12 PAGE 1836 LINE 94950 define pcodeop vbroadcastf32x8_avx512dq ; -:VBROADCASTF32X8 ZmmReg1 KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1B; ZmmReg1 ... & m256 +:VBROADCASTF32X8 ZmmReg1^KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x1B; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastf32x8_avx512dq( m256 ); @@ -5483,7 +5483,7 @@ define pcodeop vbroadcastf32x8_avx512dq ; # VBROADCAST 5-12 PAGE 1836 LINE 94953 define pcodeop vbroadcastf64x4_avx512f ; -:VBROADCASTF64X4 ZmmReg1 KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1B; ZmmReg1 ... & m256 +:VBROADCASTF64X4 ZmmReg1^KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x1B; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcastf64x4_avx512f( m256 ); @@ -5535,14 +5535,14 @@ define pcodeop vpbroadcastmw2d_avx512cd ; # VCOMPRESSPD 5-21 PAGE 1845 LINE 95380 define pcodeop vcompresspd_avx512vl ; -:VCOMPRESSPD XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8A; XmmReg1 ... & XmmReg2_m128 +:VCOMPRESSPD XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8A; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmReg2_m128 = vcompresspd_avx512vl( XmmReg1 ); } # VCOMPRESSPD 5-21 PAGE 1845 LINE 95383 -:VCOMPRESSPD YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8A; YmmReg1 ... & YmmReg2_m256 +:VCOMPRESSPD YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8A; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmReg2_m256 = vcompresspd_avx512vl( YmmReg1 ); @@ -5550,7 +5550,7 @@ define pcodeop vcompresspd_avx512vl ; # VCOMPRESSPD 5-21 PAGE 1845 LINE 95386 define pcodeop vcompresspd_avx512f ; -:VCOMPRESSPD ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8A; ZmmReg1 ... & ZmmReg2_m512 +:VCOMPRESSPD ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8A; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg2_m512 = vcompresspd_avx512f( ZmmReg1 ); @@ -5558,14 +5558,14 @@ define pcodeop vcompresspd_avx512f ; # VCOMPRESSPS 5-23 PAGE 1847 LINE 95481 define pcodeop vcompressps_avx512vl ; -:VCOMPRESSPS XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8A; XmmReg1 ... & XmmReg2_m128 +:VCOMPRESSPS XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8A; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmReg2_m128 = vcompressps_avx512vl( XmmReg1 ); } # VCOMPRESSPS 5-23 PAGE 1847 LINE 95484 -:VCOMPRESSPS YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8A; YmmReg1 ... & YmmReg2_m256 +:VCOMPRESSPS YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8A; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmReg2_m256 = vcompressps_avx512vl( YmmReg1 ); @@ -5573,7 +5573,7 @@ define pcodeop vcompressps_avx512vl ; # VCOMPRESSPS 5-23 PAGE 1847 LINE 95487 define pcodeop vcompressps_avx512f ; -:VCOMPRESSPS ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8A; ZmmReg1 ... & ZmmReg2_m512 +:VCOMPRESSPS ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8A; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg2_m512 = vcompressps_avx512f( ZmmReg1 ); @@ -5581,7 +5581,7 @@ define pcodeop vcompressps_avx512f ; # VCVTPD2QQ 5-25 PAGE 1849 LINE 95583 define pcodeop vcvtpd2qq_avx512vl ; -:VCVTPD2QQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTPD2QQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2qq_avx512vl( XmmReg2_m128_m64bcst ); @@ -5589,7 +5589,7 @@ define pcodeop vcvtpd2qq_avx512vl ; } # VCVTPD2QQ 5-25 PAGE 1849 LINE 95586 -:VCVTPD2QQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTPD2QQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7B; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtpd2qq_avx512vl( YmmReg2_m256_m64bcst ); @@ -5598,7 +5598,7 @@ define pcodeop vcvtpd2qq_avx512vl ; # VCVTPD2QQ 5-25 PAGE 1849 LINE 95589 define pcodeop vcvtpd2qq_avx512dq ; -:VCVTPD2QQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7B; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VCVTPD2QQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7B; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtpd2qq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -5606,7 +5606,7 @@ define pcodeop vcvtpd2qq_avx512dq ; # VCVTPD2UDQ 5-28 PAGE 1852 LINE 95706 define pcodeop vcvtpd2udq_avx512vl ; -:VCVTPD2UDQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTPD2UDQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2udq_avx512vl( XmmReg2_m128_m64bcst ); @@ -5614,7 +5614,7 @@ define pcodeop vcvtpd2udq_avx512vl ; } # VCVTPD2UDQ 5-28 PAGE 1852 LINE 95709 -:VCVTPD2UDQ XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTPD2UDQ XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2udq_avx512vl( YmmReg2_m256_m64bcst ); @@ -5623,7 +5623,7 @@ define pcodeop vcvtpd2udq_avx512vl ; # VCVTPD2UDQ 5-28 PAGE 1852 LINE 95712 define pcodeop vcvtpd2udq_avx512f ; -:VCVTPD2UDQ YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTPD2UDQ YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtpd2udq_avx512f( ZmmReg2_m512_m64bcst ); @@ -5632,7 +5632,7 @@ define pcodeop vcvtpd2udq_avx512f ; # VCVTPD2UQQ 5-31 PAGE 1855 LINE 95833 define pcodeop vcvtpd2uqq_avx512vl ; -:VCVTPD2UQQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTPD2UQQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtpd2uqq_avx512vl( XmmReg2_m128_m64bcst ); @@ -5640,7 +5640,7 @@ define pcodeop vcvtpd2uqq_avx512vl ; } # VCVTPD2UQQ 5-31 PAGE 1855 LINE 95836 -:VCVTPD2UQQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTPD2UQQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtpd2uqq_avx512vl( YmmReg2_m256_m64bcst ); @@ -5649,7 +5649,7 @@ define pcodeop vcvtpd2uqq_avx512vl ; # VCVTPD2UQQ 5-31 PAGE 1855 LINE 95839 define pcodeop vcvtpd2uqq_avx512dq ; -:VCVTPD2UQQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VCVTPD2UQQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x79; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtpd2uqq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -5657,7 +5657,7 @@ define pcodeop vcvtpd2uqq_avx512dq ; # VCVTPH2PS 5-34 PAGE 1858 LINE 95963 define pcodeop vcvtph2ps_avx512vl ; -:VCVTPH2PS XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VCVTPH2PS XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { local tmp:16 = vcvtph2ps_avx512vl( XmmReg2_m64 ); @@ -5665,7 +5665,7 @@ define pcodeop vcvtph2ps_avx512vl ; } # VCVTPH2PS 5-34 PAGE 1858 LINE 95966 -:VCVTPH2PS YmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VCVTPH2PS YmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { local tmp:32 = vcvtph2ps_avx512vl( XmmReg2_m128 ); @@ -5674,7 +5674,7 @@ define pcodeop vcvtph2ps_avx512vl ; # VCVTPH2PS 5-34 PAGE 1858 LINE 95969 define pcodeop vcvtph2ps_avx512f ; -:VCVTPH2PS ZmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; ZmmReg1 ... & YmmReg2_m256 +:VCVTPH2PS ZmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; ZmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { ZmmReg1 = vcvtph2ps_avx512f( YmmReg2_m256 ); @@ -5691,7 +5691,7 @@ define pcodeop vcvtph2ps_avx512f ; # VCVTPS2UDQ 5-41 PAGE 1865 LINE 96305 define pcodeop vcvtps2udq_avx512vl ; -:VCVTPS2UDQ XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTPS2UDQ XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtps2udq_avx512vl( XmmReg2_m128_m32bcst ); @@ -5699,7 +5699,7 @@ define pcodeop vcvtps2udq_avx512vl ; } # VCVTPS2UDQ 5-41 PAGE 1865 LINE 96309 -:VCVTPS2UDQ YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VCVTPS2UDQ YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtps2udq_avx512vl( YmmReg2_m256_m32bcst ); @@ -5708,7 +5708,7 @@ define pcodeop vcvtps2udq_avx512vl ; # VCVTPS2UDQ 5-41 PAGE 1865 LINE 96313 define pcodeop vcvtps2udq_avx512f ; -:VCVTPS2UDQ ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VCVTPS2UDQ ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtps2udq_avx512f( ZmmReg2_m512_m32bcst ); @@ -5716,7 +5716,7 @@ define pcodeop vcvtps2udq_avx512f ; # VCVTPS2QQ 5-44 PAGE 1868 LINE 96434 define pcodeop vcvtps2qq_avx512vl ; -:VCVTPS2QQ XmmReg1 KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst +:VCVTPS2QQ XmmReg1^KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvtps2qq_avx512vl( XmmReg2_m64_m32bcst ); @@ -5724,7 +5724,7 @@ define pcodeop vcvtps2qq_avx512vl ; } # VCVTPS2QQ 5-44 PAGE 1868 LINE 96437 -:VCVTPS2QQ YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTPS2QQ YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7B; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvtps2qq_avx512vl( XmmReg2_m128_m32bcst ); @@ -5733,7 +5733,7 @@ define pcodeop vcvtps2qq_avx512vl ; # VCVTPS2QQ 5-44 PAGE 1868 LINE 96440 define pcodeop vcvtps2qq_avx512dq ; -:VCVTPS2QQ ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7B; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTPS2QQ ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7B; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvtps2qq_avx512dq( YmmReg2_m256_m32bcst ); @@ -5741,7 +5741,7 @@ define pcodeop vcvtps2qq_avx512dq ; # VCVTPS2UQQ 5-47 PAGE 1871 LINE 96560 define pcodeop vcvtps2uqq_avx512vl ; -:VCVTPS2UQQ XmmReg1 KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst +:VCVTPS2UQQ XmmReg1^KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvtps2uqq_avx512vl( XmmReg2_m64_m32bcst ); @@ -5749,7 +5749,7 @@ define pcodeop vcvtps2uqq_avx512vl ; } # VCVTPS2UQQ 5-47 PAGE 1871 LINE 96563 -:VCVTPS2UQQ YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTPS2UQQ YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvtps2uqq_avx512vl( XmmReg2_m128_m32bcst ); @@ -5758,7 +5758,7 @@ define pcodeop vcvtps2uqq_avx512vl ; # VCVTPS2UQQ 5-47 PAGE 1871 LINE 96566 define pcodeop vcvtps2uqq_avx512dq ; -:VCVTPS2UQQ ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTPS2UQQ ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x79; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvtps2uqq_avx512dq( YmmReg2_m256_m32bcst ); @@ -5766,7 +5766,7 @@ define pcodeop vcvtps2uqq_avx512dq ; # VCVTQQ2PD 5-50 PAGE 1874 LINE 96686 define pcodeop vcvtqq2pd_avx512vl ; -:VCVTQQ2PD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTQQ2PD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtqq2pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -5774,7 +5774,7 @@ define pcodeop vcvtqq2pd_avx512vl ; } # VCVTQQ2PD 5-50 PAGE 1874 LINE 96689 -:VCVTQQ2PD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTQQ2PD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtqq2pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -5783,7 +5783,7 @@ define pcodeop vcvtqq2pd_avx512vl ; # VCVTQQ2PD 5-50 PAGE 1874 LINE 96692 define pcodeop vcvtqq2pd_avx512dq ; -:VCVTQQ2PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VCVTQQ2PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0xE6; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtqq2pd_avx512dq( ZmmReg2_m512_m64bcst ); @@ -5791,7 +5791,7 @@ define pcodeop vcvtqq2pd_avx512dq ; # VCVTQQ2PS 5-52 PAGE 1876 LINE 96797 define pcodeop vcvtqq2ps_avx512vl ; -:VCVTQQ2PS XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTQQ2PS XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtqq2ps_avx512vl( XmmReg2_m128_m64bcst ); @@ -5799,7 +5799,7 @@ define pcodeop vcvtqq2ps_avx512vl ; } # VCVTQQ2PS 5-52 PAGE 1876 LINE 96800 -:VCVTQQ2PS XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTQQ2PS XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5B; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtqq2ps_avx512vl( YmmReg2_m256_m64bcst ); @@ -5808,7 +5808,7 @@ define pcodeop vcvtqq2ps_avx512vl ; # VCVTQQ2PS 5-52 PAGE 1876 LINE 96803 define pcodeop vcvtqq2ps_avx512dq ; -:VCVTQQ2PS YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTQQ2PS YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x5B; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtqq2ps_avx512dq( ZmmReg2_m512_m64bcst ); @@ -5853,7 +5853,7 @@ define pcodeop vcvtss2usi_avx512f ; # VCVTTPD2QQ 5-57 PAGE 1881 LINE 97040 define pcodeop vcvttpd2qq_avx512vl ; -:VCVTTPD2QQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTTPD2QQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttpd2qq_avx512vl( XmmReg2_m128_m64bcst ); @@ -5861,7 +5861,7 @@ define pcodeop vcvttpd2qq_avx512vl ; } # VCVTTPD2QQ 5-57 PAGE 1881 LINE 97043 -:VCVTTPD2QQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTTPD2QQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvttpd2qq_avx512vl( YmmReg2_m256_m64bcst ); @@ -5870,7 +5870,7 @@ define pcodeop vcvttpd2qq_avx512vl ; # VCVTTPD2QQ 5-57 PAGE 1881 LINE 97046 define pcodeop vcvttpd2qq_avx512dq ; -:VCVTTPD2QQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VCVTTPD2QQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvttpd2qq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -5878,7 +5878,7 @@ define pcodeop vcvttpd2qq_avx512dq ; # VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97147 define pcodeop vcvttpd2udq_avx512vl ; -:VCVTTPD2UDQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTTPD2UDQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttpd2udq_avx512vl( XmmReg2_m128_m64bcst ); @@ -5886,7 +5886,7 @@ define pcodeop vcvttpd2udq_avx512vl ; } # VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97152 -:VCVTTPD2UDQ XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTTPD2UDQ XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttpd2udq_avx512vl( YmmReg2_m256_m64bcst ); @@ -5895,7 +5895,7 @@ define pcodeop vcvttpd2udq_avx512vl ; # VCVTTPD2UDQ 5-59 PAGE 1883 LINE 97156 define pcodeop vcvttpd2udq_avx512f ; -:VCVTTPD2UDQ YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTTPD2UDQ YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvttpd2udq_avx512f( ZmmReg2_m512_m64bcst ); @@ -5904,7 +5904,7 @@ define pcodeop vcvttpd2udq_avx512f ; # VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97272 define pcodeop vcvttpd2uqq_avx512vl ; -:VCVTTPD2UQQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTTPD2UQQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttpd2uqq_avx512vl( XmmReg2_m128_m64bcst ); @@ -5912,7 +5912,7 @@ define pcodeop vcvttpd2uqq_avx512vl ; } # VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97276 -:VCVTTPD2UQQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTTPD2UQQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvttpd2uqq_avx512vl( YmmReg2_m256_m64bcst ); @@ -5921,7 +5921,7 @@ define pcodeop vcvttpd2uqq_avx512vl ; # VCVTTPD2UQQ 5-62 PAGE 1886 LINE 97280 define pcodeop vcvttpd2uqq_avx512dq ; -:VCVTTPD2UQQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VCVTTPD2UQQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x78; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvttpd2uqq_avx512dq( ZmmReg2_m512_m64bcst ); @@ -5929,7 +5929,7 @@ define pcodeop vcvttpd2uqq_avx512dq ; # VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97385 define pcodeop vcvttps2udq_avx512vl ; -:VCVTTPS2UDQ XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTTPS2UDQ XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvttps2udq_avx512vl( XmmReg2_m128_m32bcst ); @@ -5937,7 +5937,7 @@ define pcodeop vcvttps2udq_avx512vl ; } # VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97389 -:VCVTTPS2UDQ YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VCVTTPS2UDQ YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvttps2udq_avx512vl( YmmReg2_m256_m32bcst ); @@ -5946,7 +5946,7 @@ define pcodeop vcvttps2udq_avx512vl ; # VCVTTPS2UDQ 5-64 PAGE 1888 LINE 97393 define pcodeop vcvttps2udq_avx512f ; -:VCVTTPS2UDQ ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VCVTTPS2UDQ ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvttps2udq_avx512f( ZmmReg2_m512_m32bcst ); @@ -5954,7 +5954,7 @@ define pcodeop vcvttps2udq_avx512f ; # VCVTTPS2QQ 5-66 PAGE 1890 LINE 97497 define pcodeop vcvttps2qq_avx512vl ; -:VCVTTPS2QQ XmmReg1 KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst +:VCVTTPS2QQ XmmReg1^KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvttps2qq_avx512vl( XmmReg2_m64_m32bcst ); @@ -5962,7 +5962,7 @@ define pcodeop vcvttps2qq_avx512vl ; } # VCVTTPS2QQ 5-66 PAGE 1890 LINE 97500 -:VCVTTPS2QQ YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTTPS2QQ YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvttps2qq_avx512vl( XmmReg2_m128_m32bcst ); @@ -5971,7 +5971,7 @@ define pcodeop vcvttps2qq_avx512vl ; # VCVTTPS2QQ 5-66 PAGE 1890 LINE 97503 define pcodeop vcvttps2qq_avx512dq ; -:VCVTTPS2QQ ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTTPS2QQ ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvttps2qq_avx512dq( YmmReg2_m256_m32bcst ); @@ -5979,7 +5979,7 @@ define pcodeop vcvttps2qq_avx512dq ; # VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97608 define pcodeop vcvttps2uqq_avx512vl ; -:VCVTTPS2UQQ XmmReg1 KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst +:VCVTTPS2UQQ XmmReg1^KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvttps2uqq_avx512vl( XmmReg2_m64_m32bcst ); @@ -5987,7 +5987,7 @@ define pcodeop vcvttps2uqq_avx512vl ; } # VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97611 -:VCVTTPS2UQQ YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTTPS2UQQ YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvttps2uqq_avx512vl( XmmReg2_m128_m32bcst ); @@ -5996,7 +5996,7 @@ define pcodeop vcvttps2uqq_avx512vl ; # VCVTTPS2UQQ 5-68 PAGE 1892 LINE 97615 define pcodeop vcvttps2uqq_avx512dq ; -:VCVTTPS2UQQ ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTTPS2UQQ ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x78; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvttps2uqq_avx512dq( YmmReg2_m256_m32bcst ); @@ -6040,7 +6040,7 @@ define pcodeop vcvttss2usi_avx512f ; # VCVTUDQ2PD 5-73 PAGE 1897 LINE 97852 define pcodeop vcvtudq2pd_avx512vl ; -:VCVTUDQ2PD XmmReg1 KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst +:VCVTUDQ2PD XmmReg1^KWriteMask, XmmReg2_m64_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:16 = vcvtudq2pd_avx512vl( XmmReg2_m64_m32bcst ); @@ -6048,7 +6048,7 @@ define pcodeop vcvtudq2pd_avx512vl ; } # VCVTUDQ2PD 5-73 PAGE 1897 LINE 97855 -:VCVTUDQ2PD YmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTUDQ2PD YmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { local tmp:32 = vcvtudq2pd_avx512vl( XmmReg2_m128_m32bcst ); @@ -6057,7 +6057,7 @@ define pcodeop vcvtudq2pd_avx512vl ; # VCVTUDQ2PD 5-73 PAGE 1897 LINE 97859 define pcodeop vcvtudq2pd_avx512f ; -:VCVTUDQ2PD ZmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; ZmmReg1 ... & YmmReg2_m256_m32bcst +:VCVTUDQ2PD ZmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; ZmmReg1 ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 1; ] # (TupleType HV) { ZmmReg1 = vcvtudq2pd_avx512f( YmmReg2_m256_m32bcst ); @@ -6065,7 +6065,7 @@ define pcodeop vcvtudq2pd_avx512f ; # VCVTUDQ2PS 5-75 PAGE 1899 LINE 97962 define pcodeop vcvtudq2ps_avx512vl ; -:VCVTUDQ2PS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VCVTUDQ2PS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtudq2ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -6073,7 +6073,7 @@ define pcodeop vcvtudq2ps_avx512vl ; } # VCVTUDQ2PS 5-75 PAGE 1899 LINE 97965 -:VCVTUDQ2PS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VCVTUDQ2PS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtudq2ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -6082,7 +6082,7 @@ define pcodeop vcvtudq2ps_avx512vl ; # VCVTUDQ2PS 5-75 PAGE 1899 LINE 97968 define pcodeop vcvtudq2ps_avx512f ; -:VCVTUDQ2PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VCVTUDQ2PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W0) & KWriteMask; byte=0x7A; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtudq2ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -6090,7 +6090,7 @@ define pcodeop vcvtudq2ps_avx512f ; # VCVTUQQ2PD 5-77 PAGE 1901 LINE 98078 define pcodeop vcvtuqq2pd_avx512vl ; -:VCVTUQQ2PD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTUQQ2PD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtuqq2pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -6098,7 +6098,7 @@ define pcodeop vcvtuqq2pd_avx512vl ; } # VCVTUQQ2PD 5-77 PAGE 1901 LINE 98081 -:VCVTUQQ2PD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTUQQ2PD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtuqq2pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -6107,7 +6107,7 @@ define pcodeop vcvtuqq2pd_avx512vl ; # VCVTUQQ2PD 5-77 PAGE 1901 LINE 98084 define pcodeop vcvtuqq2pd_avx512dq ; -:VCVTUQQ2PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VCVTUQQ2PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vcvtuqq2pd_avx512dq( ZmmReg2_m512_m64bcst ); @@ -6115,7 +6115,7 @@ define pcodeop vcvtuqq2pd_avx512dq ; # VCVTUQQ2PS 5-79 PAGE 1903 LINE 98193 define pcodeop vcvtuqq2ps_avx512vl ; -:VCVTUQQ2PS XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VCVTUQQ2PS XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtuqq2ps_avx512vl( XmmReg2_m128_m64bcst ); @@ -6123,7 +6123,7 @@ define pcodeop vcvtuqq2ps_avx512vl ; } # VCVTUQQ2PS 5-79 PAGE 1903 LINE 98196 -:VCVTUQQ2PS XmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VCVTUQQ2PS XmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (XmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vcvtuqq2ps_avx512vl( YmmReg2_m256_m64bcst ); @@ -6132,7 +6132,7 @@ define pcodeop vcvtuqq2ps_avx512vl ; # VCVTUQQ2PS 5-79 PAGE 1903 LINE 98199 define pcodeop vcvtuqq2ps_avx512dq ; -:VCVTUQQ2PS YmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst +:VCVTUQQ2PS YmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_W1) & KWriteMask; byte=0x7A; (YmmReg1 & ZmmReg1) ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vcvtuqq2ps_avx512dq( ZmmReg2_m512_m64bcst ); @@ -6179,7 +6179,7 @@ define pcodeop vcvtusi2ss_avx512f ; # VDBPSADBW 5-85 PAGE 1909 LINE 98455 define pcodeop vdbpsadbw_avx512vl ; -:VDBPSADBW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VDBPSADBW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vdbpsadbw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128, imm8:1 ); @@ -6187,7 +6187,7 @@ define pcodeop vdbpsadbw_avx512vl ; } # VDBPSADBW 5-85 PAGE 1909 LINE 98460 -:VDBPSADBW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 +:VDBPSADBW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vdbpsadbw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256, imm8:1 ); @@ -6196,7 +6196,7 @@ define pcodeop vdbpsadbw_avx512vl ; # VDBPSADBW 5-85 PAGE 1909 LINE 98465 define pcodeop vdbpsadbw_avx512bw ; -:VDBPSADBW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x42; ZmmReg1 ... & ZmmReg2_m512; imm8 +:VDBPSADBW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x42; ZmmReg1 ... & ZmmReg2_m512; imm8 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vdbpsadbw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512, imm8:1 ); @@ -6204,7 +6204,7 @@ define pcodeop vdbpsadbw_avx512bw ; # VEXPANDPD 5-89 PAGE 1913 LINE 98660 define pcodeop vexpandpd_avx512vl ; -:VEXPANDPD XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x88; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VEXPANDPD XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x88; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vexpandpd_avx512vl( XmmReg2_m128 ); @@ -6212,7 +6212,7 @@ define pcodeop vexpandpd_avx512vl ; } # VEXPANDPD 5-89 PAGE 1913 LINE 98663 -:VEXPANDPD YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x88; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VEXPANDPD YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x88; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vexpandpd_avx512vl( YmmReg2_m256 ); @@ -6221,7 +6221,7 @@ define pcodeop vexpandpd_avx512vl ; # VEXPANDPD 5-89 PAGE 1913 LINE 98665 define pcodeop vexpandpd_avx512f ; -:VEXPANDPD ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x88; ZmmReg1 ... & ZmmReg2_m512 +:VEXPANDPD ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x88; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vexpandpd_avx512f( ZmmReg2_m512 ); @@ -6229,7 +6229,7 @@ define pcodeop vexpandpd_avx512f ; # VEXPANDPS 5-91 PAGE 1915 LINE 98748 define pcodeop vexpandps_avx512vl ; -:VEXPANDPS XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x88; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VEXPANDPS XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x88; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vexpandps_avx512vl( XmmReg2_m128 ); @@ -6237,7 +6237,7 @@ define pcodeop vexpandps_avx512vl ; } # VEXPANDPS 5-91 PAGE 1915 LINE 98750 -:VEXPANDPS YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x88; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VEXPANDPS YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x88; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vexpandps_avx512vl( YmmReg2_m256 ); @@ -6246,7 +6246,7 @@ define pcodeop vexpandps_avx512vl ; # VEXPANDPS 5-91 PAGE 1915 LINE 98752 define pcodeop vexpandps_avx512f ; -:VEXPANDPS ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x88; ZmmReg1 ... & ZmmReg2_m512 +:VEXPANDPS ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x88; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vexpandps_avx512f( ZmmReg2_m512 ); @@ -6254,7 +6254,7 @@ define pcodeop vexpandps_avx512f ; # VEXP2PD 5-95 PAGE 1919 LINE 98936 define pcodeop vexp2pd_avx512er ; -:VEXP2PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC8; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VEXP2PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC8; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vexp2pd_avx512er( ZmmReg1, ZmmReg2_m512_m64bcst ); @@ -6262,7 +6262,7 @@ define pcodeop vexp2pd_avx512er ; # VEXP2PS 5-97 PAGE 1921 LINE 99019 define pcodeop vexp2ps_avx512er ; -:VEXP2PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC8; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VEXP2PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC8; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vexp2ps_avx512er( ZmmReg1, ZmmReg2_m512_m32bcst ); @@ -6270,7 +6270,7 @@ define pcodeop vexp2ps_avx512er ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99105 define pcodeop vextractf32x4_avx512vl ; -:VEXTRACTF32X4 XmmReg2_m128 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x19; YmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTF32X4 XmmReg2_m128^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x19; YmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextractf32x4_avx512vl( YmmReg1, imm8:1 ); @@ -6278,7 +6278,7 @@ define pcodeop vextractf32x4_avx512vl ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99108 define pcodeop vextractf32x4_avx512f ; -:VEXTRACTF32x4 XmmReg2_m128 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTF32x4 XmmReg2_m128^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextractf32x4_avx512f( ZmmReg1, imm8:1 ); @@ -6286,7 +6286,7 @@ define pcodeop vextractf32x4_avx512f ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99111 define pcodeop vextractf64x2_avx512vl ; -:VEXTRACTF64X2 XmmReg2_m128 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x19; YmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTF64X2 XmmReg2_m128^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x19; YmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextractf64x2_avx512vl( YmmReg1, imm8:1 ); @@ -6294,7 +6294,7 @@ define pcodeop vextractf64x2_avx512vl ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99114 define pcodeop vextractf64x2_avx512dq ; -:VEXTRACTF64X2 XmmReg2_m128 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTF64X2 XmmReg2_m128^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x19; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextractf64x2_avx512dq( ZmmReg1, imm8:1 ); @@ -6302,7 +6302,7 @@ define pcodeop vextractf64x2_avx512dq ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99117 define pcodeop vextractf32x8_avx512dq ; -:VEXTRACTF32X8 YmmReg2_m256 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1B; ZmmReg1 ... & YmmReg2_m256; imm8 +:VEXTRACTF32X8 YmmReg2_m256^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1B; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmReg2_m256 = vextractf32x8_avx512dq( ZmmReg1, imm8:1 ); @@ -6310,7 +6310,7 @@ define pcodeop vextractf32x8_avx512dq ; # VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4 5-99 PAGE 1923 LINE 99120 define pcodeop vextractf64x4_avx512f ; -:VEXTRACTF64x4 YmmReg2_m256 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x1B; ZmmReg1 ... & YmmReg2_m256; imm8 +:VEXTRACTF64x4 YmmReg2_m256^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x1B; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmReg2_m256 = vextractf64x4_avx512f( ZmmReg1, imm8:1 ); @@ -6318,7 +6318,7 @@ define pcodeop vextractf64x4_avx512f ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99435 define pcodeop vextracti32x4_avx512vl ; -:VEXTRACTI32X4 XmmReg2_m128 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x39; YmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTI32X4 XmmReg2_m128^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x39; YmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextracti32x4_avx512vl( YmmReg1, imm8:1 ); @@ -6326,7 +6326,7 @@ define pcodeop vextracti32x4_avx512vl ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99438 define pcodeop vextracti32x4_avx512f ; -:VEXTRACTI32x4 XmmReg2_m128 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x39; ZmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTI32x4 XmmReg2_m128^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x39; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextracti32x4_avx512f( ZmmReg1, imm8:1 ); @@ -6334,7 +6334,7 @@ define pcodeop vextracti32x4_avx512f ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99441 define pcodeop vextracti64x2_avx512vl ; -:VEXTRACTI64X2 XmmReg2_m128 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x39; YmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTI64X2 XmmReg2_m128^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x39; YmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextracti64x2_avx512vl( YmmReg1, imm8:1 ); @@ -6342,7 +6342,7 @@ define pcodeop vextracti64x2_avx512vl ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99444 define pcodeop vextracti64x2_avx512dq ; -:VEXTRACTI64X2 XmmReg2_m128 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x39; ZmmReg1 ... & XmmReg2_m128; imm8 +:VEXTRACTI64X2 XmmReg2_m128^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x39; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { XmmReg2_m128 = vextracti64x2_avx512dq( ZmmReg1, imm8:1 ); @@ -6350,7 +6350,7 @@ define pcodeop vextracti64x2_avx512dq ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99447 define pcodeop vextracti32x8_avx512dq ; -:VEXTRACTI32X8 YmmReg2_m256 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x3B; ZmmReg1 ... & YmmReg2_m256; imm8 +:VEXTRACTI32X8 YmmReg2_m256^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x3B; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmReg2_m256 = vextracti32x8_avx512dq( ZmmReg1, imm8:1 ); @@ -6358,7 +6358,7 @@ define pcodeop vextracti32x8_avx512dq ; # VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4 5-106 PAGE 1930 LINE 99450 define pcodeop vextracti64x4_avx512f ; -:VEXTRACTI64x4 YmmReg2_m256 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x3B; ZmmReg1 ... & YmmReg2_m256; imm8 +:VEXTRACTI64x4 YmmReg2_m256^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x3B; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { YmmReg2_m256 = vextracti64x4_avx512f( ZmmReg1, imm8:1 ); @@ -6366,7 +6366,7 @@ define pcodeop vextracti64x4_avx512f ; # VFIXUPIMMPD 5-112 PAGE 1936 LINE 99754 define pcodeop vfixupimmpd_avx512vl ; -:VFIXUPIMMPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VFIXUPIMMPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfixupimmpd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -6374,7 +6374,7 @@ define pcodeop vfixupimmpd_avx512vl ; } # VFIXUPIMMPD 5-112 PAGE 1936 LINE 99757 -:VFIXUPIMMPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VFIXUPIMMPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfixupimmpd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -6383,7 +6383,7 @@ define pcodeop vfixupimmpd_avx512vl ; # VFIXUPIMMPD 5-112 PAGE 1936 LINE 99760 define pcodeop vfixupimmpd_avx512f ; -:VFIXUPIMMPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VFIXUPIMMPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfixupimmpd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -6391,7 +6391,7 @@ define pcodeop vfixupimmpd_avx512f ; # VFIXUPIMMPS 5-116 PAGE 1940 LINE 99957 define pcodeop vfixupimmps_avx512vl ; -:VFIXUPIMMPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VFIXUPIMMPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x54; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfixupimmps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -6399,7 +6399,7 @@ define pcodeop vfixupimmps_avx512vl ; } # VFIXUPIMMPS 5-116 PAGE 1940 LINE 99960 -:VFIXUPIMMPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VFIXUPIMMPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x54; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfixupimmps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -6408,7 +6408,7 @@ define pcodeop vfixupimmps_avx512vl ; # VFIXUPIMMPS 5-116 PAGE 1940 LINE 99963 define pcodeop vfixupimmps_avx512f ; -:VFIXUPIMMPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VFIXUPIMMPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x54; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfixupimmps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -6416,7 +6416,7 @@ define pcodeop vfixupimmps_avx512f ; # VFIXUPIMMSD 5-120 PAGE 1944 LINE 100159 define pcodeop vfixupimmsd_avx512f ; -:VFIXUPIMMSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8 +:VFIXUPIMMSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfixupimmsd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); @@ -6425,7 +6425,7 @@ define pcodeop vfixupimmsd_avx512f ; # VFIXUPIMMSS 5-123 PAGE 1947 LINE 100331 define pcodeop vfixupimmss_avx512f ; -:VFIXUPIMMSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8 +:VFIXUPIMMSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x55; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfixupimmss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32, imm8:1 ); @@ -6434,7 +6434,7 @@ define pcodeop vfixupimmss_avx512f ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100523 define pcodeop vfmadd132pd_avx512vl ; -:VFMADD132PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMADD132PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst { local tmp:16 = vfmadd132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); ZmmReg1 = zext(tmp); @@ -6442,7 +6442,7 @@ define pcodeop vfmadd132pd_avx512vl ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100526 define pcodeop vfmadd213pd_avx512vl ; -:VFMADD213PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMADD213PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmadd213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6451,7 +6451,7 @@ define pcodeop vfmadd213pd_avx512vl ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100529 define pcodeop vfmadd231pd_avx512vl ; -:VFMADD231PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMADD231PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmadd231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6459,7 +6459,7 @@ define pcodeop vfmadd231pd_avx512vl ; } # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100532 -:VFMADD132PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMADD132PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmadd132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6467,7 +6467,7 @@ define pcodeop vfmadd231pd_avx512vl ; } # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100535 -:VFMADD213PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMADD213PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmadd213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6475,7 +6475,7 @@ define pcodeop vfmadd231pd_avx512vl ; } # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100538 -:VFMADD231PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMADD231PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmadd231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6484,7 +6484,7 @@ define pcodeop vfmadd231pd_avx512vl ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100541 define pcodeop vfmadd132pd_avx512f ; -:VFMADD132PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x98; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMADD132PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x98; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6492,7 +6492,7 @@ define pcodeop vfmadd132pd_avx512f ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100544 define pcodeop vfmadd213pd_avx512f ; -:VFMADD213PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xA8; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMADD213PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xA8; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6500,7 +6500,7 @@ define pcodeop vfmadd213pd_avx512f ; # VFMADD132PD/VFMADD213PD/VFMADD231PD 5-126 PAGE 1950 LINE 100547 define pcodeop vfmadd231pd_avx512f ; -:VFMADD231PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xB8; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMADD231PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xB8; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6508,7 +6508,7 @@ define pcodeop vfmadd231pd_avx512f ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100884 define pcodeop vfmadd132ps_avx512vl ; -:VFMADD132PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMADD132PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x98; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmadd132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6517,7 +6517,7 @@ define pcodeop vfmadd132ps_avx512vl ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100887 define pcodeop vfmadd213ps_avx512vl ; -:VFMADD213PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMADD213PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmadd213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6526,7 +6526,7 @@ define pcodeop vfmadd213ps_avx512vl ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100890 define pcodeop vfmadd231ps_avx512vl ; -:VFMADD231PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMADD231PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB8; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmadd231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6534,7 +6534,7 @@ define pcodeop vfmadd231ps_avx512vl ; } # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100893 -:VFMADD132PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMADD132PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x98; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmadd132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6542,7 +6542,7 @@ define pcodeop vfmadd231ps_avx512vl ; } # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100896 -:VFMADD213PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMADD213PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xA8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmadd213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6550,7 +6550,7 @@ define pcodeop vfmadd231ps_avx512vl ; } # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100899 -:VFMADD231PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMADD231PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xB8; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmadd231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6559,7 +6559,7 @@ define pcodeop vfmadd231ps_avx512vl ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100902 define pcodeop vfmadd132ps_avx512f ; -:VFMADD132PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x98; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMADD132PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x98; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6567,7 +6567,7 @@ define pcodeop vfmadd132ps_avx512f ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100905 define pcodeop vfmadd213ps_avx512f ; -:VFMADD213PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xA8; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMADD213PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xA8; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6575,7 +6575,7 @@ define pcodeop vfmadd213ps_avx512f ; # VFMADD132PS/VFMADD213PS/VFMADD231PS 5-133 PAGE 1957 LINE 100908 define pcodeop vfmadd231ps_avx512f ; -:VFMADD231PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xB8; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMADD231PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xB8; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6583,7 +6583,7 @@ define pcodeop vfmadd231ps_avx512f ; # VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101235 define pcodeop vfmadd132sd_avx512f ; -:VFMADD132SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMADD132SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmadd132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -6592,7 +6592,7 @@ define pcodeop vfmadd132sd_avx512f ; # VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101238 define pcodeop vfmadd213sd_avx512f ; -:VFMADD213SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMADD213SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmadd213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -6601,7 +6601,7 @@ define pcodeop vfmadd213sd_avx512f ; # VFMADD132SD/VFMADD213SD/VFMADD231SD 5-140 PAGE 1964 LINE 101241 define pcodeop vfmadd231sd_avx512f ; -:VFMADD231SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMADD231SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmadd231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -6610,7 +6610,7 @@ define pcodeop vfmadd231sd_avx512f ; # VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101403 define pcodeop vfmadd132ss_avx512f ; -:VFMADD132SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMADD132SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x99; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmadd132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -6619,7 +6619,7 @@ define pcodeop vfmadd132ss_avx512f ; # VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101406 define pcodeop vfmadd213ss_avx512f ; -:VFMADD213SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMADD213SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmadd213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -6628,7 +6628,7 @@ define pcodeop vfmadd213ss_avx512f ; # VFMADD132SS/VFMADD213SS/VFMADD231SS 5-143 PAGE 1967 LINE 101409 define pcodeop vfmadd231ss_avx512f ; -:VFMADD231SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMADD231SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB9; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmadd231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -6637,7 +6637,7 @@ define pcodeop vfmadd231ss_avx512f ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101585 define pcodeop vfmaddsub213pd_avx512vl ; -:VFMADDSUB213PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMADDSUB213PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmaddsub213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6646,7 +6646,7 @@ define pcodeop vfmaddsub213pd_avx512vl ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101589 define pcodeop vfmaddsub231pd_avx512vl ; -:VFMADDSUB231PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMADDSUB231PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmaddsub231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6655,7 +6655,7 @@ define pcodeop vfmaddsub231pd_avx512vl ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101593 define pcodeop vfmaddsub132pd_avx512vl ; -:VFMADDSUB132PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMADDSUB132PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmaddsub132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6663,7 +6663,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; } # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101597 -:VFMADDSUB213PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMADDSUB213PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmaddsub213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6671,7 +6671,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; } # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101601 -:VFMADDSUB231PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMADDSUB231PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmaddsub231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6679,7 +6679,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; } # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-146 PAGE 1970 LINE 101605 -:VFMADDSUB132PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMADDSUB132PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmaddsub132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6688,7 +6688,7 @@ define pcodeop vfmaddsub132pd_avx512vl ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101621 define pcodeop vfmaddsub213pd_avx512f ; -:VFMADDSUB213PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xA6; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMADDSUB213PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xA6; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmaddsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6696,7 +6696,7 @@ define pcodeop vfmaddsub213pd_avx512f ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101625 define pcodeop vfmaddsub231pd_avx512f ; -:VFMADDSUB231PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xB6; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMADDSUB231PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xB6; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmaddsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6704,7 +6704,7 @@ define pcodeop vfmaddsub231pd_avx512f ; # VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD 5-147 PAGE 1971 LINE 101629 define pcodeop vfmaddsub132pd_avx512f ; -:VFMADDSUB132PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x96; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMADDSUB132PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x96; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmaddsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6712,7 +6712,7 @@ define pcodeop vfmaddsub132pd_avx512f ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102024 define pcodeop vfmaddsub213ps_avx512vl ; -:VFMADDSUB213PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMADDSUB213PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmaddsub213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6721,7 +6721,7 @@ define pcodeop vfmaddsub213ps_avx512vl ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102028 define pcodeop vfmaddsub231ps_avx512vl ; -:VFMADDSUB231PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMADDSUB231PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB6; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmaddsub231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6730,7 +6730,7 @@ define pcodeop vfmaddsub231ps_avx512vl ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102031 define pcodeop vfmaddsub132ps_avx512vl ; -:VFMADDSUB132PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMADDSUB132PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x96; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmaddsub132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6738,7 +6738,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; } # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102034 -:VFMADDSUB213PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMADDSUB213PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xA6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmaddsub213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6746,7 +6746,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; } # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102038 -:VFMADDSUB231PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMADDSUB231PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xB6; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmaddsub231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6754,7 +6754,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; } # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102041 -:VFMADDSUB132PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMADDSUB132PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x96; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmaddsub132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6763,7 +6763,7 @@ define pcodeop vfmaddsub132ps_avx512vl ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102044 define pcodeop vfmaddsub213ps_avx512f ; -:VFMADDSUB213PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xA6; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMADDSUB213PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xA6; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmaddsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6771,7 +6771,7 @@ define pcodeop vfmaddsub213ps_avx512f ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102048 define pcodeop vfmaddsub231ps_avx512f ; -:VFMADDSUB231PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xB6; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMADDSUB231PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xB6; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmaddsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6779,7 +6779,7 @@ define pcodeop vfmaddsub231ps_avx512f ; # VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS 5-156 PAGE 1980 LINE 102051 define pcodeop vfmaddsub132ps_avx512f ; -:VFMADDSUB132PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x96; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMADDSUB132PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x96; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmaddsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6787,7 +6787,7 @@ define pcodeop vfmaddsub132ps_avx512f ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102454 define pcodeop vfmsubadd132pd_avx512vl ; -:VFMSUBADD132PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMSUBADD132PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsubadd132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6796,7 +6796,7 @@ define pcodeop vfmsubadd132pd_avx512vl ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102458 define pcodeop vfmsubadd213pd_avx512vl ; -:VFMSUBADD213PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMSUBADD213PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsubadd213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6805,7 +6805,7 @@ define pcodeop vfmsubadd213pd_avx512vl ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102462 define pcodeop vfmsubadd231pd_avx512vl ; -:VFMSUBADD231PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMSUBADD231PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsubadd231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6813,7 +6813,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; } # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102466 -:VFMSUBADD132PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMSUBADD132PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsubadd132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6821,7 +6821,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; } # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102470 -:VFMSUBADD213PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMSUBADD213PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsubadd213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6829,7 +6829,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; } # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-165 PAGE 1989 LINE 102474 -:VFMSUBADD231PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMSUBADD231PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsubadd231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6838,7 +6838,7 @@ define pcodeop vfmsubadd231pd_avx512vl ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102490 define pcodeop vfmsubadd132pd_avx512f ; -:VFMSUBADD132PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x97; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMSUBADD132PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x97; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsubadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6846,7 +6846,7 @@ define pcodeop vfmsubadd132pd_avx512f ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102494 define pcodeop vfmsubadd213pd_avx512f ; -:VFMSUBADD213PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xA7; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMSUBADD213PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xA7; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsubadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6854,7 +6854,7 @@ define pcodeop vfmsubadd213pd_avx512f ; # VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD 5-166 PAGE 1990 LINE 102498 define pcodeop vfmsubadd231pd_avx512f ; -:VFMSUBADD231PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xB7; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMSUBADD231PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xB7; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsubadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6862,7 +6862,7 @@ define pcodeop vfmsubadd231pd_avx512f ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102894 define pcodeop vfmsubadd132ps_avx512vl ; -:VFMSUBADD132PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMSUBADD132PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x97; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsubadd132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6871,7 +6871,7 @@ define pcodeop vfmsubadd132ps_avx512vl ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102897 define pcodeop vfmsubadd213ps_avx512vl ; -:VFMSUBADD213PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMSUBADD213PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xA7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsubadd213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6880,7 +6880,7 @@ define pcodeop vfmsubadd213ps_avx512vl ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102901 define pcodeop vfmsubadd231ps_avx512vl ; -:VFMSUBADD231PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMSUBADD231PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xB7; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsubadd231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -6888,7 +6888,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; } # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102904 -:VFMSUBADD132PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMSUBADD132PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x97; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsubadd132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6896,7 +6896,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; } # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102907 -:VFMSUBADD213PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMSUBADD213PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xA7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsubadd213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6904,7 +6904,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; } # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102911 -:VFMSUBADD231PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMSUBADD231PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xB7; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsubadd231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -6913,7 +6913,7 @@ define pcodeop vfmsubadd231ps_avx512vl ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102914 define pcodeop vfmsubadd132ps_avx512f ; -:VFMSUBADD132PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x97; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMSUBADD132PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x97; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsubadd132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6921,7 +6921,7 @@ define pcodeop vfmsubadd132ps_avx512f ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102917 define pcodeop vfmsubadd213ps_avx512f ; -:VFMSUBADD213PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xA7; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMSUBADD213PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xA7; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsubadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6929,7 +6929,7 @@ define pcodeop vfmsubadd213ps_avx512f ; # VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS 5-175 PAGE 1999 LINE 102921 define pcodeop vfmsubadd231ps_avx512f ; -:VFMSUBADD231PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xB7; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMSUBADD231PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xB7; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsubadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -6937,7 +6937,7 @@ define pcodeop vfmsubadd231ps_avx512f ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103332 define pcodeop vfmsub132pd_avx512vl ; -:VFMSUB132PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMSUB132PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsub132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6946,7 +6946,7 @@ define pcodeop vfmsub132pd_avx512vl ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103335 define pcodeop vfmsub213pd_avx512vl ; -:VFMSUB213PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMSUB213PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsub213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6955,7 +6955,7 @@ define pcodeop vfmsub213pd_avx512vl ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103338 define pcodeop vfmsub231pd_avx512vl ; -:VFMSUB231PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFMSUB231PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsub231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -6963,7 +6963,7 @@ define pcodeop vfmsub231pd_avx512vl ; } # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103341 -:VFMSUB132PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMSUB132PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsub132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6971,7 +6971,7 @@ define pcodeop vfmsub231pd_avx512vl ; } # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103344 -:VFMSUB213PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMSUB213PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsub213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6979,7 +6979,7 @@ define pcodeop vfmsub231pd_avx512vl ; } # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103347 -:VFMSUB231PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFMSUB231PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsub231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -6988,7 +6988,7 @@ define pcodeop vfmsub231pd_avx512vl ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103350 define pcodeop vfmsub132pd_avx512f ; -:VFMSUB132PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x9A; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMSUB132PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x9A; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -6996,7 +6996,7 @@ define pcodeop vfmsub132pd_avx512f ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103353 define pcodeop vfmsub213pd_avx512f ; -:VFMSUB213PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xAA; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMSUB213PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xAA; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7004,7 +7004,7 @@ define pcodeop vfmsub213pd_avx512f ; # VFMSUB132PD/VFMSUB213PD/VFMSUB231PD 5-185 PAGE 2009 LINE 103356 define pcodeop vfmsub231pd_avx512f ; -:VFMSUB231PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xBA; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFMSUB231PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xBA; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7012,7 +7012,7 @@ define pcodeop vfmsub231pd_avx512f ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103692 define pcodeop vfmsub132ps_avx512vl ; -:VFMSUB132PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMSUB132PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsub132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7021,7 +7021,7 @@ define pcodeop vfmsub132ps_avx512vl ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103695 define pcodeop vfmsub213ps_avx512vl ; -:VFMSUB213PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMSUB213PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsub213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7030,7 +7030,7 @@ define pcodeop vfmsub213ps_avx512vl ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103698 define pcodeop vfmsub231ps_avx512vl ; -:VFMSUB231PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFMSUB231PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBA; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfmsub231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7038,7 +7038,7 @@ define pcodeop vfmsub231ps_avx512vl ; } # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103701 -:VFMSUB132PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMSUB132PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x9A; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsub132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7046,7 +7046,7 @@ define pcodeop vfmsub231ps_avx512vl ; } # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103704 -:VFMSUB213PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMSUB213PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xAA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsub213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7054,7 +7054,7 @@ define pcodeop vfmsub231ps_avx512vl ; } # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103707 -:VFMSUB231PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFMSUB231PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xBA; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfmsub231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7063,7 +7063,7 @@ define pcodeop vfmsub231ps_avx512vl ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103710 define pcodeop vfmsub132ps_avx512f ; -:VFMSUB132PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x9A; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMSUB132PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x9A; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7071,7 +7071,7 @@ define pcodeop vfmsub132ps_avx512f ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103713 define pcodeop vfmsub213ps_avx512f ; -:VFMSUB213PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xAA; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMSUB213PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xAA; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7079,7 +7079,7 @@ define pcodeop vfmsub213ps_avx512f ; # VFMSUB132PS/VFMSUB213PS/VFMSUB231PS 5-192 PAGE 2016 LINE 103716 define pcodeop vfmsub231ps_avx512f ; -:VFMSUB231PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xBA; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFMSUB231PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xBA; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7087,7 +7087,7 @@ define pcodeop vfmsub231ps_avx512f ; # VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104042 define pcodeop vfmsub132sd_avx512f ; -:VFMSUB132SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMSUB132SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmsub132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7096,7 +7096,7 @@ define pcodeop vfmsub132sd_avx512f ; # VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104045 define pcodeop vfmsub213sd_avx512f ; -:VFMSUB213SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMSUB213SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmsub213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7105,7 +7105,7 @@ define pcodeop vfmsub213sd_avx512f ; # VFMSUB132SD/VFMSUB213SD/VFMSUB231SD 5-199 PAGE 2023 LINE 104048 define pcodeop vfmsub231sd_avx512f ; -:VFMSUB231SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFMSUB231SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmsub231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7114,7 +7114,7 @@ define pcodeop vfmsub231sd_avx512f ; # VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104217 define pcodeop vfmsub132ss_avx512f ; -:VFMSUB132SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMSUB132SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmsub132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7123,7 +7123,7 @@ define pcodeop vfmsub132ss_avx512f ; # VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104220 define pcodeop vfmsub213ss_avx512f ; -:VFMSUB213SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMSUB213SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmsub213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7132,7 +7132,7 @@ define pcodeop vfmsub213ss_avx512f ; # VFMSUB132SS/VFMSUB213SS/VFMSUB231SS 5-202 PAGE 2026 LINE 104223 define pcodeop vfmsub231ss_avx512f ; -:VFMSUB231SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFMSUB231SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfmsub231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7141,7 +7141,7 @@ define pcodeop vfmsub231ss_avx512f ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104401 define pcodeop vfnmadd132pd_avx512vl ; -:VFNMADD132PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFNMADD132PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmadd132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7150,7 +7150,7 @@ define pcodeop vfnmadd132pd_avx512vl ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104405 define pcodeop vfnmadd213pd_avx512vl ; -:VFNMADD213PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFNMADD213PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmadd213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7159,7 +7159,7 @@ define pcodeop vfnmadd213pd_avx512vl ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104408 define pcodeop vfnmadd231pd_avx512vl ; -:VFNMADD231PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFNMADD231PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmadd231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7167,7 +7167,7 @@ define pcodeop vfnmadd231pd_avx512vl ; } # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104412 -:VFNMADD132PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFNMADD132PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmadd132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7175,7 +7175,7 @@ define pcodeop vfnmadd231pd_avx512vl ; } # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104416 -:VFNMADD213PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFNMADD213PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmadd213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7183,7 +7183,7 @@ define pcodeop vfnmadd231pd_avx512vl ; } # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104419 -:VFNMADD231PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFNMADD231PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmadd231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7192,7 +7192,7 @@ define pcodeop vfnmadd231pd_avx512vl ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104423 define pcodeop vfnmadd132pd_avx512f ; -:VFNMADD132PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x9C; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFNMADD132PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x9C; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmadd132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7200,7 +7200,7 @@ define pcodeop vfnmadd132pd_avx512f ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104426 define pcodeop vfnmadd213pd_avx512f ; -:VFNMADD213PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xAC; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFNMADD213PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xAC; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmadd213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7208,7 +7208,7 @@ define pcodeop vfnmadd213pd_avx512f ; # VFNMADD132PD/VFNMADD213PD/VFNMADD231PD 5-205 PAGE 2029 LINE 104429 define pcodeop vfnmadd231pd_avx512f ; -:VFNMADD231PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xBC; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFNMADD231PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xBC; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmadd231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7216,7 +7216,7 @@ define pcodeop vfnmadd231pd_avx512f ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104760 define pcodeop vfnmadd132ps_avx512vl ; -:VFNMADD132PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFNMADD132PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmadd132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7225,7 +7225,7 @@ define pcodeop vfnmadd132ps_avx512vl ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104763 define pcodeop vfnmadd213ps_avx512vl ; -:VFNMADD213PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFNMADD213PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmadd213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7234,7 +7234,7 @@ define pcodeop vfnmadd213ps_avx512vl ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104766 define pcodeop vfnmadd231ps_avx512vl ; -:VFNMADD231PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFNMADD231PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBC; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmadd231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7242,7 +7242,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104769 -:VFNMADD132PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFNMADD132PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x9C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmadd132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7250,7 +7250,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104772 -:VFNMADD213PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFNMADD213PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xAC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmadd213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7258,7 +7258,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104775 -:VFNMADD231PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFNMADD231PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xBC; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmadd231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7266,7 +7266,7 @@ define pcodeop vfnmadd231ps_avx512vl ; } # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104778 -:VFNMADD132PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x9C; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFNMADD132PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x9C; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmadd132ps_avx512vl( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7274,7 +7274,7 @@ define pcodeop vfnmadd231ps_avx512vl ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104781 define pcodeop vfnmadd213ps_avx512f ; -:VFNMADD213PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xAC; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFNMADD213PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xAC; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmadd213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7282,7 +7282,7 @@ define pcodeop vfnmadd213ps_avx512f ; # VFNMADD132PS/VFNMADD213PS/VFNMADD231PS 5-212 PAGE 2036 LINE 104784 define pcodeop vfnmadd231ps_avx512f ; -:VFNMADD231PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xBC; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFNMADD231PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xBC; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmadd231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7290,7 +7290,7 @@ define pcodeop vfnmadd231ps_avx512f ; # VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105098 define pcodeop vfnmadd132sd_avx512f ; -:VFNMADD132SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFNMADD132SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmadd132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7299,7 +7299,7 @@ define pcodeop vfnmadd132sd_avx512f ; # VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105101 define pcodeop vfnmadd213sd_avx512f ; -:VFNMADD213SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFNMADD213SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmadd213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7308,7 +7308,7 @@ define pcodeop vfnmadd213sd_avx512f ; # VFNMADD132SD/VFNMADD213SD/VFNMADD231SD 5-218 PAGE 2042 LINE 105104 define pcodeop vfnmadd231sd_avx512f ; -:VFNMADD231SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFNMADD231SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmadd231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7317,7 +7317,7 @@ define pcodeop vfnmadd231sd_avx512f ; # VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105270 define pcodeop vfnmadd132ss_avx512f ; -:VFNMADD132SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFNMADD132SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmadd132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7326,7 +7326,7 @@ define pcodeop vfnmadd132ss_avx512f ; # VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105273 define pcodeop vfnmadd213ss_avx512f ; -:VFNMADD213SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFNMADD213SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmadd213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7335,7 +7335,7 @@ define pcodeop vfnmadd213ss_avx512f ; # VFNMADD132SS/VFNMADD213SS/VFNMADD231SS 5-221 PAGE 2045 LINE 105276 define pcodeop vfnmadd231ss_avx512f ; -:VFNMADD231SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFNMADD231SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmadd231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7344,7 +7344,7 @@ define pcodeop vfnmadd231ss_avx512f ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105451 define pcodeop vfnmsub132pd_avx512vl ; -:VFNMSUB132PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFNMSUB132PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmsub132pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7353,7 +7353,7 @@ define pcodeop vfnmsub132pd_avx512vl ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105455 define pcodeop vfnmsub213pd_avx512vl ; -:VFNMSUB213PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFNMSUB213PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmsub213pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7362,7 +7362,7 @@ define pcodeop vfnmsub213pd_avx512vl ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105458 define pcodeop vfnmsub231pd_avx512vl ; -:VFNMSUB231PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VFNMSUB231PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmsub231pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -7370,7 +7370,7 @@ define pcodeop vfnmsub231pd_avx512vl ; } # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105462 -:VFNMSUB132PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFNMSUB132PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmsub132pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7378,7 +7378,7 @@ define pcodeop vfnmsub231pd_avx512vl ; } # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105466 -:VFNMSUB213PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFNMSUB213PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmsub213pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7386,7 +7386,7 @@ define pcodeop vfnmsub231pd_avx512vl ; } # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105469 -:VFNMSUB231PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VFNMSUB231PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmsub231pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -7395,7 +7395,7 @@ define pcodeop vfnmsub231pd_avx512vl ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105473 define pcodeop vfnmsub132pd_avx512f ; -:VFNMSUB132PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x9E; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFNMSUB132PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x9E; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmsub132pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7403,7 +7403,7 @@ define pcodeop vfnmsub132pd_avx512f ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105476 define pcodeop vfnmsub213pd_avx512f ; -:VFNMSUB213PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xAE; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFNMSUB213PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xAE; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmsub213pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7411,7 +7411,7 @@ define pcodeop vfnmsub213pd_avx512f ; # VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD 5-224 PAGE 2048 LINE 105479 define pcodeop vfnmsub231pd_avx512f ; -:VFNMSUB231PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xBE; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VFNMSUB231PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0xBE; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmsub231pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -7419,7 +7419,7 @@ define pcodeop vfnmsub231pd_avx512f ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105800 define pcodeop vfnmsub132ps_avx512vl ; -:VFNMSUB132PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFNMSUB132PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmsub132ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7428,7 +7428,7 @@ define pcodeop vfnmsub132ps_avx512vl ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105803 define pcodeop vfnmsub213ps_avx512vl ; -:VFNMSUB213PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFNMSUB213PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmsub213ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7437,7 +7437,7 @@ define pcodeop vfnmsub213ps_avx512vl ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105806 define pcodeop vfnmsub231ps_avx512vl ; -:VFNMSUB231PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VFNMSUB231PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBE; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vfnmsub231ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -7445,7 +7445,7 @@ define pcodeop vfnmsub231ps_avx512vl ; } # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105809 -:VFNMSUB132PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFNMSUB132PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x9E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmsub132ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7453,7 +7453,7 @@ define pcodeop vfnmsub231ps_avx512vl ; } # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105812 -:VFNMSUB213PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFNMSUB213PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xAE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmsub213ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7461,7 +7461,7 @@ define pcodeop vfnmsub231ps_avx512vl ; } # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105815 -:VFNMSUB231PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VFNMSUB231PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0xBE; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vfnmsub231ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -7470,7 +7470,7 @@ define pcodeop vfnmsub231ps_avx512vl ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105818 define pcodeop vfnmsub132ps_avx512f ; -:VFNMSUB132PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x9E; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFNMSUB132PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x9E; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmsub132ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7478,7 +7478,7 @@ define pcodeop vfnmsub132ps_avx512f ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105821 define pcodeop vfnmsub213ps_avx512f ; -:VFNMSUB213PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xAE; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFNMSUB213PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xAE; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmsub213ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7486,7 +7486,7 @@ define pcodeop vfnmsub213ps_avx512f ; # VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS 5-230 PAGE 2054 LINE 105824 define pcodeop vfnmsub231ps_avx512f ; -:VFNMSUB231PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xBE; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VFNMSUB231PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0xBE; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vfnmsub231ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -7494,7 +7494,7 @@ define pcodeop vfnmsub231ps_avx512f ; # VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106135 define pcodeop vfnmsub132sd_avx512f ; -:VFNMSUB132SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFNMSUB132SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmsub132sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7503,7 +7503,7 @@ define pcodeop vfnmsub132sd_avx512f ; # VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106138 define pcodeop vfnmsub213sd_avx512f ; -:VFNMSUB213SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFNMSUB213SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmsub213sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7512,7 +7512,7 @@ define pcodeop vfnmsub213sd_avx512f ; # VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD 5-236 PAGE 2060 LINE 106141 define pcodeop vfnmsub231sd_avx512f ; -:VFNMSUB231SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VFNMSUB231SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmsub231sd_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7521,7 +7521,7 @@ define pcodeop vfnmsub231sd_avx512f ; # VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106307 define pcodeop vfnmsub132ss_avx512f ; -:VFNMSUB132SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFNMSUB132SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x9F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmsub132ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7530,7 +7530,7 @@ define pcodeop vfnmsub132ss_avx512f ; # VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106310 define pcodeop vfnmsub213ss_avx512f ; -:VFNMSUB213SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFNMSUB213SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xAF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmsub213ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7539,7 +7539,7 @@ define pcodeop vfnmsub213ss_avx512f ; # VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS 5-239 PAGE 2063 LINE 106313 define pcodeop vfnmsub231ss_avx512f ; -:VFNMSUB231SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VFNMSUB231SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xBF; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vfnmsub231ss_avx512f( XmmReg1, vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7548,14 +7548,14 @@ define pcodeop vfnmsub231ss_avx512f ; # VFPCLASSPD 5-242 PAGE 2066 LINE 106466 define pcodeop vfpclasspd_avx512vl ; -:VFPCLASSPD KReg_reg KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m64bcst +:VFPCLASSPD KReg_reg^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vfpclasspd_avx512vl( XmmReg2_m128_m64bcst ); } # VFPCLASSPD 5-242 PAGE 2066 LINE 106470 -:VFPCLASSPD KReg_reg KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m64bcst +:VFPCLASSPD KReg_reg^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vfpclasspd_avx512vl( YmmReg2_m256_m64bcst ); @@ -7563,7 +7563,7 @@ define pcodeop vfpclasspd_avx512vl ; # VFPCLASSPD 5-242 PAGE 2066 LINE 106474 define pcodeop vfpclasspd_avx512dq ; -:VFPCLASSPD KReg_reg KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m64bcst +:VFPCLASSPD KReg_reg^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vfpclasspd_avx512dq( ZmmReg2_m512_m64bcst ); @@ -7571,14 +7571,14 @@ define pcodeop vfpclasspd_avx512dq ; # VFPCLASSPS 5-245 PAGE 2069 LINE 106608 define pcodeop vfpclassps_avx512vl ; -:VFPCLASSPS KReg_reg KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst +:VFPCLASSPS KReg_reg^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x66; KReg_reg ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vfpclassps_avx512vl( XmmReg2_m128_m32bcst ); } # VFPCLASSPS 5-245 PAGE 2069 LINE 106612 -:VFPCLASSPS KReg_reg KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst +:VFPCLASSPS KReg_reg^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x66; KReg_reg ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vfpclassps_avx512vl( YmmReg2_m256_m32bcst ); @@ -7586,7 +7586,7 @@ define pcodeop vfpclassps_avx512vl ; # VFPCLASSPS 5-245 PAGE 2069 LINE 106616 define pcodeop vfpclassps_avx512dq ; -:VFPCLASSPS KReg_reg KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst +:VFPCLASSPS KReg_reg^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x66; KReg_reg ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vfpclassps_avx512dq( ZmmReg2_m512_m32bcst ); @@ -7594,7 +7594,7 @@ define pcodeop vfpclassps_avx512dq ; # VFPCLASSSD 5-247 PAGE 2071 LINE 106722 define pcodeop vfpclasssd_avx512dq ; -:VFPCLASSSD KReg_reg KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x67; KReg_reg ... & XmmReg2_m64 +:VFPCLASSSD KReg_reg^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x67; KReg_reg ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { KReg_reg = vfpclasssd_avx512dq( XmmReg2_m64 ); @@ -7602,7 +7602,7 @@ define pcodeop vfpclasssd_avx512dq ; # VFPCLASSSS 5-249 PAGE 2073 LINE 106810 define pcodeop vfpclassss_avx512dq ; -:VFPCLASSSS KReg_reg KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x67; KReg_reg ... & XmmReg2_m32 +:VFPCLASSSS KReg_reg^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x67; KReg_reg ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { KReg_reg = vfpclassss_avx512dq( XmmReg2_m32 ); @@ -7611,7 +7611,7 @@ define pcodeop vfpclassss_avx512dq ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107357 # WARNING: did not recognize qualifier /vsib for "VGATHERDPS xmm1 {k1}, vm32x" define pcodeop vgatherdps_avx512vl ; -:VGATHERDPS XmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x92; (XmmReg1 & ZmmReg1) ... & m32 +:VGATHERDPS XmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x92; (XmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgatherdps_avx512vl( m32 ); @@ -7620,7 +7620,7 @@ define pcodeop vgatherdps_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107359 # WARNING: did not recognize qualifier /vsib for "VGATHERDPS ymm1 {k1}, vm32y" -:VGATHERDPS YmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x92; (YmmReg1 & ZmmReg1) ... & m32 +:VGATHERDPS YmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x92; (YmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vgatherdps_avx512vl( m32 ); @@ -7630,7 +7630,7 @@ define pcodeop vgatherdps_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107361 # WARNING: did not recognize qualifier /vsib for "VGATHERDPS zmm1 {k1}, vm32z" define pcodeop vgatherdps_avx512f ; -:VGATHERDPS ZmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x92; ZmmReg1 ... & m32 +:VGATHERDPS ZmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x92; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vgatherdps_avx512f( m32 ); @@ -7639,7 +7639,7 @@ define pcodeop vgatherdps_avx512f ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107363 # WARNING: did not recognize qualifier /vsib for "VGATHERDPD xmm1 {k1}, vm32x" define pcodeop vgatherdpd_avx512vl ; -:VGATHERDPD XmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x92; (XmmReg1 & ZmmReg1) ... & m32 +:VGATHERDPD XmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x92; (XmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgatherdpd_avx512vl( m32 ); @@ -7648,7 +7648,7 @@ define pcodeop vgatherdpd_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107366 # WARNING: did not recognize qualifier /vsib for "VGATHERDPD ymm1 {k1}, vm32x" -:VGATHERDPD YmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x92; (YmmReg1 & ZmmReg1) ... & m32 +:VGATHERDPD YmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x92; (YmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vgatherdpd_avx512vl( m32 ); @@ -7658,7 +7658,7 @@ define pcodeop vgatherdpd_avx512vl ; # VGATHERDPS/VGATHERDPD 5-261 PAGE 2085 LINE 107369 # WARNING: did not recognize qualifier /vsib for "VGATHERDPD zmm1 {k1}, vm32y" define pcodeop vgatherdpd_avx512f ; -:VGATHERDPD ZmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x92; ZmmReg1 ... & m32 +:VGATHERDPD ZmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x92; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vgatherdpd_avx512f( m32 ); @@ -7747,7 +7747,7 @@ define pcodeop vgatherpf1qpd_avx512pf ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107742 # WARNING: did not recognize qualifier /vsib for "VGATHERQPS xmm1 {k1}, vm64x" define pcodeop vgatherqps_avx512vl ; -:VGATHERQPS XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x93; (XmmReg1 & ZmmReg1) ... & m64 +:VGATHERQPS XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x93; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgatherqps_avx512vl( m64 ); @@ -7756,7 +7756,7 @@ define pcodeop vgatherqps_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107745 # WARNING: did not recognize qualifier /vsib for "VGATHERQPS xmm1 {k1}, vm64y" -:VGATHERQPS XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x93; (XmmReg1 & ZmmReg1) ... & m64 +:VGATHERQPS XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x93; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgatherqps_avx512vl( m64 ); @@ -7766,7 +7766,7 @@ define pcodeop vgatherqps_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107748 # WARNING: did not recognize qualifier /vsib for "VGATHERQPS ymm1 {k1}, vm64z" define pcodeop vgatherqps_avx512f ; -:VGATHERQPS YmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x93; (YmmReg1 & ZmmReg1) ... & m64 +:VGATHERQPS YmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x93; (YmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vgatherqps_avx512f( m64 ); @@ -7776,7 +7776,7 @@ define pcodeop vgatherqps_avx512f ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107751 # WARNING: did not recognize qualifier /vsib for "VGATHERQPD xmm1 {k1}, vm64x" define pcodeop vgatherqpd_avx512vl ; -:VGATHERQPD XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x93; (XmmReg1 & ZmmReg1) ... & m64 +:VGATHERQPD XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x93; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgatherqpd_avx512vl( m64 ); @@ -7785,7 +7785,7 @@ define pcodeop vgatherqpd_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107753 # WARNING: did not recognize qualifier /vsib for "VGATHERQPD ymm1 {k1}, vm64y" -:VGATHERQPD YmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x93; (YmmReg1 & ZmmReg1) ... & m64 +:VGATHERQPD YmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x93; (YmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vgatherqpd_avx512vl( m64 ); @@ -7795,7 +7795,7 @@ define pcodeop vgatherqpd_avx512vl ; # VGATHERQPS/VGATHERQPD 5-270 PAGE 2094 LINE 107755 # WARNING: did not recognize qualifier /vsib for "VGATHERQPD zmm1 {k1}, vm64z" define pcodeop vgatherqpd_avx512f ; -:VGATHERQPD ZmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x93; ZmmReg1 ... & m64 +:VGATHERQPD ZmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x93; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vgatherqpd_avx512f( m64 ); @@ -7804,7 +7804,7 @@ define pcodeop vgatherqpd_avx512f ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108099 # WARNING: did not recognize qualifier /vsib for "VPGATHERDD xmm1 {k1}, vm32x" define pcodeop vpgatherdd_avx512vl ; -:VPGATHERDD XmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x90; (XmmReg1 & ZmmReg1) ... & m32 +:VPGATHERDD XmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x90; (XmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpgatherdd_avx512vl( m32 ); @@ -7813,7 +7813,7 @@ define pcodeop vpgatherdd_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108101 # WARNING: did not recognize qualifier /vsib for "VPGATHERDD ymm1 {k1}, vm32y" -:VPGATHERDD YmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x90; (YmmReg1 & ZmmReg1) ... & m32 +:VPGATHERDD YmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x90; (YmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vpgatherdd_avx512vl( m32 ); @@ -7823,7 +7823,7 @@ define pcodeop vpgatherdd_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108103 # WARNING: did not recognize qualifier /vsib for "VPGATHERDD zmm1 {k1}, vm32z" define pcodeop vpgatherdd_avx512f ; -:VPGATHERDD ZmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x90; ZmmReg1 ... & m32 +:VPGATHERDD ZmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x90; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vpgatherdd_avx512f( m32 ); @@ -7832,7 +7832,7 @@ define pcodeop vpgatherdd_avx512f ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108105 # WARNING: did not recognize qualifier /vsib for "VPGATHERDQ xmm1 {k1}, vm32x" define pcodeop vpgatherdq_avx512vl ; -:VPGATHERDQ XmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x90; (XmmReg1 & ZmmReg1) ... & m32 +:VPGATHERDQ XmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x90; (XmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpgatherdq_avx512vl( m32 ); @@ -7841,7 +7841,7 @@ define pcodeop vpgatherdq_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108107 # WARNING: did not recognize qualifier /vsib for "VPGATHERDQ ymm1 {k1}, vm32x" -:VPGATHERDQ YmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x90; (YmmReg1 & ZmmReg1) ... & m32 +:VPGATHERDQ YmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x90; (YmmReg1 & ZmmReg1) ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vpgatherdq_avx512vl( m32 ); @@ -7851,7 +7851,7 @@ define pcodeop vpgatherdq_avx512vl ; # VPGATHERDD/VPGATHERDQ 5-277 PAGE 2101 LINE 108109 # WARNING: did not recognize qualifier /vsib for "VPGATHERDQ zmm1 {k1}, vm32y" define pcodeop vpgatherdq_avx512f ; -:VPGATHERDQ ZmmReg1 KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x90; ZmmReg1 ... & m32 +:VPGATHERDQ ZmmReg1^KWriteMask, m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x90; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vpgatherdq_avx512f( m32 ); @@ -7860,7 +7860,7 @@ define pcodeop vpgatherdq_avx512f ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108457 # WARNING: did not recognize qualifier /vsib for "VPGATHERQD xmm1 {k1}, vm64x" define pcodeop vpgatherqd_avx512vl ; -:VPGATHERQD XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x91; (XmmReg1 & ZmmReg1) ... & m64 +:VPGATHERQD XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x91; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpgatherqd_avx512vl( m64 ); @@ -7869,7 +7869,7 @@ define pcodeop vpgatherqd_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108459 # WARNING: did not recognize qualifier /vsib for "VPGATHERQD xmm1 {k1}, vm64y" -:VPGATHERQD XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x91; (XmmReg1 & ZmmReg1) ... & m64 +:VPGATHERQD XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x91; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpgatherqd_avx512vl( m64 ); @@ -7879,7 +7879,7 @@ define pcodeop vpgatherqd_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108461 # WARNING: did not recognize qualifier /vsib for "VPGATHERQD ymm1 {k1}, vm64z" define pcodeop vpgatherqd_avx512f ; -:VPGATHERQD YmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x91; (YmmReg1 & ZmmReg1) ... & m64 +:VPGATHERQD YmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x91; (YmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vpgatherqd_avx512f( m64 ); @@ -7889,7 +7889,7 @@ define pcodeop vpgatherqd_avx512f ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108463 # WARNING: did not recognize qualifier /vsib for "VPGATHERQQ xmm1 {k1}, vm64x" define pcodeop vpgatherqq_avx512vl ; -:VPGATHERQQ XmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x91; (XmmReg1 & ZmmReg1) ... & m64 +:VPGATHERQQ XmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x91; (XmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpgatherqq_avx512vl( m64 ); @@ -7898,7 +7898,7 @@ define pcodeop vpgatherqq_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108465 # WARNING: did not recognize qualifier /vsib for "VPGATHERQQ ymm1 {k1}, vm64y" -:VPGATHERQQ YmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x91; (YmmReg1 & ZmmReg1) ... & m64 +:VPGATHERQQ YmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x91; (YmmReg1 & ZmmReg1) ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vpgatherqq_avx512vl( m64 ); @@ -7908,7 +7908,7 @@ define pcodeop vpgatherqq_avx512vl ; # VPGATHERQD/VPGATHERQQ 5-285 PAGE 2109 LINE 108467 # WARNING: did not recognize qualifier /vsib for "VPGATHERQQ zmm1 {k1}, vm64z" define pcodeop vpgatherqq_avx512f ; -:VPGATHERQQ ZmmReg1 KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x91; ZmmReg1 ... & m64 +:VPGATHERQQ ZmmReg1^KWriteMask, m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x91; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vpgatherqq_avx512f( m64 ); @@ -7916,7 +7916,7 @@ define pcodeop vpgatherqq_avx512f ; # VGETEXPPD 5-288 PAGE 2112 LINE 108594 define pcodeop vgetexppd_avx512vl ; -:VGETEXPPD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VGETEXPPD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vgetexppd_avx512vl( XmmReg2_m128_m64bcst ); @@ -7924,7 +7924,7 @@ define pcodeop vgetexppd_avx512vl ; } # VGETEXPPD 5-288 PAGE 2112 LINE 108598 -:VGETEXPPD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VGETEXPPD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vgetexppd_avx512vl( YmmReg2_m256_m64bcst ); @@ -7933,7 +7933,7 @@ define pcodeop vgetexppd_avx512vl ; # VGETEXPPD 5-288 PAGE 2112 LINE 108602 define pcodeop vgetexppd_avx512f ; -:VGETEXPPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x42; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VGETEXPPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x42; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vgetexppd_avx512f( ZmmReg2_m512_m64bcst ); @@ -7941,7 +7941,7 @@ define pcodeop vgetexppd_avx512f ; # VGETEXPPS 5-291 PAGE 2115 LINE 108760 define pcodeop vgetexpps_avx512vl ; -:VGETEXPPS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VGETEXPPS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x42; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vgetexpps_avx512vl( XmmReg2_m128_m32bcst ); @@ -7949,7 +7949,7 @@ define pcodeop vgetexpps_avx512vl ; } # VGETEXPPS 5-291 PAGE 2115 LINE 108764 -:VGETEXPPS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VGETEXPPS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x42; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vgetexpps_avx512vl( YmmReg2_m256_m32bcst ); @@ -7958,7 +7958,7 @@ define pcodeop vgetexpps_avx512vl ; # VGETEXPPS 5-291 PAGE 2115 LINE 108768 define pcodeop vgetexpps_avx512f ; -:VGETEXPPS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x42; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VGETEXPPS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x42; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vgetexpps_avx512f( ZmmReg2_m512_m32bcst ); @@ -7966,7 +7966,7 @@ define pcodeop vgetexpps_avx512f ; # VGETEXPSD 5-295 PAGE 2119 LINE 108959 define pcodeop vgetexpsd_avx512f ; -:VGETEXPSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VGETEXPSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgetexpsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -7975,7 +7975,7 @@ define pcodeop vgetexpsd_avx512f ; # VGETEXPSS 5-297 PAGE 2121 LINE 109037 define pcodeop vgetexpss_avx512f ; -:VGETEXPSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VGETEXPSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x43; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgetexpss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -7984,7 +7984,7 @@ define pcodeop vgetexpss_avx512f ; # VGETMANTPD 5-299 PAGE 2123 LINE 109120 define pcodeop vgetmantpd_avx512vl ; -:VGETMANTPD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x26; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VGETMANTPD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x26; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:16 = vgetmantpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -7992,7 +7992,7 @@ define pcodeop vgetmantpd_avx512vl ; } # VGETMANTPD 5-299 PAGE 2123 LINE 109125 -:VGETMANTPD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x26; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VGETMANTPD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x26; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:32 = vgetmantpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -8001,7 +8001,7 @@ define pcodeop vgetmantpd_avx512vl ; # VGETMANTPD 5-299 PAGE 2123 LINE 109130 define pcodeop vgetmantpd_avx512f ; -:VGETMANTPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x26; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VGETMANTPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x26; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmReg1 = vgetmantpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -8009,7 +8009,7 @@ define pcodeop vgetmantpd_avx512f ; # VGETMANTPS 5-303 PAGE 2127 LINE 109339 define pcodeop vgetmantps_avx512vl ; -:VGETMANTPS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x26; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VGETMANTPS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x26; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:16 = vgetmantps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -8017,7 +8017,7 @@ define pcodeop vgetmantps_avx512vl ; } # VGETMANTPS 5-303 PAGE 2127 LINE 109344 -:VGETMANTPS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x26; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VGETMANTPS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x26; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { local tmp:32 = vgetmantps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -8026,7 +8026,7 @@ define pcodeop vgetmantps_avx512vl ; # VGETMANTPS 5-303 PAGE 2127 LINE 109349 define pcodeop vgetmantps_avx512f ; -:VGETMANTPS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x26; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VGETMANTPS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x26; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FVI) { ZmmReg1 = vgetmantps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -8034,7 +8034,7 @@ define pcodeop vgetmantps_avx512f ; # VGETMANTSD 5-306 PAGE 2130 LINE 109519 define pcodeop vgetmantsd_avx512f ; -:VGETMANTSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VGETMANTSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgetmantsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -8043,7 +8043,7 @@ define pcodeop vgetmantsd_avx512f ; # VGETMANTSS 5-308 PAGE 2132 LINE 109610 define pcodeop vgetmantss_avx512f ; -:VGETMANTSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VGETMANTSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x27; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vgetmantss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -8052,7 +8052,7 @@ define pcodeop vgetmantss_avx512f ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109706 define pcodeop vinsertf32x4_avx512vl ; -:VINSERTF32X4 YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VINSERTF32X4 YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { local tmp:32 = vinsertf32x4_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -8061,7 +8061,7 @@ define pcodeop vinsertf32x4_avx512vl ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109709 define pcodeop vinsertf32x4_avx512f ; -:VINSERTF32X4 ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x18; ZmmReg1 ... & XmmReg2_m128; imm8 +:VINSERTF32X4 ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x18; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinsertf32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -8069,7 +8069,7 @@ define pcodeop vinsertf32x4_avx512f ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109712 define pcodeop vinsertf64x2_avx512vl ; -:VINSERTF64X2 YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VINSERTF64X2 YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x18; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { local tmp:32 = vinsertf64x2_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -8078,7 +8078,7 @@ define pcodeop vinsertf64x2_avx512vl ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109715 define pcodeop vinsertf64x2_avx512dq ; -:VINSERTF64X2 ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x18; ZmmReg1 ... & XmmReg2_m128; imm8 +:VINSERTF64X2 ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x18; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinsertf64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -8086,7 +8086,7 @@ define pcodeop vinsertf64x2_avx512dq ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109718 define pcodeop vinsertf32x8_avx512dq ; -:VINSERTF32X8 ZmmReg1 KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x1A; ZmmReg1 ... & YmmReg2_m256; imm8 +:VINSERTF32X8 ZmmReg1^KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x1A; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinsertf32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -8094,7 +8094,7 @@ define pcodeop vinsertf32x8_avx512dq ; # VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4 5-310 PAGE 2134 LINE 109721 define pcodeop vinsertf64x4_avx512f ; -:VINSERTF64X4 ZmmReg1 KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x1A; ZmmReg1 ... & YmmReg2_m256; imm8 +:VINSERTF64X4 ZmmReg1^KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x1A; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinsertf64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -8102,7 +8102,7 @@ define pcodeop vinsertf64x4_avx512f ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109930 define pcodeop vinserti32x4_avx512vl ; -:VINSERTI32X4 YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VINSERTI32X4 YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { local tmp:32 = vinserti32x4_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -8111,7 +8111,7 @@ define pcodeop vinserti32x4_avx512vl ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109933 define pcodeop vinserti32x4_avx512f ; -:VINSERTI32X4 ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x38; ZmmReg1 ... & XmmReg2_m128; imm8 +:VINSERTI32X4 ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x38; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinserti32x4_avx512f( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -8119,7 +8119,7 @@ define pcodeop vinserti32x4_avx512f ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109936 define pcodeop vinserti64x2_avx512vl ; -:VINSERTI64X2 YmmReg1 KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 +:VINSERTI64X2 YmmReg1^KWriteMask, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x38; (YmmReg1 & ZmmReg1) ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { local tmp:32 = vinserti64x2_avx512vl( vexVVVV_YmmReg, XmmReg2_m128, imm8:1 ); @@ -8128,7 +8128,7 @@ define pcodeop vinserti64x2_avx512vl ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109939 define pcodeop vinserti64x2_avx512dq ; -:VINSERTI64X2 ZmmReg1 KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x38; ZmmReg1 ... & XmmReg2_m128; imm8 +:VINSERTI64X2 ZmmReg1^KWriteMask, evexV5_ZmmReg, XmmReg2_m128, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x38; ZmmReg1 ... & XmmReg2_m128; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinserti64x2_avx512dq( evexV5_ZmmReg, XmmReg2_m128, imm8:1 ); @@ -8136,7 +8136,7 @@ define pcodeop vinserti64x2_avx512dq ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109942 define pcodeop vinserti32x8_avx512dq ; -:VINSERTI32X8 ZmmReg1 KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3A; ZmmReg1 ... & YmmReg2_m256; imm8 +:VINSERTI32X8 ZmmReg1^KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3A; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinserti32x8_avx512dq( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -8144,7 +8144,7 @@ define pcodeop vinserti32x8_avx512dq ; # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109945 define pcodeop vinserti64x4_avx512f ; -:VINSERTI64X4 ZmmReg1 KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3A; ZmmReg1 ... & YmmReg2_m256; imm8 +:VINSERTI64X4 ZmmReg1^KWriteMask, evexV5_ZmmReg, YmmReg2_m256, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3A; ZmmReg1 ... & YmmReg2_m256; imm8 [ evexD8Type = 1; evexTType = 6; ] # (TupleType T2,T4,T8) { ZmmReg1 = vinserti64x4_avx512f( evexV5_ZmmReg, YmmReg2_m256, imm8:1 ); @@ -8152,7 +8152,7 @@ define pcodeop vinserti64x4_avx512f ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110393 define pcodeop vpblendmb_avx512vl ; -:VPBLENDMB XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPBLENDMB XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpblendmb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -8160,7 +8160,7 @@ define pcodeop vpblendmb_avx512vl ; } # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110396 -:VPBLENDMB YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPBLENDMB YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpblendmb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8169,7 +8169,7 @@ define pcodeop vpblendmb_avx512vl ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110399 define pcodeop vpblendmb_avx512bw ; -:VPBLENDMB ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x66; ZmmReg1 ... & ZmmReg2_m512 +:VPBLENDMB ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x66; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpblendmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8177,7 +8177,7 @@ define pcodeop vpblendmb_avx512bw ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110402 define pcodeop vpblendmw_avx512vl ; -:VPBLENDMW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPBLENDMW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x66; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpblendmw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -8185,7 +8185,7 @@ define pcodeop vpblendmw_avx512vl ; } # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110405 -:VPBLENDMW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPBLENDMW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x66; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpblendmw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8194,7 +8194,7 @@ define pcodeop vpblendmw_avx512vl ; # VPBLENDMB/VPBLENDMW 5-323 PAGE 2147 LINE 110408 define pcodeop vpblendmw_avx512bw ; -:VPBLENDMW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x66; ZmmReg1 ... & ZmmReg2_m512 +:VPBLENDMW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x66; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpblendmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8202,7 +8202,7 @@ define pcodeop vpblendmw_avx512bw ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110495 define pcodeop vpblendmd_avx512vl ; -:VPBLENDMD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPBLENDMD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpblendmd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8210,7 +8210,7 @@ define pcodeop vpblendmd_avx512vl ; } # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110498 -:VPBLENDMD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPBLENDMD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpblendmd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8219,7 +8219,7 @@ define pcodeop vpblendmd_avx512vl ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110501 define pcodeop vpblendmd_avx512f ; -:VPBLENDMD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x64; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPBLENDMD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x64; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpblendmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8227,7 +8227,7 @@ define pcodeop vpblendmd_avx512f ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110504 define pcodeop vpblendmq_avx512vl ; -:VPBLENDMQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPBLENDMQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x64; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpblendmq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8235,7 +8235,7 @@ define pcodeop vpblendmq_avx512vl ; } # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110507 -:VPBLENDMQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPBLENDMQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x64; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpblendmq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8244,7 +8244,7 @@ define pcodeop vpblendmq_avx512vl ; # VPBLENDMD/VPBLENDMQ 5-325 PAGE 2149 LINE 110510 define pcodeop vpblendmq_avx512f ; -:VPBLENDMQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x64; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPBLENDMQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x64; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpblendmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8369,7 +8369,7 @@ define pcodeop vpbroadcastq_avx512f ; @endif # VPBROADCAST 5-331 PAGE 2155 LINE 110780 -:VPBROADCASTB XmmReg1 KWriteMask, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m8 +:VPBROADCASTB XmmReg1^KWriteMask, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x78; (XmmReg1 & ZmmReg1) ... & XmmReg2_m8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:16 = vpbroadcastb_avx512vl( XmmReg2_m8 ); @@ -8377,7 +8377,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110782 -:VPBROADCASTB YmmReg1 KWriteMask, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m8 +:VPBROADCASTB YmmReg1^KWriteMask, XmmReg2_m8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x78; (YmmReg1 & ZmmReg1) ... & XmmReg2_m8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vpbroadcastb_avx512vl( XmmReg2_m8 ); @@ -8385,14 +8385,14 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110784 -:VPBROADCASTB ZmmReg1 KWriteMask, XmmReg2_m8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x78; ZmmReg1 ... & XmmReg2_m8 +:VPBROADCASTB ZmmReg1^KWriteMask, XmmReg2_m8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x78; ZmmReg1 ... & XmmReg2_m8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vpbroadcastb_avx512bw( XmmReg2_m8 ); } # VPBROADCAST 5-331 PAGE 2155 LINE 110791 -:VPBROADCASTW XmmReg1 KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 +:VPBROADCASTW XmmReg1^KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x79; (XmmReg1 & ZmmReg1) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:16 = vpbroadcastw_avx512vl( XmmReg2_m16 ); @@ -8400,7 +8400,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110794 -:VPBROADCASTW YmmReg1 KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m16 +:VPBROADCASTW YmmReg1^KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x79; (YmmReg1 & ZmmReg1) ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vpbroadcastw_avx512vl( XmmReg2_m16 ); @@ -8408,14 +8408,14 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110797 -:VPBROADCASTW ZmmReg1 KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x79; ZmmReg1 ... & XmmReg2_m16 +:VPBROADCASTW ZmmReg1^KWriteMask, XmmReg2_m16 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x79; ZmmReg1 ... & XmmReg2_m16 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vpbroadcastw_avx512bw( XmmReg2_m16 ); } # VPBROADCAST 5-331 PAGE 2155 LINE 110804 -:VPBROADCASTD XmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPBROADCASTD XmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x58; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:16 = vpbroadcastd_avx512vl( XmmReg2_m32 ); @@ -8423,7 +8423,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110807 -:VPBROADCASTD YmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x58; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VPBROADCASTD YmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x58; (YmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vpbroadcastd_avx512vl( XmmReg2_m32 ); @@ -8431,14 +8431,14 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110810 -:VPBROADCASTD ZmmReg1 KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x58; ZmmReg1 ... & XmmReg2_m32 +:VPBROADCASTD ZmmReg1^KWriteMask, XmmReg2_m32 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x58; ZmmReg1 ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vpbroadcastd_avx512f( XmmReg2_m32 ); } # VPBROADCAST 5-331 PAGE 2155 LINE 110817 -:VPBROADCASTQ XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPBROADCASTQ XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:16 = vpbroadcastq_avx512vl( XmmReg2_m64 ); @@ -8446,7 +8446,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110819 -:VPBROADCASTQ YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x59; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VPBROADCASTQ YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x59; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vpbroadcastq_avx512vl( XmmReg2_m64 ); @@ -8454,7 +8454,7 @@ define pcodeop vpbroadcastq_avx512f ; } # VPBROADCAST 5-331 PAGE 2155 LINE 110821 -:VPBROADCASTQ ZmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x59; ZmmReg1 ... & XmmReg2_m64 +:VPBROADCASTQ ZmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x59; ZmmReg1 ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vpbroadcastq_avx512f( XmmReg2_m64 ); @@ -8462,7 +8462,7 @@ define pcodeop vpbroadcastq_avx512f ; # VPBROADCAST 5-331 PAGE 2155 LINE 110823 define pcodeop vbroadcasti32x2_avx512vl ; -:VBROADCASTI32x2 XmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VBROADCASTI32x2 XmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x59; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:16 = vbroadcasti32x2_avx512vl( XmmReg2_m64 ); @@ -8470,7 +8470,7 @@ define pcodeop vbroadcasti32x2_avx512vl ; } # VPBROADCAST 5-332 PAGE 2156 LINE 110837 -:VBROADCASTI32x2 YmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x59; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VBROADCASTI32x2 YmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x59; (YmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcasti32x2_avx512vl( XmmReg2_m64 ); @@ -8479,7 +8479,7 @@ define pcodeop vbroadcasti32x2_avx512vl ; # VPBROADCAST 5-332 PAGE 2156 LINE 110840 define pcodeop vbroadcasti32x2_avx512dq ; -:VBROADCASTI32x2 ZmmReg1 KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x59; ZmmReg1 ... & XmmReg2_m64 +:VBROADCASTI32x2 ZmmReg1^KWriteMask, XmmReg2_m64 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x59; ZmmReg1 ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcasti32x2_avx512dq( XmmReg2_m64 ); @@ -8487,7 +8487,7 @@ define pcodeop vbroadcasti32x2_avx512dq ; # VPBROADCAST 5-332 PAGE 2156 LINE 110845 define pcodeop vbroadcasti32x4_avx512vl ; -:VBROADCASTI32X4 YmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & m128 +:VBROADCASTI32X4 YmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcasti32x4_avx512vl( m128 ); @@ -8496,7 +8496,7 @@ define pcodeop vbroadcasti32x4_avx512vl ; # VPBROADCAST 5-332 PAGE 2156 LINE 110848 define pcodeop vbroadcasti32x4_avx512f ; -:VBROADCASTI32X4 ZmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x5A; ZmmReg1 ... & m128 +:VBROADCASTI32X4 ZmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x5A; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcasti32x4_avx512f( m128 ); @@ -8504,7 +8504,7 @@ define pcodeop vbroadcasti32x4_avx512f ; # VPBROADCAST 5-332 PAGE 2156 LINE 110851 define pcodeop vbroadcasti64x2_avx512vl ; -:VBROADCASTI64X2 YmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & m128 +:VBROADCASTI64X2 YmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x5A; (YmmReg1 & ZmmReg1) ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { local tmp:32 = vbroadcasti64x2_avx512vl( m128 ); @@ -8513,7 +8513,7 @@ define pcodeop vbroadcasti64x2_avx512vl ; # VPBROADCAST 5-332 PAGE 2156 LINE 110854 define pcodeop vbroadcasti64x2_avx512dq ; -:VBROADCASTI64X2 ZmmReg1 KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x5A; ZmmReg1 ... & m128 +:VBROADCASTI64X2 ZmmReg1^KWriteMask, m128 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x5A; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcasti64x2_avx512dq( m128 ); @@ -8521,7 +8521,7 @@ define pcodeop vbroadcasti64x2_avx512dq ; # VPBROADCAST 5-332 PAGE 2156 LINE 110857 define pcodeop vbroadcasti32x8_avx512dq ; -:VBROADCASTI32X8 ZmmReg1 KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & m256 +:VBROADCASTI32X8 ZmmReg1^KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x5B; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcasti32x8_avx512dq( m256 ); @@ -8529,7 +8529,7 @@ define pcodeop vbroadcasti32x8_avx512dq ; # VPBROADCAST 5-332 PAGE 2156 LINE 110860 define pcodeop vbroadcasti64x4_avx512f ; -:VBROADCASTI64X4 ZmmReg1 KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x5B; ZmmReg1 ... & m256 +:VBROADCASTI64X4 ZmmReg1^KWriteMask, m256 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x5B; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S,T2,T4,T8) { ZmmReg1 = vbroadcasti64x4_avx512f( m256 ); @@ -8537,14 +8537,14 @@ define pcodeop vbroadcasti64x4_avx512f ; # VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111259 define pcodeop vpcmpb_avx512vl ; -:VPCMPB KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128 +:VPCMPB KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111263 -:VPCMPB KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256 +:VPCMPB KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8552,7 +8552,7 @@ define pcodeop vpcmpb_avx512vl ; # VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111267 define pcodeop vpcmpb_avx512bw ; -:VPCMPB KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512 +:VPCMPB KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8560,14 +8560,14 @@ define pcodeop vpcmpb_avx512bw ; # VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111271 define pcodeop vpcmpub_avx512vl ; -:VPCMPUB KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128 +:VPCMPUB KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpub_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111275 -:VPCMPUB KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256 +:VPCMPUB KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpub_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8575,7 +8575,7 @@ define pcodeop vpcmpub_avx512vl ; # VPCMPB/VPCMPUB 5-339 PAGE 2163 LINE 111279 define pcodeop vpcmpub_avx512bw ; -:VPCMPUB KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512 +:VPCMPUB KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpub_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8583,14 +8583,14 @@ define pcodeop vpcmpub_avx512bw ; # VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111422 define pcodeop vpcmpd_avx512vl ; -:VPCMPD KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m32bcst; imm8 +:VPCMPD KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); } # VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111426 -:VPCMPD KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m32bcst; imm8 +:VPCMPD KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -8598,7 +8598,7 @@ define pcodeop vpcmpd_avx512vl ; # VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111430 define pcodeop vpcmpd_avx512f ; -:VPCMPD KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m32bcst; imm8 +:VPCMPD KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -8606,14 +8606,14 @@ define pcodeop vpcmpd_avx512f ; # VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111434 define pcodeop vpcmpud_avx512vl ; -:VPCMPUD KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m32bcst; imm8 +:VPCMPUD KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpud_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); } # VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111438 -:VPCMPUD KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m32bcst; imm8 +:VPCMPUD KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpud_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -8621,7 +8621,7 @@ define pcodeop vpcmpud_avx512vl ; # VPCMPD/VPCMPUD 5-342 PAGE 2166 LINE 111442 define pcodeop vpcmpud_avx512f ; -:VPCMPUD KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m32bcst; imm8 +:VPCMPUD KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpud_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -8629,14 +8629,14 @@ define pcodeop vpcmpud_avx512f ; # VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111573 define pcodeop vpcmpq_avx512vl ; -:VPCMPQ KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m64bcst; imm8 +:VPCMPQ KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x1F; KReg_reg ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); } # VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111577 -:VPCMPQ KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m64bcst; imm8 +:VPCMPQ KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x1F; KReg_reg ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -8644,7 +8644,7 @@ define pcodeop vpcmpq_avx512vl ; # VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111581 define pcodeop vpcmpq_avx512f ; -:VPCMPQ KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m64bcst; imm8 +:VPCMPQ KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x1F; KReg_reg ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -8652,14 +8652,14 @@ define pcodeop vpcmpq_avx512f ; # VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111585 define pcodeop vpcmpuq_avx512vl ; -:VPCMPUQ KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m64bcst; imm8 +:VPCMPUQ KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x1E; KReg_reg ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpuq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); } # VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111589 -:VPCMPUQ KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m64bcst; imm8 +:VPCMPUQ KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x1E; KReg_reg ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpuq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -8667,7 +8667,7 @@ define pcodeop vpcmpuq_avx512vl ; # VPCMPQ/VPCMPUQ 5-345 PAGE 2169 LINE 111593 define pcodeop vpcmpuq_avx512f ; -:VPCMPUQ KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m64bcst; imm8 +:VPCMPUQ KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x1E; KReg_reg ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vpcmpuq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -8675,14 +8675,14 @@ define pcodeop vpcmpuq_avx512f ; # VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111724 define pcodeop vpcmpw_avx512vl ; -:VPCMPW KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128 +:VPCMPW KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3F; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111728 -:VPCMPW KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256 +:VPCMPW KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3F; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8690,7 +8690,7 @@ define pcodeop vpcmpw_avx512vl ; # VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111732 define pcodeop vpcmpw_avx512bw ; -:VPCMPW KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512 +:VPCMPW KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3F; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8698,14 +8698,14 @@ define pcodeop vpcmpw_avx512bw ; # VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111736 define pcodeop vpcmpuw_avx512vl ; -:VPCMPUW KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128 +:VPCMPUW KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x3E; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpuw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111740 -:VPCMPUW KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256 +:VPCMPUW KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x3E; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpuw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8713,7 +8713,7 @@ define pcodeop vpcmpuw_avx512vl ; # VPCMPW/VPCMPUW 5-348 PAGE 2172 LINE 111745 define pcodeop vpcmpuw_avx512bw ; -:VPCMPUW KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512 +:VPCMPUW KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x3E; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vpcmpuw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8721,14 +8721,14 @@ define pcodeop vpcmpuw_avx512bw ; # VPCOMPRESSD 5-351 PAGE 2175 LINE 111873 define pcodeop vpcompressd_avx512vl ; -:VPCOMPRESSD XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8B; XmmReg1 ... & XmmReg2_m128 +:VPCOMPRESSD XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8B; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmReg2_m128 = vpcompressd_avx512vl( XmmReg1 ); } # VPCOMPRESSD 5-351 PAGE 2175 LINE 111875 -:VPCOMPRESSD YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8B; YmmReg1 ... & YmmReg2_m256 +:VPCOMPRESSD YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8B; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmReg2_m256 = vpcompressd_avx512vl( YmmReg1 ); @@ -8736,7 +8736,7 @@ define pcodeop vpcompressd_avx512vl ; # VPCOMPRESSD 5-351 PAGE 2175 LINE 111877 define pcodeop vpcompressd_avx512f ; -:VPCOMPRESSD ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 +:VPCOMPRESSD ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg2_m512 = vpcompressd_avx512f( ZmmReg1 ); @@ -8744,14 +8744,14 @@ define pcodeop vpcompressd_avx512f ; # VPCOMPRESSQ 5-353 PAGE 2177 LINE 111970 define pcodeop vpcompressq_avx512vl ; -:VPCOMPRESSQ XmmReg2_m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8B; XmmReg1 ... & XmmReg2_m128 +:VPCOMPRESSQ XmmReg2_m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8B; XmmReg1 ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { XmmReg2_m128 = vpcompressq_avx512vl( XmmReg1 ); } # VPCOMPRESSQ 5-353 PAGE 2177 LINE 111972 -:VPCOMPRESSQ YmmReg2_m256 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8B; YmmReg1 ... & YmmReg2_m256 +:VPCOMPRESSQ YmmReg2_m256^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8B; YmmReg1 ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { YmmReg2_m256 = vpcompressq_avx512vl( YmmReg1 ); @@ -8759,7 +8759,7 @@ define pcodeop vpcompressq_avx512vl ; # VPCOMPRESSQ 5-353 PAGE 2177 LINE 111974 define pcodeop vpcompressq_avx512f ; -:VPCOMPRESSQ ZmmReg2_m512 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 +:VPCOMPRESSQ ZmmReg2_m512^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x8B; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg2_m512 = vpcompressq_avx512f( ZmmReg1 ); @@ -8767,7 +8767,7 @@ define pcodeop vpcompressq_avx512f ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112068 define pcodeop vpconflictd_avx512vl ; -:VPCONFLICTD XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPCONFLICTD XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpconflictd_avx512vl( XmmReg2_m128_m32bcst ); @@ -8775,7 +8775,7 @@ define pcodeop vpconflictd_avx512vl ; } # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112072 -:VPCONFLICTD YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPCONFLICTD YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpconflictd_avx512vl( YmmReg2_m256_m32bcst ); @@ -8784,7 +8784,7 @@ define pcodeop vpconflictd_avx512vl ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112076 define pcodeop vpconflictd_avx512cd ; -:VPCONFLICTD ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC4; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPCONFLICTD ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xC4; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpconflictd_avx512cd( ZmmReg2_m512_m32bcst ); @@ -8792,7 +8792,7 @@ define pcodeop vpconflictd_avx512cd ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112080 define pcodeop vpconflictq_avx512vl ; -:VPCONFLICTQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPCONFLICTQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC4; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpconflictq_avx512vl( XmmReg2_m128_m64bcst ); @@ -8800,7 +8800,7 @@ define pcodeop vpconflictq_avx512vl ; } # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112084 -:VPCONFLICTQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPCONFLICTQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC4; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpconflictq_avx512vl( YmmReg2_m256_m64bcst ); @@ -8809,7 +8809,7 @@ define pcodeop vpconflictq_avx512vl ; # VPCONFLICTD/Q 5-355 PAGE 2179 LINE 112088 define pcodeop vpconflictq_avx512cd ; -:VPCONFLICTQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC4; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPCONFLICTQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xC4; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpconflictq_avx512cd( ZmmReg2_m512_m64bcst ); @@ -8817,7 +8817,7 @@ define pcodeop vpconflictq_avx512cd ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112407 define pcodeop vpermd_avx512vl ; -:VPERMD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPERMD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpermd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8826,7 +8826,7 @@ define pcodeop vpermd_avx512vl ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112410 define pcodeop vpermd_avx512f ; -:VPERMD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x36; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPERMD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x36; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpermd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8834,7 +8834,7 @@ define pcodeop vpermd_avx512f ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112413 define pcodeop vpermw_avx512vl ; -:VPERMW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPERMW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x8D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpermw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -8842,7 +8842,7 @@ define pcodeop vpermw_avx512vl ; } # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112417 -:VPERMW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPERMW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x8D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpermw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8851,7 +8851,7 @@ define pcodeop vpermw_avx512vl ; # VPERMD/VPERMW 5-362 PAGE 2186 LINE 112421 define pcodeop vpermw_avx512bw ; -:VPERMW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x8D; ZmmReg1 ... & ZmmReg2_m512 +:VPERMW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x8D; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpermw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8859,7 +8859,7 @@ define pcodeop vpermw_avx512bw ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112553 define pcodeop vpermi2w_avx512vl ; -:VPERMI2W XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPERMI2W XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x75; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpermi2w_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 ); @@ -8867,7 +8867,7 @@ define pcodeop vpermi2w_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112556 -:VPERMI2W YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPERMI2W YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x75; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpermi2w_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 ); @@ -8876,7 +8876,7 @@ define pcodeop vpermi2w_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112559 define pcodeop vpermi2w_avx512bw ; -:VPERMI2W ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x75; ZmmReg1 ... & ZmmReg2_m512 +:VPERMI2W ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x75; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpermi2w_avx512bw( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512 ); @@ -8884,7 +8884,7 @@ define pcodeop vpermi2w_avx512bw ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112562 define pcodeop vpermi2d_avx512vl ; -:VPERMI2D XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPERMI2D XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpermi2d_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8892,7 +8892,7 @@ define pcodeop vpermi2d_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112566 -:VPERMI2D YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPERMI2D YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpermi2d_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8901,7 +8901,7 @@ define pcodeop vpermi2d_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112570 define pcodeop vpermi2d_avx512f ; -:VPERMI2D ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x76; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPERMI2D ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x76; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpermi2d_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8909,7 +8909,7 @@ define pcodeop vpermi2d_avx512f ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112574 define pcodeop vpermi2q_avx512vl ; -:VPERMI2Q XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPERMI2Q XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x76; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpermi2q_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8917,7 +8917,7 @@ define pcodeop vpermi2q_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112578 -:VPERMI2Q YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPERMI2Q YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x76; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpermi2q_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8926,7 +8926,7 @@ define pcodeop vpermi2q_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112582 define pcodeop vpermi2q_avx512f ; -:VPERMI2Q ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x76; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPERMI2Q ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x76; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpermi2q_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8934,7 +8934,7 @@ define pcodeop vpermi2q_avx512f ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112586 define pcodeop vpermi2ps_avx512vl ; -:VPERMI2PS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPERMI2PS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpermi2ps_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -8942,7 +8942,7 @@ define pcodeop vpermi2ps_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112590 -:VPERMI2PS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPERMI2PS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpermi2ps_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -8951,7 +8951,7 @@ define pcodeop vpermi2ps_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-365 PAGE 2189 LINE 112594 define pcodeop vpermi2ps_avx512f ; -:VPERMI2PS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x77; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPERMI2PS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x77; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpermi2ps_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -8959,7 +8959,7 @@ define pcodeop vpermi2ps_avx512f ; # VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112610 define pcodeop vpermi2pd_avx512vl ; -:VPERMI2PD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPERMI2PD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x77; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpermi2pd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8967,7 +8967,7 @@ define pcodeop vpermi2pd_avx512vl ; } # VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112614 -:VPERMI2PD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPERMI2PD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x77; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpermi2pd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -8976,7 +8976,7 @@ define pcodeop vpermi2pd_avx512vl ; # VPERMI2W/D/Q/PS/PD 5-366 PAGE 2190 LINE 112618 define pcodeop vpermi2pd_avx512f ; -:VPERMI2PD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x77; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPERMI2PD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x77; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpermi2pd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -8984,7 +8984,7 @@ define pcodeop vpermi2pd_avx512f ; # VPERMILPD 5-371 PAGE 2195 LINE 112866 define pcodeop vpermilpd_avx512vl ; -:VPERMILPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPERMILPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x0D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:16 = vpermilpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -8992,7 +8992,7 @@ define pcodeop vpermilpd_avx512vl ; } # VPERMILPD 5-371 PAGE 2195 LINE 112869 -:VPERMILPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPERMILPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x0D; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vpermilpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9001,14 +9001,14 @@ define pcodeop vpermilpd_avx512vl ; # VPERMILPD 5-371 PAGE 2195 LINE 112872 define pcodeop vpermilpd_avx512f ; -:VPERMILPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x0D; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPERMILPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x0D; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vpermilpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); } # VPERMILPD 5-371 PAGE 2195 LINE 112879 -:VPERMILPD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x05; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VPERMILPD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x05; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { local tmp:16 = vpermilpd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -9016,7 +9016,7 @@ define pcodeop vpermilpd_avx512f ; } # VPERMILPD 5-371 PAGE 2195 LINE 112882 -:VPERMILPD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x05; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VPERMILPD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x05; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { local tmp:32 = vpermilpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -9024,7 +9024,7 @@ define pcodeop vpermilpd_avx512f ; } # VPERMILPD 5-371 PAGE 2195 LINE 112885 -:VPERMILPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x05; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VPERMILPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x05; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { ZmmReg1 = vpermilpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -9032,7 +9032,7 @@ define pcodeop vpermilpd_avx512f ; # VPERMILPS 5-376 PAGE 2200 LINE 113170 define pcodeop vpermilps_avx512vl ; -:VPERMILPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPERMILPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x0C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:16 = vpermilps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9040,7 +9040,7 @@ define pcodeop vpermilps_avx512vl ; } # VPERMILPS 5-376 PAGE 2200 LINE 113173 -:VPERMILPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPERMILPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x0C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vpermilps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9049,14 +9049,14 @@ define pcodeop vpermilps_avx512vl ; # VPERMILPS 5-376 PAGE 2200 LINE 113176 define pcodeop vpermilps_avx512f ; -:VPERMILPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x0C; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPERMILPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x0C; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vpermilps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); } # VPERMILPS 5-376 PAGE 2200 LINE 113179 -:VPERMILPS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VPERMILPS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x04; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { local tmp:16 = vpermilps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -9064,7 +9064,7 @@ define pcodeop vpermilps_avx512f ; } # VPERMILPS 5-376 PAGE 2200 LINE 113182 -:VPERMILPS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VPERMILPS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x04; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { local tmp:32 = vpermilps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -9072,7 +9072,7 @@ define pcodeop vpermilps_avx512f ; } # VPERMILPS 5-376 PAGE 2200 LINE 113186 -:VPERMILPS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x04; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VPERMILPS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x04; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RM) { ZmmReg1 = vpermilps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -9080,7 +9080,7 @@ define pcodeop vpermilps_avx512f ; # VPERMPD 5-381 PAGE 2205 LINE 113456 define pcodeop vpermpd_avx512vl ; -:VPERMPD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x01; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VPERMPD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x01; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { local tmp:32 = vpermpd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -9089,14 +9089,14 @@ define pcodeop vpermpd_avx512vl ; # VPERMPD 5-381 PAGE 2205 LINE 113459 define pcodeop vpermpd_avx512f ; -:VPERMPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x01; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VPERMPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x01; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { ZmmReg1 = vpermpd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); } # VPERMPD 5-381 PAGE 2205 LINE 113462 -:VPERMPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPERMPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vpermpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9104,7 +9104,7 @@ define pcodeop vpermpd_avx512f ; } # VPERMPD 5-381 PAGE 2205 LINE 113465 -:VPERMPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x16; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPERMPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x16; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vpermpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9112,7 +9112,7 @@ define pcodeop vpermpd_avx512f ; # VPERMPS 5-384 PAGE 2208 LINE 113636 define pcodeop vpermps_avx512vl ; -:VPERMPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPERMPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x16; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpermps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9121,7 +9121,7 @@ define pcodeop vpermps_avx512vl ; # VPERMPS 5-384 PAGE 2208 LINE 113639 define pcodeop vpermps_avx512f ; -:VPERMPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x16; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPERMPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x16; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpermps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9129,7 +9129,7 @@ define pcodeop vpermps_avx512f ; # VPERMQ 5-387 PAGE 2211 LINE 113771 define pcodeop vpermq_avx512vl ; -:VPERMQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x00; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VPERMQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x00; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { local tmp:32 = vpermq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -9138,14 +9138,14 @@ define pcodeop vpermq_avx512vl ; # VPERMQ 5-387 PAGE 2211 LINE 113774 define pcodeop vpermq_avx512f ; -:VPERMQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x00; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VPERMQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x00; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RMI) { ZmmReg1 = vpermq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); } # VPERMQ 5-387 PAGE 2211 LINE 113777 -:VPERMQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPERMQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x36; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vpermq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9153,7 +9153,7 @@ define pcodeop vpermq_avx512f ; } # VPERMQ 5-387 PAGE 2211 LINE 113780 -:VPERMQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x36; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPERMQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x36; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vpermq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9161,7 +9161,7 @@ define pcodeop vpermq_avx512f ; # VPEXPANDD 5-390 PAGE 2214 LINE 113945 define pcodeop vpexpandd_avx512vl ; -:VPEXPANDD XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x89; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPEXPANDD XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x89; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpexpandd_avx512vl( XmmReg2_m128 ); @@ -9169,7 +9169,7 @@ define pcodeop vpexpandd_avx512vl ; } # VPEXPANDD 5-390 PAGE 2214 LINE 113948 -:VPEXPANDD YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x89; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPEXPANDD YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x89; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vpexpandd_avx512vl( YmmReg2_m256 ); @@ -9178,7 +9178,7 @@ define pcodeop vpexpandd_avx512vl ; # VPEXPANDD 5-390 PAGE 2214 LINE 113951 define pcodeop vpexpandd_avx512f ; -:VPEXPANDD ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x89; ZmmReg1 ... & ZmmReg2_m512 +:VPEXPANDD ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x89; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vpexpandd_avx512f( ZmmReg2_m512 ); @@ -9186,7 +9186,7 @@ define pcodeop vpexpandd_avx512f ; # VPEXPANDQ 5-392 PAGE 2216 LINE 114033 define pcodeop vpexpandq_avx512vl ; -:VPEXPANDQ XmmReg1 KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x89; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPEXPANDQ XmmReg1^KWriteMask, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x89; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vpexpandq_avx512vl( XmmReg2_m128 ); @@ -9194,7 +9194,7 @@ define pcodeop vpexpandq_avx512vl ; } # VPEXPANDQ 5-392 PAGE 2216 LINE 114035 -:VPEXPANDQ YmmReg1 KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x89; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPEXPANDQ YmmReg1^KWriteMask, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x89; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:32 = vpexpandq_avx512vl( YmmReg2_m256 ); @@ -9203,7 +9203,7 @@ define pcodeop vpexpandq_avx512vl ; # VPEXPANDQ 5-392 PAGE 2216 LINE 114037 define pcodeop vpexpandq_avx512f ; -:VPEXPANDQ ZmmReg1 KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x89; ZmmReg1 ... & ZmmReg2_m512 +:VPEXPANDQ ZmmReg1^KWriteMask, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x89; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { ZmmReg1 = vpexpandq_avx512f( ZmmReg2_m512 ); @@ -9211,7 +9211,7 @@ define pcodeop vpexpandq_avx512f ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114118 define pcodeop vplzcntd_avx512vl ; -:VPLZCNTD XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPLZCNTD XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vplzcntd_avx512vl( XmmReg2_m128_m32bcst ); @@ -9219,7 +9219,7 @@ define pcodeop vplzcntd_avx512vl ; } # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114122 -:VPLZCNTD YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x44; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPLZCNTD YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x44; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vplzcntd_avx512vl( YmmReg2_m256_m32bcst ); @@ -9228,7 +9228,7 @@ define pcodeop vplzcntd_avx512vl ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114126 define pcodeop vplzcntd_avx512cd ; -:VPLZCNTD ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x44; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPLZCNTD ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x44; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vplzcntd_avx512cd( ZmmReg2_m512_m32bcst ); @@ -9236,7 +9236,7 @@ define pcodeop vplzcntd_avx512cd ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114130 define pcodeop vplzcntq_avx512vl ; -:VPLZCNTQ XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPLZCNTQ XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x44; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vplzcntq_avx512vl( XmmReg2_m128_m64bcst ); @@ -9244,7 +9244,7 @@ define pcodeop vplzcntq_avx512vl ; } # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114134 -:VPLZCNTQ YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x44; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPLZCNTQ YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x44; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vplzcntq_avx512vl( YmmReg2_m256_m64bcst ); @@ -9253,7 +9253,7 @@ define pcodeop vplzcntq_avx512vl ; # VPLZCNTD/Q 5-394 PAGE 2218 LINE 114138 define pcodeop vplzcntq_avx512cd ; -:VPLZCNTQ ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x44; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPLZCNTQ ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x44; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vplzcntq_avx512cd( ZmmReg2_m512_m64bcst ); @@ -9430,7 +9430,7 @@ define pcodeop vpmovq2m_avx512dq ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115959 define pcodeop vprolvd_avx512vl ; -:VPROLVD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPROLVD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:16 = vprolvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9439,7 +9439,7 @@ define pcodeop vprolvd_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115962 define pcodeop vprold_avx512vl ; -:VPROLD vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m32bcst; imm8 +:VPROLD vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprold_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -9448,7 +9448,7 @@ define pcodeop vprold_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115965 define pcodeop vprolvq_avx512vl ; -:VPROLVQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPROLVQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x15; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:16 = vprolvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9457,7 +9457,7 @@ define pcodeop vprolvq_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115968 define pcodeop vprolq_avx512vl ; -:VPROLQ vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m64bcst; imm8 +:VPROLQ vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprolq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -9465,7 +9465,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115971 -:VPROLVD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPROLVD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vprolvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9473,7 +9473,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115974 -:VPROLD vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m32bcst; imm8 +:VPROLD vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprold_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -9481,7 +9481,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115977 -:VPROLVQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPROLVQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x15; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vprolvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9489,7 +9489,7 @@ define pcodeop vprolq_avx512vl ; } # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115980 -:VPROLQ vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m64bcst; imm8 +:VPROLQ vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=1 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprolq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -9498,7 +9498,7 @@ define pcodeop vprolq_avx512vl ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115983 define pcodeop vprolvd_avx512f ; -:VPROLVD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPROLVD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vprolvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9506,7 +9506,7 @@ define pcodeop vprolvd_avx512f ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115987 define pcodeop vprold_avx512f ; -:VPROLD evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m32bcst; imm8 +:VPROLD evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { evexV5_ZmmReg = vprold_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -9514,7 +9514,7 @@ define pcodeop vprold_avx512f ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115990 define pcodeop vprolvq_avx512f ; -:VPROLVQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPROLVQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x15; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vprolvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9522,7 +9522,7 @@ define pcodeop vprolvq_avx512f ; # PROLD/PROLVD/PROLQ/PROLVQ 5-430 PAGE 2254 LINE 115993 define pcodeop vprolq_avx512f ; -:VPROLQ evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m64bcst; imm8 +:VPROLQ evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { evexV5_ZmmReg = vprolq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -9530,7 +9530,7 @@ define pcodeop vprolq_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116190 define pcodeop vprorvd_avx512vl ; -:VPRORVD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPRORVD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:16 = vprorvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9539,7 +9539,7 @@ define pcodeop vprorvd_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116194 define pcodeop vprord_avx512vl ; -:VPRORD vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m32bcst; imm8 +:VPRORD vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprord_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -9548,7 +9548,7 @@ define pcodeop vprord_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116197 define pcodeop vprorvq_avx512vl ; -:VPRORVQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPRORVQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x14; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:16 = vprorvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9557,7 +9557,7 @@ define pcodeop vprorvq_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116200 define pcodeop vprorq_avx512vl ; -:VPRORQ vexVVVV_XmmReg KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m64bcst; imm8 +:VPRORQ vexVVVV_XmmReg^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_XmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprorq_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -9565,7 +9565,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116203 -:VPRORVD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPRORVD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vprorvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9573,7 +9573,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116207 -:VPRORD vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m32bcst; imm8 +:VPRORD vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprord_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -9581,7 +9581,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116210 -:VPRORVQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPRORVQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x14; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { local tmp:32 = vprorvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9589,7 +9589,7 @@ define pcodeop vprorq_avx512vl ; } # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116213 -:VPRORQ vexVVVV_YmmReg KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m64bcst; imm8 +:VPRORQ vexVVVV_YmmReg^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & (vexVVVV_YmmReg & vexVVVV_ZmmReg) & KWriteMask; byte=0x72; reg_opcode=0 ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { local tmp:64 = vprorq_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -9598,7 +9598,7 @@ define pcodeop vprorq_avx512vl ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116216 define pcodeop vprorvd_avx512f ; -:VPRORVD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPRORVD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vprorvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9606,7 +9606,7 @@ define pcodeop vprorvd_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116220 define pcodeop vprord_avx512f ; -:VPRORD evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m32bcst; imm8 +:VPRORD evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { evexV5_ZmmReg = vprord_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -9614,7 +9614,7 @@ define pcodeop vprord_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116223 define pcodeop vprorvq_avx512f ; -:VPRORVQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPRORVQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x14; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-RVM) { ZmmReg1 = vprorvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9622,7 +9622,7 @@ define pcodeop vprorvq_avx512f ; # PRORD/PRORVD/PRORQ/PRORVQ 5-435 PAGE 2259 LINE 116226 define pcodeop vprorq_avx512f ; -:VPRORQ evexV5_ZmmReg KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m64bcst; imm8 +:VPRORQ evexV5_ZmmReg^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & evexV5_ZmmReg & KWriteMask; byte=0x72; reg_opcode=0 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV-VMI) { evexV5_ZmmReg = vprorq_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -9631,7 +9631,7 @@ define pcodeop vprorq_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116424 # WARNING: did not recognize qualifier /vsib for "VPSCATTERDD vm32x {k1}, xmm1" define pcodeop vpscatterdd_avx512vl ; -:VPSCATTERDD m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA0; XmmReg1 ... & m32 +:VPSCATTERDD m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA0; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdd_avx512vl( m32, XmmReg1 ); @@ -9640,7 +9640,7 @@ define pcodeop vpscatterdd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116426 # WARNING: did not recognize qualifier /vsib for "VPSCATTERDD vm32y {k1}, ymm1" -:VPSCATTERDD m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA0; YmmReg1 ... & m32 +:VPSCATTERDD m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA0; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdd_avx512vl( m32, YmmReg1 ); @@ -9650,7 +9650,7 @@ define pcodeop vpscatterdd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116428 # WARNING: did not recognize qualifier /vsib for "VPSCATTERDD vm32z {k1}, zmm1" define pcodeop vpscatterdd_avx512f ; -:VPSCATTERDD m32 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA0; ZmmReg1 ... & m32 +:VPSCATTERDD m32^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA0; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdd_avx512f( m32, ZmmReg1 ); @@ -9660,7 +9660,7 @@ define pcodeop vpscatterdd_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116430 # WARNING: did not recognize qualifier /vsib for "VPSCATTERDQ vm32x {k1}, xmm1" define pcodeop vpscatterdq_avx512vl ; -:VPSCATTERDQ m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA0; XmmReg1 ... & m32 +:VPSCATTERDQ m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA0; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdq_avx512vl( m32, XmmReg1 ); @@ -9669,7 +9669,7 @@ define pcodeop vpscatterdq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116432 # WARNING: did not recognize qualifier /vsib for "VPSCATTERDQ vm32x {k1}, ymm1" -:VPSCATTERDQ m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA0; YmmReg1 ... & m32 +:VPSCATTERDQ m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA0; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdq_avx512vl( m32, YmmReg1 ); @@ -9679,7 +9679,7 @@ define pcodeop vpscatterdq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116434 # WARNING: did not recognize qualifier /vsib for "VPSCATTERDQ vm32y {k1}, zmm1" define pcodeop vpscatterdq_avx512f ; -:VPSCATTERDQ m32 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA0; ZmmReg1 ... & m32 +:VPSCATTERDQ m32^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA0; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterdq_avx512f( m32, ZmmReg1 ); @@ -9689,7 +9689,7 @@ define pcodeop vpscatterdq_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116436 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64x {k1}, xmm1" define pcodeop vpscatterqd_avx512vl ; -:VPSCATTERQD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA1; XmmReg1 ... & m64 +:VPSCATTERQD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA1; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqd_avx512vl( m64, XmmReg1 ); @@ -9698,7 +9698,7 @@ define pcodeop vpscatterqd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116438 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64y {k1}, xmm1" -:VPSCATTERQD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA1; XmmReg1 ... & m64 +:VPSCATTERQD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA1; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqd_avx512vl( m64, XmmReg1 ); @@ -9708,7 +9708,7 @@ define pcodeop vpscatterqd_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116440 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQD vm64z {k1}, ymm1" define pcodeop vpscatterqd_avx512f ; -:VPSCATTERQD m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA1; YmmReg1 ... & m64 +:VPSCATTERQD m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA1; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqd_avx512f( m64, YmmReg1 ); @@ -9718,7 +9718,7 @@ define pcodeop vpscatterqd_avx512f ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116442 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64x {k1}, xmm1" define pcodeop vpscatterqq_avx512vl ; -:VPSCATTERQQ m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA1; XmmReg1 ... & m64 +:VPSCATTERQQ m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA1; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqq_avx512vl( m64, XmmReg1 ); @@ -9727,7 +9727,7 @@ define pcodeop vpscatterqq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116444 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64y {k1}, ymm1" -:VPSCATTERQQ m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA1; YmmReg1 ... & m64 +:VPSCATTERQQ m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA1; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqq_avx512vl( m64, YmmReg1 ); @@ -9737,7 +9737,7 @@ define pcodeop vpscatterqq_avx512vl ; # VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ 5-440 PAGE 2264 LINE 116446 # WARNING: did not recognize qualifier /vsib for "VPSCATTERQQ vm64z {k1}, zmm1" define pcodeop vpscatterqq_avx512f ; -:VPSCATTERQQ m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA1; ZmmReg1 ... & m64 +:VPSCATTERQQ m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA1; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vpscatterqq_avx512f( m64, ZmmReg1 ); @@ -9746,7 +9746,7 @@ define pcodeop vpscatterqq_avx512f ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116632 define pcodeop vpsllvw_avx512vl ; -:VPSLLVW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSLLVW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x12; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsllvw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -9754,7 +9754,7 @@ define pcodeop vpsllvw_avx512vl ; } # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116635 -:VPSLLVW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSLLVW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x12; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsllvw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -9763,7 +9763,7 @@ define pcodeop vpsllvw_avx512vl ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116638 define pcodeop vpsllvw_avx512bw ; -:VPSLLVW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x12; ZmmReg1 ... & ZmmReg2_m512 +:VPSLLVW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x12; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsllvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -9771,7 +9771,7 @@ define pcodeop vpsllvw_avx512bw ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116641 define pcodeop vpsllvd_avx512vl ; -:VPSLLVD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPSLLVD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsllvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9779,7 +9779,7 @@ define pcodeop vpsllvd_avx512vl ; } # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116644 -:VPSLLVD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPSLLVD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsllvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9788,7 +9788,7 @@ define pcodeop vpsllvd_avx512vl ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116647 define pcodeop vpsllvd_avx512f ; -:VPSLLVD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x47; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPSLLVD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x47; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsllvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9796,7 +9796,7 @@ define pcodeop vpsllvd_avx512f ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116650 define pcodeop vpsllvq_avx512vl ; -:VPSLLVQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPSLLVQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x47; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsllvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9804,7 +9804,7 @@ define pcodeop vpsllvq_avx512vl ; } # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116653 -:VPSLLVQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPSLLVQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x47; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsllvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9813,7 +9813,7 @@ define pcodeop vpsllvq_avx512vl ; # VPSLLVW/VPSLLVD/VPSLLVQ 5-445 PAGE 2269 LINE 116656 define pcodeop vpsllvq_avx512f ; -:VPSLLVQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x47; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPSLLVQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x47; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsllvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9821,7 +9821,7 @@ define pcodeop vpsllvq_avx512f ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116880 define pcodeop vpsravw_avx512vl ; -:VPSRAVW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x11; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRAVW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x11; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsravw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -9829,7 +9829,7 @@ define pcodeop vpsravw_avx512vl ; } # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116883 -:VPSRAVW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x11; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSRAVW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x11; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsravw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -9838,7 +9838,7 @@ define pcodeop vpsravw_avx512vl ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116886 define pcodeop vpsravw_avx512bw ; -:VPSRAVW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 +:VPSRAVW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x11; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsravw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -9846,7 +9846,7 @@ define pcodeop vpsravw_avx512bw ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116889 define pcodeop vpsravd_avx512vl ; -:VPSRAVD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPSRAVD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsravd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9854,7 +9854,7 @@ define pcodeop vpsravd_avx512vl ; } # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116893 -:VPSRAVD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPSRAVD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsravd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9863,7 +9863,7 @@ define pcodeop vpsravd_avx512vl ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116897 define pcodeop vpsravd_avx512f ; -:VPSRAVD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x46; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPSRAVD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x46; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsravd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9871,7 +9871,7 @@ define pcodeop vpsravd_avx512f ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116901 define pcodeop vpsravq_avx512vl ; -:VPSRAVQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPSRAVQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x46; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsravq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9879,7 +9879,7 @@ define pcodeop vpsravq_avx512vl ; } # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116905 -:VPSRAVQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPSRAVQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x46; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsravq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9888,7 +9888,7 @@ define pcodeop vpsravq_avx512vl ; # VPSRAVW/VPSRAVD/VPSRAVQ 5-450 PAGE 2274 LINE 116910 define pcodeop vpsravq_avx512f ; -:VPSRAVQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x46; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPSRAVQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x46; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsravq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9896,7 +9896,7 @@ define pcodeop vpsravq_avx512f ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117151 define pcodeop vpsrlvw_avx512vl ; -:VPSRLVW XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 +:VPSRLVW XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x10; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:16 = vpsrlvw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); @@ -9904,7 +9904,7 @@ define pcodeop vpsrlvw_avx512vl ; } # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117154 -:VPSRLVW YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 +:VPSRLVW YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x10; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { local tmp:32 = vpsrlvw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -9913,7 +9913,7 @@ define pcodeop vpsrlvw_avx512vl ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117157 define pcodeop vpsrlvw_avx512bw ; -:VPSRLVW ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x10; ZmmReg1 ... & ZmmReg2_m512 +:VPSRLVW ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x10; ZmmReg1 ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { ZmmReg1 = vpsrlvw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -9921,7 +9921,7 @@ define pcodeop vpsrlvw_avx512bw ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117160 define pcodeop vpsrlvd_avx512vl ; -:VPSRLVD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VPSRLVD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsrlvd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -9929,7 +9929,7 @@ define pcodeop vpsrlvd_avx512vl ; } # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117163 -:VPSRLVD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VPSRLVD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsrlvd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -9938,7 +9938,7 @@ define pcodeop vpsrlvd_avx512vl ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117166 define pcodeop vpsrlvd_avx512f ; -:VPSRLVD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x45; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VPSRLVD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x45; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsrlvd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -9946,7 +9946,7 @@ define pcodeop vpsrlvd_avx512f ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117169 define pcodeop vpsrlvq_avx512vl ; -:VPSRLVQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VPSRLVQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x45; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpsrlvq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -9954,7 +9954,7 @@ define pcodeop vpsrlvq_avx512vl ; } # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117172 -:VPSRLVQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VPSRLVQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x45; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpsrlvq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -9963,7 +9963,7 @@ define pcodeop vpsrlvq_avx512vl ; # VPSRLVW/VPSRLVD/VPSRLVQ 5-455 PAGE 2279 LINE 117175 define pcodeop vpsrlvq_avx512f ; -:VPSRLVQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x45; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VPSRLVQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x45; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpsrlvq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -9971,7 +9971,7 @@ define pcodeop vpsrlvq_avx512f ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117395 define pcodeop vpternlogd_avx512vl ; -:VPTERNLOGD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VPTERNLOGD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpternlogd_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -9979,7 +9979,7 @@ define pcodeop vpternlogd_avx512vl ; } # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117400 -:VPTERNLOGD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VPTERNLOGD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpternlogd_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -9988,7 +9988,7 @@ define pcodeop vpternlogd_avx512vl ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117405 define pcodeop vpternlogd_avx512f ; -:VPTERNLOGD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x25; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VPTERNLOGD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x25; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpternlogd_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -9996,7 +9996,7 @@ define pcodeop vpternlogd_avx512f ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117410 define pcodeop vpternlogq_avx512vl ; -:VPTERNLOGQ XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VPTERNLOGQ XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x25; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vpternlogq_avx512vl( XmmReg1, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -10004,7 +10004,7 @@ define pcodeop vpternlogq_avx512vl ; } # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117415 -:VPTERNLOGQ YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VPTERNLOGQ YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x25; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vpternlogq_avx512vl( YmmReg1, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -10013,7 +10013,7 @@ define pcodeop vpternlogq_avx512vl ; # VPTERNLOGD/VPTERNLOGQ 5-460 PAGE 2284 LINE 117420 define pcodeop vpternlogq_avx512f ; -:VPTERNLOGQ ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x25; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VPTERNLOGQ ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x25; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vpternlogq_avx512f( ZmmReg1, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -10021,14 +10021,14 @@ define pcodeop vpternlogq_avx512f ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117559 define pcodeop vptestmb_avx512vl ; -:VPTESTMB KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 +:VPTESTMB KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestmb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117562 -:VPTESTMB KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 +:VPTESTMB KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestmb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10036,7 +10036,7 @@ define pcodeop vptestmb_avx512vl ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117565 define pcodeop vptestmb_avx512bw ; -:VPTESTMB KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 +:VPTESTMB KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestmb_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10044,14 +10044,14 @@ define pcodeop vptestmb_avx512bw ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117568 define pcodeop vptestmw_avx512vl ; -:VPTESTMW KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 +:VPTESTMW KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestmw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117571 -:VPTESTMW KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 +:VPTESTMW KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestmw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10059,7 +10059,7 @@ define pcodeop vptestmw_avx512vl ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117574 define pcodeop vptestmw_avx512bw ; -:VPTESTMW KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 +:VPTESTMW KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestmw_avx512bw( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10067,14 +10067,14 @@ define pcodeop vptestmw_avx512bw ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117577 define pcodeop vptestmd_avx512vl ; -:VPTESTMD KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst +:VPTESTMD KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestmd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); } # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117581 -:VPTESTMD KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst +:VPTESTMD KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestmd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10082,7 +10082,7 @@ define pcodeop vptestmd_avx512vl ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117585 define pcodeop vptestmd_avx512f ; -:VPTESTMD KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst +:VPTESTMD KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10090,14 +10090,14 @@ define pcodeop vptestmd_avx512f ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117589 define pcodeop vptestmq_avx512vl ; -:VPTESTMQ KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst +:VPTESTMQ KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestmq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); } # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117593 -:VPTESTMQ KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst +:VPTESTMQ KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestmq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10105,7 +10105,7 @@ define pcodeop vptestmq_avx512vl ; # VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ 5-463 PAGE 2287 LINE 117597 define pcodeop vptestmq_avx512f ; -:VPTESTMQ KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst +:VPTESTMQ KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10113,14 +10113,14 @@ define pcodeop vptestmq_avx512f ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117717 define pcodeop vptestnmb_avx512vl ; -:VPTESTNMB KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 +:VPTESTNMB KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestnmb_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117721 -:VPTESTNMB KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 +:VPTESTNMB KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestnmb_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10128,7 +10128,7 @@ define pcodeop vptestnmb_avx512vl ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117725 define pcodeop vptestnmb_avx512f ; -:VPTESTNMB KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 +:VPTESTNMB KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestnmb_avx512f( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10136,14 +10136,14 @@ define pcodeop vptestnmb_avx512f ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117729 define pcodeop vptestnmw_avx512vl ; -:VPTESTNMW KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 +:VPTESTNMW KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x26; KReg_reg ... & XmmReg2_m128 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestnmw_avx512vl( vexVVVV_XmmReg, XmmReg2_m128 ); } # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117733 -:VPTESTNMW KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 +:VPTESTNMW KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x26; KReg_reg ... & YmmReg2_m256 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestnmw_avx512vl( vexVVVV_YmmReg, YmmReg2_m256 ); @@ -10151,7 +10151,7 @@ define pcodeop vptestnmw_avx512vl ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117737 define pcodeop vptestnmw_avx512f ; -:VPTESTNMW KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 +:VPTESTNMW KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x26; KReg_reg ... & ZmmReg2_m512 [ evexD8Type = 1; evexTType = 0; ] # (TupleType FVM) { KReg_reg = vptestnmw_avx512f( evexV5_ZmmReg, ZmmReg2_m512 ); @@ -10159,14 +10159,14 @@ define pcodeop vptestnmw_avx512f ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117741 define pcodeop vptestnmd_avx512vl ; -:VPTESTNMD KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst +:VPTESTNMD KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestnmd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); } # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117745 -:VPTESTNMD KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst +:VPTESTNMD KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestnmd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10174,7 +10174,7 @@ define pcodeop vptestnmd_avx512vl ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117749 define pcodeop vptestnmd_avx512f ; -:VPTESTNMD KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst +:VPTESTNMD KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestnmd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10182,14 +10182,14 @@ define pcodeop vptestnmd_avx512f ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117753 define pcodeop vptestnmq_avx512vl ; -:VPTESTNMQ KReg_reg KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst +:VPTESTNMQ KReg_reg^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x27; KReg_reg ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestnmq_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); } # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117757 -:VPTESTNMQ KReg_reg KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst +:VPTESTNMQ KReg_reg^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x27; KReg_reg ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestnmq_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10197,7 +10197,7 @@ define pcodeop vptestnmq_avx512vl ; # VPTESTNMB/W/D/Q 5-466 PAGE 2290 LINE 117761 define pcodeop vptestnmq_avx512f ; -:VPTESTNMQ KReg_reg KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst +:VPTESTNMQ KReg_reg^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x27; KReg_reg ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { KReg_reg = vptestnmq_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10205,7 +10205,7 @@ define pcodeop vptestnmq_avx512f ; # VRANGEPD 5-470 PAGE 2294 LINE 117905 define pcodeop vrangepd_avx512vl ; -:VRANGEPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VRANGEPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrangepd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst, imm8:1 ); @@ -10213,7 +10213,7 @@ define pcodeop vrangepd_avx512vl ; } # VRANGEPD 5-470 PAGE 2294 LINE 117910 -:VRANGEPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VRANGEPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrangepd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst, imm8:1 ); @@ -10222,7 +10222,7 @@ define pcodeop vrangepd_avx512vl ; # VRANGEPD 5-470 PAGE 2294 LINE 117915 define pcodeop vrangepd_avx512dq ; -:VRANGEPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x50; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VRANGEPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x50; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrangepd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst, imm8:1 ); @@ -10230,7 +10230,7 @@ define pcodeop vrangepd_avx512dq ; # VRANGEPS 5-475 PAGE 2299 LINE 118139 define pcodeop vrangeps_avx512vl ; -:VRANGEPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VRANGEPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x50; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrangeps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst, imm8:1 ); @@ -10238,7 +10238,7 @@ define pcodeop vrangeps_avx512vl ; } # VRANGEPS 5-475 PAGE 2299 LINE 118144 -:VRANGEPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VRANGEPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x50; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrangeps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst, imm8:1 ); @@ -10247,7 +10247,7 @@ define pcodeop vrangeps_avx512vl ; # VRANGEPS 5-475 PAGE 2299 LINE 118149 define pcodeop vrangeps_avx512dq ; -:VRANGEPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x50; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VRANGEPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x50; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrangeps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst, imm8:1 ); @@ -10255,7 +10255,7 @@ define pcodeop vrangeps_avx512dq ; # VRANGESD 5-479 PAGE 2303 LINE 118318 define pcodeop vrangesd_avx512dq ; -:VRANGESD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8 +:VRANGESD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrangesd_avx512dq( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); @@ -10264,7 +10264,7 @@ define pcodeop vrangesd_avx512dq ; # VRANGESS 5-482 PAGE 2306 LINE 118473 define pcodeop vrangess_avx512dq ; -:VRANGESS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VRANGESS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x51; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrangess_avx512dq( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10273,7 +10273,7 @@ define pcodeop vrangess_avx512dq ; # VRCP14PD 5-485 PAGE 2309 LINE 118626 define pcodeop vrcp14pd_avx512vl ; -:VRCP14PD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VRCP14PD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrcp14pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -10281,7 +10281,7 @@ define pcodeop vrcp14pd_avx512vl ; } # VRCP14PD 5-485 PAGE 2309 LINE 118629 -:VRCP14PD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VRCP14PD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrcp14pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -10290,7 +10290,7 @@ define pcodeop vrcp14pd_avx512vl ; # VRCP14PD 5-485 PAGE 2309 LINE 118632 define pcodeop vrcp14pd_avx512f ; -:VRCP14PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4C; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VRCP14PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4C; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrcp14pd_avx512f( ZmmReg2_m512_m64bcst ); @@ -10298,7 +10298,7 @@ define pcodeop vrcp14pd_avx512f ; # VRCP14SD 5-487 PAGE 2311 LINE 118726 define pcodeop vrcp14sd_avx512f ; -:VRCP14SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VRCP14SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrcp14sd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -10307,7 +10307,7 @@ define pcodeop vrcp14sd_avx512f ; # VRCP14PS 5-489 PAGE 2313 LINE 118800 define pcodeop vrcp14ps_avx512vl ; -:VRCP14PS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VRCP14PS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrcp14ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -10315,7 +10315,7 @@ define pcodeop vrcp14ps_avx512vl ; } # VRCP14PS 5-489 PAGE 2313 LINE 118803 -:VRCP14PS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VRCP14PS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrcp14ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -10324,7 +10324,7 @@ define pcodeop vrcp14ps_avx512vl ; # VRCP14PS 5-489 PAGE 2313 LINE 118806 define pcodeop vrcp14ps_avx512f ; -:VRCP14PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4C; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VRCP14PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4C; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrcp14ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -10332,7 +10332,7 @@ define pcodeop vrcp14ps_avx512f ; # VRCP14SS 5-491 PAGE 2315 LINE 118904 define pcodeop vrcp14ss_avx512f ; -:VRCP14SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VRCP14SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x4D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrcp14ss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10341,7 +10341,7 @@ define pcodeop vrcp14ss_avx512f ; # VRCP28PD 5-493 PAGE 2317 LINE 118979 define pcodeop vrcp28pd_avx512er ; -:VRCP28PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xCA; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VRCP28PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xCA; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrcp28pd_avx512er( ZmmReg2_m512_m64bcst ); @@ -10349,7 +10349,7 @@ define pcodeop vrcp28pd_avx512er ; # VRCP28SD 5-495 PAGE 2319 LINE 119074 define pcodeop vrcp28sd_avx512er ; -:VRCP28SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VRCP28SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrcp28sd_avx512er( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -10358,7 +10358,7 @@ define pcodeop vrcp28sd_avx512er ; # VRCP28PS 5-497 PAGE 2321 LINE 119167 define pcodeop vrcp28ps_avx512er ; -:VRCP28PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xCA; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VRCP28PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xCA; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrcp28ps_avx512er( ZmmReg2_m512_m32bcst ); @@ -10366,7 +10366,7 @@ define pcodeop vrcp28ps_avx512er ; # VRCP28SS 5-499 PAGE 2323 LINE 119263 define pcodeop vrcp28ss_avx512er ; -:VRCP28SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VRCP28SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xCB; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrcp28ss_avx512er( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10375,7 +10375,7 @@ define pcodeop vrcp28ss_avx512er ; # VREDUCEPD 5-501 PAGE 2325 LINE 119356 define pcodeop vreducepd_avx512vl ; -:VREDUCEPD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VREDUCEPD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vreducepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -10383,7 +10383,7 @@ define pcodeop vreducepd_avx512vl ; } # VREDUCEPD 5-501 PAGE 2325 LINE 119360 -:VREDUCEPD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VREDUCEPD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vreducepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -10392,7 +10392,7 @@ define pcodeop vreducepd_avx512vl ; # VREDUCEPD 5-501 PAGE 2325 LINE 119364 define pcodeop vreducepd_avx512dq ; -:VREDUCEPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VREDUCEPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vreducepd_avx512dq( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -10400,7 +10400,7 @@ define pcodeop vreducepd_avx512dq ; # VREDUCESD 5-504 PAGE 2328 LINE 119510 define pcodeop vreducesd_avx512dq ; -:VREDUCESD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VREDUCESD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vreducesd_avx512dq( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -10409,7 +10409,7 @@ define pcodeop vreducesd_avx512dq ; # VREDUCEPS 5-506 PAGE 2330 LINE 119605 define pcodeop vreduceps_avx512vl ; -:VREDUCEPS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VREDUCEPS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x56; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vreduceps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -10417,7 +10417,7 @@ define pcodeop vreduceps_avx512vl ; } # VREDUCEPS 5-506 PAGE 2330 LINE 119609 -:VREDUCEPS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VREDUCEPS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x56; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vreduceps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -10426,7 +10426,7 @@ define pcodeop vreduceps_avx512vl ; # VREDUCEPS 5-506 PAGE 2330 LINE 119613 define pcodeop vreduceps_avx512dq ; -:VREDUCEPS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VREDUCEPS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x56; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vreduceps_avx512dq( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -10434,7 +10434,7 @@ define pcodeop vreduceps_avx512dq ; # VREDUCESS 5-508 PAGE 2332 LINE 119719 define pcodeop vreducess_avx512dq ; -:VREDUCESS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VREDUCESS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vreducess_avx512dq( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10443,7 +10443,7 @@ define pcodeop vreducess_avx512dq ; # VRNDSCALEPD 5-510 PAGE 2334 LINE 119814 define pcodeop vrndscalepd_avx512vl ; -:VRNDSCALEPD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x09; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 +:VRNDSCALEPD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x09; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrndscalepd_avx512vl( XmmReg2_m128_m64bcst, imm8:1 ); @@ -10451,7 +10451,7 @@ define pcodeop vrndscalepd_avx512vl ; } # VRNDSCALEPD 5-510 PAGE 2334 LINE 119818 -:VRNDSCALEPD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x09; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 +:VRNDSCALEPD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x09; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrndscalepd_avx512vl( YmmReg2_m256_m64bcst, imm8:1 ); @@ -10460,7 +10460,7 @@ define pcodeop vrndscalepd_avx512vl ; # VRNDSCALEPD 5-510 PAGE 2334 LINE 119822 define pcodeop vrndscalepd_avx512f ; -:VRNDSCALEPD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x09; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 +:VRNDSCALEPD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask; byte=0x09; ZmmReg1 ... & ZmmReg2_m512_m64bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrndscalepd_avx512f( ZmmReg2_m512_m64bcst, imm8:1 ); @@ -10468,7 +10468,7 @@ define pcodeop vrndscalepd_avx512f ; # VRNDSCALESD 5-514 PAGE 2338 LINE 119998 define pcodeop vrndscalesd_avx512f ; -:VRNDSCALESD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8 +:VRNDSCALESD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64, imm8 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x0B; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64; imm8 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrndscalesd_avx512f( vexVVVV_XmmReg, XmmReg2_m64, imm8:1 ); @@ -10477,7 +10477,7 @@ define pcodeop vrndscalesd_avx512f ; # VRNDSCALEPS 5-516 PAGE 2340 LINE 120116 define pcodeop vrndscaleps_avx512vl ; -:VRNDSCALEPS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 +:VRNDSCALEPS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x08; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrndscaleps_avx512vl( XmmReg2_m128_m32bcst, imm8:1 ); @@ -10485,7 +10485,7 @@ define pcodeop vrndscaleps_avx512vl ; } # VRNDSCALEPS 5-516 PAGE 2340 LINE 120120 -:VRNDSCALEPS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 +:VRNDSCALEPS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x08; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrndscaleps_avx512vl( YmmReg2_m256_m32bcst, imm8:1 ); @@ -10494,7 +10494,7 @@ define pcodeop vrndscaleps_avx512vl ; # VRNDSCALEPS 5-516 PAGE 2340 LINE 120124 define pcodeop vrndscaleps_avx512f ; -:VRNDSCALEPS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x08; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 +:VRNDSCALEPS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x08; ZmmReg1 ... & ZmmReg2_m512_m32bcst; imm8 [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrndscaleps_avx512f( ZmmReg2_m512_m32bcst, imm8:1 ); @@ -10502,7 +10502,7 @@ define pcodeop vrndscaleps_avx512f ; # VRNDSCALESS 5-519 PAGE 2343 LINE 120263 define pcodeop vrndscaless_avx512f ; -:VRNDSCALESS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VRNDSCALESS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x0A; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrndscaless_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10511,7 +10511,7 @@ define pcodeop vrndscaless_avx512f ; # VRSQRT14PD 5-521 PAGE 2345 LINE 120381 define pcodeop vrsqrt14pd_avx512vl ; -:VRSQRT14PD XmmReg1 KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VRSQRT14PD XmmReg1^KWriteMask, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrsqrt14pd_avx512vl( XmmReg2_m128_m64bcst ); @@ -10519,7 +10519,7 @@ define pcodeop vrsqrt14pd_avx512vl ; } # VRSQRT14PD 5-521 PAGE 2345 LINE 120385 -:VRSQRT14PD YmmReg1 KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VRSQRT14PD YmmReg1^KWriteMask, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrsqrt14pd_avx512vl( YmmReg2_m256_m64bcst ); @@ -10528,7 +10528,7 @@ define pcodeop vrsqrt14pd_avx512vl ; # VRSQRT14PD 5-521 PAGE 2345 LINE 120389 define pcodeop vrsqrt14pd_avx512f ; -:VRSQRT14PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4E; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VRSQRT14PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0x4E; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrsqrt14pd_avx512f( ZmmReg2_m512_m64bcst ); @@ -10536,7 +10536,7 @@ define pcodeop vrsqrt14pd_avx512f ; # VRSQRT14SD 5-523 PAGE 2347 LINE 120491 define pcodeop vrsqrt14sd_avx512f ; -:VRSQRT14SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VRSQRT14SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrsqrt14sd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -10545,7 +10545,7 @@ define pcodeop vrsqrt14sd_avx512f ; # VRSQRT14PS 5-525 PAGE 2349 LINE 120578 define pcodeop vrsqrt14ps_avx512vl ; -:VRSQRT14PS XmmReg1 KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VRSQRT14PS XmmReg1^KWriteMask, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4E; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vrsqrt14ps_avx512vl( XmmReg2_m128_m32bcst ); @@ -10553,7 +10553,7 @@ define pcodeop vrsqrt14ps_avx512vl ; } # VRSQRT14PS 5-525 PAGE 2349 LINE 120582 -:VRSQRT14PS YmmReg1 KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VRSQRT14PS YmmReg1^KWriteMask, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4E; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vrsqrt14ps_avx512vl( YmmReg2_m256_m32bcst ); @@ -10562,7 +10562,7 @@ define pcodeop vrsqrt14ps_avx512vl ; # VRSQRT14PS 5-525 PAGE 2349 LINE 120586 define pcodeop vrsqrt14ps_avx512f ; -:VRSQRT14PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4E; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VRSQRT14PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x4E; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrsqrt14ps_avx512f( ZmmReg2_m512_m32bcst ); @@ -10570,7 +10570,7 @@ define pcodeop vrsqrt14ps_avx512f ; # VRSQRT14SS 5-527 PAGE 2351 LINE 120690 define pcodeop vrsqrt14ss_avx512f ; -:VRSQRT14SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VRSQRT14SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x4F; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrsqrt14ss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10579,7 +10579,7 @@ define pcodeop vrsqrt14ss_avx512f ; # VRSQRT28PD 5-529 PAGE 2353 LINE 120778 define pcodeop vrsqrt28pd_avx512er ; -:VRSQRT28PD ZmmReg1 KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xCC; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VRSQRT28PD ZmmReg1^KWriteMask, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xCC; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrsqrt28pd_avx512er( ZmmReg2_m512_m64bcst ); @@ -10587,7 +10587,7 @@ define pcodeop vrsqrt28pd_avx512er ; # VRSQRT28SD 5-531 PAGE 2355 LINE 120869 define pcodeop vrsqrt28sd_avx512er ; -:VRSQRT28SD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VRSQRT28SD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrsqrt28sd_avx512er( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -10596,7 +10596,7 @@ define pcodeop vrsqrt28sd_avx512er ; # VRSQRT28PS 5-533 PAGE 2357 LINE 120959 define pcodeop vrsqrt28ps_avx512er ; -:VRSQRT28PS ZmmReg1 KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xCC; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VRSQRT28PS ZmmReg1^KWriteMask, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xCC; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vrsqrt28ps_avx512er( ZmmReg2_m512_m32bcst ); @@ -10604,7 +10604,7 @@ define pcodeop vrsqrt28ps_avx512er ; # VRSQRT28SS 5-535 PAGE 2359 LINE 121051 define pcodeop vrsqrt28ss_avx512er ; -:VRSQRT28SS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VRSQRT28SS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0xCD; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vrsqrt28ss_avx512er( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10613,7 +10613,7 @@ define pcodeop vrsqrt28ss_avx512er ; # VSCALEFPD 5-537 PAGE 2361 LINE 121140 define pcodeop vscalefpd_avx512vl ; -:VSCALEFPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VSCALEFPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vscalefpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -10621,7 +10621,7 @@ define pcodeop vscalefpd_avx512vl ; } # VSCALEFPD 5-537 PAGE 2361 LINE 121143 -:VSCALEFPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VSCALEFPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vscalefpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10630,7 +10630,7 @@ define pcodeop vscalefpd_avx512vl ; # VSCALEFPD 5-537 PAGE 2361 LINE 121146 define pcodeop vscalefpd_avx512f ; -:VSCALEFPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x2C; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VSCALEFPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x2C; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vscalefpd_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10638,7 +10638,7 @@ define pcodeop vscalefpd_avx512f ; # VSCALEFSD 5-540 PAGE 2364 LINE 121269 define pcodeop vscalefsd_avx512f ; -:VSCALEFSD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 +:VSCALEFSD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m64 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vscalefsd_avx512f( vexVVVV_XmmReg, XmmReg2_m64 ); @@ -10647,7 +10647,7 @@ define pcodeop vscalefsd_avx512f ; # VSCALEFPS 5-542 PAGE 2366 LINE 121355 define pcodeop vscalefps_avx512vl ; -:VSCALEFPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VSCALEFPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x2C; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vscalefps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -10655,7 +10655,7 @@ define pcodeop vscalefps_avx512vl ; } # VSCALEFPS 5-542 PAGE 2366 LINE 121358 -:VSCALEFPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VSCALEFPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x2C; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vscalefps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10664,7 +10664,7 @@ define pcodeop vscalefps_avx512vl ; # VSCALEFPS 5-542 PAGE 2366 LINE 121361 define pcodeop vscalefps_avx512f ; -:VSCALEFPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x2C; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VSCALEFPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x2C; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vscalefps_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10672,7 +10672,7 @@ define pcodeop vscalefps_avx512f ; # VSCALEFSS 5-544 PAGE 2368 LINE 121470 define pcodeop vscalefss_avx512f ; -:VSCALEFSS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 +:VSCALEFSS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m32 is $(EVEX_NONE) & $(VEX_LIG) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x2D; (XmmReg1 & ZmmReg1) ... & XmmReg2_m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { local tmp:16 = vscalefss_avx512f( vexVVVV_XmmReg, XmmReg2_m32 ); @@ -10682,7 +10682,7 @@ define pcodeop vscalefss_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121559 # WARNING: did not recognize qualifier /vsib for "VSCATTERDPS vm32x {k1}, xmm1" define pcodeop vscatterdps_avx512vl ; -:VSCATTERDPS m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA2; XmmReg1 ... & m32 +:VSCATTERDPS m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA2; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdps_avx512vl( m32, XmmReg1 ); @@ -10691,7 +10691,7 @@ define pcodeop vscatterdps_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121561 # WARNING: did not recognize qualifier /vsib for "VSCATTERDPS vm32y {k1}, ymm1" -:VSCATTERDPS m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA2; YmmReg1 ... & m32 +:VSCATTERDPS m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA2; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdps_avx512vl( m32, YmmReg1 ); @@ -10701,7 +10701,7 @@ define pcodeop vscatterdps_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121563 # WARNING: did not recognize qualifier /vsib for "VSCATTERDPS vm32z {k1}, zmm1" define pcodeop vscatterdps_avx512f ; -:VSCATTERDPS m32 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA2; ZmmReg1 ... & m32 +:VSCATTERDPS m32^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA2; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdps_avx512f( m32, ZmmReg1 ); @@ -10711,7 +10711,7 @@ define pcodeop vscatterdps_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121565 # WARNING: did not recognize qualifier /vsib for "VSCATTERDPD vm32x {k1}, xmm1" define pcodeop vscatterdpd_avx512vl ; -:VSCATTERDPD m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA2; XmmReg1 ... & m32 +:VSCATTERDPD m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA2; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdpd_avx512vl( m32, XmmReg1 ); @@ -10720,7 +10720,7 @@ define pcodeop vscatterdpd_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121567 # WARNING: did not recognize qualifier /vsib for "VSCATTERDPD vm32x {k1}, ymm1" -:VSCATTERDPD m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA2; YmmReg1 ... & m32 +:VSCATTERDPD m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA2; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdpd_avx512vl( m32, YmmReg1 ); @@ -10730,7 +10730,7 @@ define pcodeop vscatterdpd_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121569 # WARNING: did not recognize qualifier /vsib for "VSCATTERDPD vm32y {k1}, zmm1" define pcodeop vscatterdpd_avx512f ; -:VSCATTERDPD m32 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA2; ZmmReg1 ... & m32 +:VSCATTERDPD m32^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA2; ZmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterdpd_avx512f( m32, ZmmReg1 ); @@ -10740,7 +10740,7 @@ define pcodeop vscatterdpd_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121571 # WARNING: did not recognize qualifier /vsib for "VSCATTERQPS vm64x {k1}, xmm1" define pcodeop vscatterqps_avx512vl ; -:VSCATTERQPS m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA3; XmmReg1 ... & m64 +:VSCATTERQPS m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA3; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqps_avx512vl( m64, XmmReg1 ); @@ -10749,7 +10749,7 @@ define pcodeop vscatterqps_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121573 # WARNING: did not recognize qualifier /vsib for "VSCATTERQPS vm64y {k1}, xmm1" -:VSCATTERQPS m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA3; XmmReg1 ... & m64 +:VSCATTERQPS m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA3; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqps_avx512vl( m64, XmmReg1 ); @@ -10759,7 +10759,7 @@ define pcodeop vscatterqps_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121575 # WARNING: did not recognize qualifier /vsib for "VSCATTERQPS vm64z {k1}, ymm1" define pcodeop vscatterqps_avx512f ; -:VSCATTERQPS m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA3; YmmReg1 ... & m64 +:VSCATTERQPS m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0xA3; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqps_avx512f( m64, YmmReg1 ); @@ -10769,7 +10769,7 @@ define pcodeop vscatterqps_avx512f ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121577 # WARNING: did not recognize qualifier /vsib for "VSCATTERQPD vm64x {k1}, xmm1" define pcodeop vscatterqpd_avx512vl ; -:VSCATTERQPD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA3; XmmReg1 ... & m64 +:VSCATTERQPD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA3; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqpd_avx512vl( m64, XmmReg1 ); @@ -10778,7 +10778,7 @@ define pcodeop vscatterqpd_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121579 # WARNING: did not recognize qualifier /vsib for "VSCATTERQPD vm64y {k1}, ymm1" -:VSCATTERQPD m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA3; YmmReg1 ... & m64 +:VSCATTERQPD m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA3; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqpd_avx512vl( m64, YmmReg1 ); @@ -10788,7 +10788,7 @@ define pcodeop vscatterqpd_avx512vl ; # VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD 5-546 PAGE 2370 LINE 121581 # WARNING: did not recognize qualifier /vsib for "VSCATTERQPD vm64z {k1}, zmm1" define pcodeop vscatterqpd_avx512f ; -:VSCATTERQPD m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA3; ZmmReg1 ... & m64 +:VSCATTERQPD m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_W1) & KWriteMask; byte=0xA3; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 3; ] # (TupleType T1S) { vscatterqpd_avx512f( m64, ZmmReg1 ); @@ -10877,7 +10877,7 @@ define pcodeop vscatterpf1qpd_avx512pf ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121994 define pcodeop vshuff32x4_avx512vl ; -:VSHUFF32X4 YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VSHUFF32X4 YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vshuff32x4_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10886,7 +10886,7 @@ define pcodeop vshuff32x4_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 121998 define pcodeop vshuff32x4_avx512f ; -:VSHUFF32x4 ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x23; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VSHUFF32x4 ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x23; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vshuff32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10894,7 +10894,7 @@ define pcodeop vshuff32x4_avx512f ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122002 define pcodeop vshuff64x2_avx512vl ; -:VSHUFF64X2 YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VSHUFF64X2 YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x23; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vshuff64x2_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10903,7 +10903,7 @@ define pcodeop vshuff64x2_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122006 define pcodeop vshuff64x2_avx512f ; -:VSHUFF64x2 ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x23; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VSHUFF64x2 ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x23; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vshuff64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10911,7 +10911,7 @@ define pcodeop vshuff64x2_avx512f ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122010 define pcodeop vshufi32x4_avx512vl ; -:VSHUFI32X4 YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VSHUFI32X4 YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vshufi32x4_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10920,7 +10920,7 @@ define pcodeop vshufi32x4_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122013 define pcodeop vshufi32x4_avx512f ; -:VSHUFI32x4 ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x43; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VSHUFI32x4 ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x43; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vshufi32x4_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); @@ -10928,7 +10928,7 @@ define pcodeop vshufi32x4_avx512f ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122016 define pcodeop vshufi64x2_avx512vl ; -:VSHUFI64X2 YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VSHUFI64X2 YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x43; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vshufi64x2_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10937,7 +10937,7 @@ define pcodeop vshufi64x2_avx512vl ; # VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 5-555 PAGE 2379 LINE 122019 define pcodeop vshufi64x2_avx512f ; -:VSHUFI64x2 ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x43; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VSHUFI64x2 ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x43; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vshufi64x2_avx512f( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10945,7 +10945,7 @@ define pcodeop vshufi64x2_avx512f ; # XORPD 5-596 PAGE 2420 LINE 123834 define pcodeop vxorpd_avx512vl ; -:VXORPD XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst +:VXORPD XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m64bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vxorpd_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m64bcst ); @@ -10953,7 +10953,7 @@ define pcodeop vxorpd_avx512vl ; } # XORPD 5-596 PAGE 2420 LINE 123837 -:VXORPD YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst +:VXORPD YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m64bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vxorpd_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m64bcst ); @@ -10962,7 +10962,7 @@ define pcodeop vxorpd_avx512vl ; # XORPD 5-596 PAGE 2420 LINE 123840 define pcodeop vxorpd_avx512dq ; -:VXORPD ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x57; ZmmReg1 ... & ZmmReg2_m512_m64bcst +:VXORPD ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m64bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W1) & KWriteMask & evexV5_ZmmReg; byte=0x57; ZmmReg1 ... & ZmmReg2_m512_m64bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vxorpd_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m64bcst ); @@ -10970,7 +10970,7 @@ define pcodeop vxorpd_avx512dq ; # XORPS 5-599 PAGE 2423 LINE 123959 define pcodeop vxorps_avx512vl ; -:VXORPS XmmReg1 KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst +:VXORPS XmmReg1^KWriteMask, vexVVVV_XmmReg, XmmReg2_m128_m32bcst is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_XmmReg; byte=0x57; (XmmReg1 & ZmmReg1) ... & XmmReg2_m128_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:16 = vxorps_avx512vl( vexVVVV_XmmReg, XmmReg2_m128_m32bcst ); @@ -10978,7 +10978,7 @@ define pcodeop vxorps_avx512vl ; } # XORPS 5-599 PAGE 2423 LINE 123962 -:VXORPS YmmReg1 KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst +:VXORPS YmmReg1^KWriteMask, vexVVVV_YmmReg, YmmReg2_m256_m32bcst is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & vexVVVV_YmmReg; byte=0x57; (YmmReg1 & ZmmReg1) ... & YmmReg2_m256_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { local tmp:32 = vxorps_avx512vl( vexVVVV_YmmReg, YmmReg2_m256_m32bcst ); @@ -10987,7 +10987,7 @@ define pcodeop vxorps_avx512vl ; # XORPS 5-599 PAGE 2423 LINE 123965 define pcodeop vxorps_avx512dq ; -:VXORPS ZmmReg1 KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x57; ZmmReg1 ... & ZmmReg2_m512_m32bcst +:VXORPS ZmmReg1^KWriteMask, evexV5_ZmmReg, ZmmReg2_m512_m32bcst is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_W0) & KWriteMask & evexV5_ZmmReg; byte=0x57; ZmmReg1 ... & ZmmReg2_m512_m32bcst [ evexD8Type = 0; evexTType = 0; ] # (TupleType FV) { ZmmReg1 = vxorps_avx512dq( evexV5_ZmmReg, ZmmReg2_m512_m32bcst ); diff --git a/Ghidra/Processors/x86/data/languages/avx512_manual.sinc b/Ghidra/Processors/x86/data/languages/avx512_manual.sinc index de4f8ea507..c14f24e143 100644 --- a/Ghidra/Processors/x86/data/languages/avx512_manual.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512_manual.sinc @@ -110,27 +110,27 @@ define pcodeop kmovd_avx512bw ; # VCVTPS2PH 5-37 PAGE 1861 LINE 96116 define pcodeop vcvtps2ph_avx512vl ; -:VCVTPS2PH XmmReg2 KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8 +:VCVTPS2PH XmmReg2^KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2; imm8 { XmmReg2 = vcvtps2ph_avx512vl( XmmReg1, imm8:1 ); ZmmReg2 = zext(XmmReg2); } -:VCVTPS2PH m64 KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; XmmReg1 ... & m64; imm8 +:VCVTPS2PH m64^KWriteMask, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; XmmReg1 ... & m64; imm8 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vcvtps2ph_avx512vl( XmmReg1, imm8:1 ); } # VCVTPS2PH 5-37 PAGE 1861 LINE 96119 -:VCVTPS2PH XmmReg2 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8 +:VCVTPS2PH XmmReg2^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2; imm8 { XmmReg2 = vcvtps2ph_avx512vl( YmmReg1, imm8:1 ); ZmmReg2 = zext(XmmReg2); } # VCVTPS2PH 5-37 PAGE 1861 LINE 96119 -:VCVTPS2PH m128 KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; YmmReg1 ... & m128; imm8 +:VCVTPS2PH m128^KWriteMask, YmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; YmmReg1 ... & m128; imm8 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vcvtps2ph_avx512vl( YmmReg1, imm8:1 ); @@ -138,13 +138,13 @@ define pcodeop vcvtps2ph_avx512vl ; # VCVTPS2PH 5-37 PAGE 1861 LINE 96122 define pcodeop vcvtps2ph_avx512f ; -:VCVTPS2PH YmmReg2 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8 +:VCVTPS2PH YmmReg2^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2; imm8 { YmmReg2 = vcvtps2ph_avx512f( ZmmReg1, imm8:1 ); ZmmReg2 = zext(YmmReg2); } -:VCVTPS2PH m256 KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; ZmmReg1 ... & m256; imm8 +:VCVTPS2PH m256^KWriteMask, ZmmReg1, imm8 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & KWriteMask; byte=0x1D; ZmmReg1 ... & m256; imm8 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vcvtps2ph_avx512f( ZmmReg1, imm8:1 ); @@ -152,13 +152,13 @@ define pcodeop vcvtps2ph_avx512f ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115319 define pcodeop vpmovdb_avx512vl ; -:VPMOVDB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovdb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVDB m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; XmmReg1 ... & m32 +:VPMOVDB m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m32 = vpmovdb_avx512vl( XmmReg1 ); @@ -166,65 +166,65 @@ define pcodeop vpmovdb_avx512vl ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115322 define pcodeop vpmovsdb_avx512vl ; -:VPMOVSDB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsdb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSDB m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; XmmReg1 ... & m32 +:VPMOVSDB m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m32 = vpmovsdb_avx512vl( XmmReg1 ); } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115326 define pcodeop vpmovusdb_avx512vl ; -:VPMOVUSDB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusdb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSDB m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & m32 +:VPMOVUSDB m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m32 = vpmovusdb_avx512vl( XmmReg1 ); } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115330 -:VPMOVDB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovdb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVDB m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; YmmReg1 ... & m64 +:VPMOVDB m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m64 = vpmovdb_avx512vl( YmmReg1 ); } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115333 -:VPMOVSDB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsdb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSDB m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; YmmReg1 ... & m64 +:VPMOVSDB m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m64 = vpmovsdb_avx512vl( YmmReg1 ); } # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115337 -:VPMOVUSDB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusdb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSDB m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; YmmReg1 ... & m64 +:VPMOVUSDB m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m64 = vpmovusdb_avx512vl( YmmReg1 ); @@ -232,13 +232,13 @@ define pcodeop vpmovusdb_avx512vl ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115341 define pcodeop vpmovdb_avx512f ; -:VPMOVDB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovdb_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVDB m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; ZmmReg1 ... & m128 +:VPMOVDB m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x31; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m128 = vpmovdb_avx512f( ZmmReg1 ); @@ -246,13 +246,13 @@ define pcodeop vpmovdb_avx512f ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115344 define pcodeop vpmovsdb_avx512f ; -:VPMOVSDB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsdb_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSDB m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; ZmmReg1 ... & m128 +:VPMOVSDB m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x21; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m128 = vpmovsdb_avx512f( ZmmReg1 ); @@ -260,13 +260,13 @@ define pcodeop vpmovsdb_avx512f ; # VPMOVDB/VPMOVSDB/VPMOVUSDB 5-418 PAGE 2242 LINE 115348 define pcodeop vpmovusdb_avx512f ; -:VPMOVUSDB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusdb_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSDB m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; ZmmReg1 ... & m128 +:VPMOVUSDB m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x11; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m128 = vpmovusdb_avx512f( ZmmReg1 ); @@ -274,13 +274,13 @@ define pcodeop vpmovusdb_avx512f ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115532 define pcodeop vpmovdw_avx512vl ; -:VPMOVDW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovdw_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVDW m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; XmmReg1 ... & m64 +:VPMOVDW m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovdw_avx512vl( XmmReg1 ); @@ -288,13 +288,13 @@ define pcodeop vpmovdw_avx512vl ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115535 define pcodeop vpmovsdw_avx512vl ; -:VPMOVSDW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsdw_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSDW m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; XmmReg1 ... & m64 +:VPMOVSDW m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovsdw_avx512vl( XmmReg1 ); @@ -302,52 +302,52 @@ define pcodeop vpmovsdw_avx512vl ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115539 define pcodeop vpmovusdw_avx512vl ; -:VPMOVUSDW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusdw_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSDW m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; XmmReg1 ... & m64 +:VPMOVUSDW m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovusdw_avx512vl( XmmReg1 ); } # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115543 -:VPMOVDW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVDW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovdw_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVDW m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; YmmReg1 ... & m128 +:VPMOVDW m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovdw_avx512vl( YmmReg1 ); } # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115546 -:VPMOVSDW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSDW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsdw_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSDW m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; YmmReg1 ... & m128 +:VPMOVSDW m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovsdw_avx512vl( YmmReg1 ); } # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115550 -:VPMOVUSDW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSDW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusdw_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSDW m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; YmmReg1 ... & m128 +:VPMOVUSDW m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovusdw_avx512vl( YmmReg1 ); @@ -355,13 +355,13 @@ define pcodeop vpmovusdw_avx512vl ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115554 define pcodeop vpmovdw_avx512f ; -:VPMOVDW YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVDW YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovdw_avx512f( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVDW m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; ZmmReg1 ... & m256 +:VPMOVDW m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x33; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovdw_avx512f( ZmmReg1 ); @@ -369,13 +369,13 @@ define pcodeop vpmovdw_avx512f ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115557 define pcodeop vpmovsdw_avx512f ; -:VPMOVSDW YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVSDW YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovsdw_avx512f( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVSDW m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; ZmmReg1 ... & m256 +:VPMOVSDW m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x23; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovsdw_avx512f( ZmmReg1 ); @@ -383,13 +383,13 @@ define pcodeop vpmovsdw_avx512f ; # VPMOVDW/VPMOVSDW/VPMOVUSDW 5-422 PAGE 2246 LINE 115561 define pcodeop vpmovusdw_avx512f ; -:VPMOVUSDW YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVUSDW YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovusdw_avx512f( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVUSDW m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; ZmmReg1 ... & m256 +:VPMOVUSDW m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x13; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovusdw_avx512f( ZmmReg1 ); @@ -397,13 +397,13 @@ define pcodeop vpmovusdw_avx512f ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114671 define pcodeop vpmovqb_avx512vl ; -:VPMOVQB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQB m16 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; XmmReg1 ... & m16 +:VPMOVQB m16^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; XmmReg1 ... & m16 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m16 = vpmovqb_avx512vl( XmmReg1 ); @@ -411,13 +411,13 @@ define pcodeop vpmovqb_avx512vl ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114674 define pcodeop vpmovsqb_avx512vl ; -:VPMOVSQB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQB m16 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; XmmReg1 ... & m16 +:VPMOVSQB m16^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; XmmReg1 ... & m16 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m16 = vpmovsqb_avx512vl( XmmReg1 ); @@ -425,52 +425,52 @@ define pcodeop vpmovsqb_avx512vl ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114678 define pcodeop vpmovusqb_avx512vl ; -:VPMOVUSQB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQB m16 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; XmmReg1 ... & m16 +:VPMOVUSQB m16^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; XmmReg1 ... & m16 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m16 = vpmovusqb_avx512vl( XmmReg1 ); } # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114682 -:VPMOVQB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQB m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; YmmReg1 ... & m32 +:VPMOVQB m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m32 = vpmovqb_avx512vl( YmmReg1 ); } # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114685 -:VPMOVSQB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQB m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; YmmReg1 ... & m32 +:VPMOVSQB m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m32 = vpmovsqb_avx512vl( YmmReg1 ); } # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114689 -:VPMOVUSQB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQB m32 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; YmmReg1 ... & m32 +:VPMOVUSQB m32^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; YmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m32 = vpmovusqb_avx512vl( YmmReg1 ); @@ -478,13 +478,13 @@ define pcodeop vpmovusqb_avx512vl ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114693 define pcodeop vpmovqb_avx512f ; -:VPMOVQB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqb_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQB m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; ZmmReg1 ... & m64 +:VPMOVQB m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x32; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m64 = vpmovqb_avx512f( ZmmReg1 ); @@ -492,13 +492,13 @@ define pcodeop vpmovqb_avx512f ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114696 define pcodeop vpmovsqb_avx512f ; -:VPMOVSQB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqb_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQB m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; ZmmReg1 ... & m64 +:VPMOVSQB m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x22; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m64 = vpmovsqb_avx512f( ZmmReg1 ); @@ -506,13 +506,13 @@ define pcodeop vpmovsqb_avx512f ; # VPMOVQB/VPMOVSQB/VPMOVUSQB 5-406 PAGE 2230 LINE 114700 define pcodeop vpmovusqb_avx512f ; -:VPMOVUSQB XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQB XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqb_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQB m64 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; ZmmReg1 ... & m64 +:VPMOVUSQB m64^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x12; ZmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 11; ] # (TupleType OVM) { m64 = vpmovusqb_avx512f( ZmmReg1 ); @@ -520,13 +520,13 @@ define pcodeop vpmovusqb_avx512f ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114887 define pcodeop vpmovqw_avx512vl ; -:VPMOVQW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqw_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQW m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; XmmReg1 ... & m32 +:VPMOVQW m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m32 = vpmovqw_avx512vl( XmmReg1 ); @@ -534,13 +534,13 @@ define pcodeop vpmovqw_avx512vl ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114890 define pcodeop vpmovsqw_avx512vl ; -:VPMOVSQW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqw_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQW m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; XmmReg1 ... & m32 +:VPMOVSQW m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m32 = vpmovsqw_avx512vl( XmmReg1 ); @@ -548,52 +548,52 @@ define pcodeop vpmovsqw_avx512vl ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114894 define pcodeop vpmovusqw_avx512vl ; -:VPMOVUSQW XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQW XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqw_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQW m32 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; XmmReg1 ... & m32 +:VPMOVUSQW m32^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; XmmReg1 ... & m32 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m32 = vpmovusqw_avx512vl( XmmReg1 ); } # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114898 -:VPMOVQW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqw_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQW m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; YmmReg1 ... & m64 +:VPMOVQW m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m64 = vpmovqw_avx512vl( YmmReg1 ); } # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114901 -:VPMOVSQW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqw_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQW m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; YmmReg1 ... & m64 +:VPMOVSQW m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m64 = vpmovsqw_avx512vl( YmmReg1 ); } # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114905 -:VPMOVUSQW XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQW XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqw_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQW m64 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; YmmReg1 ... & m64 +:VPMOVUSQW m64^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; YmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m64 = vpmovusqw_avx512vl( YmmReg1 ); @@ -601,13 +601,13 @@ define pcodeop vpmovusqw_avx512vl ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114909 define pcodeop vpmovqw_avx512f ; -:VPMOVQW XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQW XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqw_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQW m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; ZmmReg1 ... & m128 +:VPMOVQW m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x34; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m128 = vpmovqw_avx512f( ZmmReg1 ); @@ -615,13 +615,13 @@ define pcodeop vpmovqw_avx512f ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114912 define pcodeop vpmovsqw_avx512f ; -:VPMOVSQW XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQW XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqw_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQW m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; ZmmReg1 ... & m128 +:VPMOVSQW m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x24; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m128 = vpmovsqw_avx512f( ZmmReg1 ); @@ -629,13 +629,13 @@ define pcodeop vpmovsqw_avx512f ; # VPMOVQW/VPMOVSQW/VPMOVUSQW 5-410 PAGE 2234 LINE 114916 define pcodeop vpmovusqw_avx512f ; -:VPMOVUSQW XmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQW XmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; mod=3 & ZmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqw_avx512f( ZmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQW m128 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; ZmmReg1 ... & m128 +:VPMOVUSQW m128^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x14; ZmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 10; ] # (TupleType QVM) { m128 = vpmovusqw_avx512f( ZmmReg1 ); @@ -643,13 +643,13 @@ define pcodeop vpmovusqw_avx512f ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115104 define pcodeop vpmovqd_avx512vl ; -:VPMOVQD XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQD XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqd_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQD m128 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; XmmReg1 ... & m128 +:VPMOVQD m128^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; XmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovqd_avx512vl( XmmReg1 ); @@ -657,13 +657,13 @@ define pcodeop vpmovqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115108 define pcodeop vpmovsqd_avx512vl ; -:VPMOVSQD XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQD XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqd_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; XmmReg1 ... & m64 +:VPMOVSQD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovsqd_avx512vl( XmmReg1 ); @@ -671,13 +671,13 @@ define pcodeop vpmovsqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115113 define pcodeop vpmovusqd_avx512vl ; -:VPMOVUSQD XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQD XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqd_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQD m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; XmmReg1 ... & m64 +:VPMOVUSQD m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovusqd_avx512vl( XmmReg1 ); @@ -685,39 +685,39 @@ define pcodeop vpmovusqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115118 -:VPMOVQD XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVQD XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovqd_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVQD m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; YmmReg1 ... & m128 +:VPMOVQD m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovqd_avx512vl( YmmReg1 ); } # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115122 -:VPMOVSQD XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSQD XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovsqd_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSQD m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; YmmReg1 ... & m128 +:VPMOVSQD m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovsqd_avx512vl( YmmReg1 ); } # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115127 -:VPMOVUSQD XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSQD XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovusqd_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSQD m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; YmmReg1 ... & m128 +:VPMOVUSQD m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovusqd_avx512vl( YmmReg1 ); @@ -725,13 +725,13 @@ define pcodeop vpmovusqd_avx512vl ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115131 define pcodeop vpmovqd_avx512f ; -:VPMOVQD YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVQD YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovqd_avx512f( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVQD m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; ZmmReg1 ... & m256 +:VPMOVQD m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x35; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovqd_avx512f( ZmmReg1 ); @@ -739,13 +739,13 @@ define pcodeop vpmovqd_avx512f ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115134 define pcodeop vpmovsqd_avx512f ; -:VPMOVSQD YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVSQD YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovsqd_avx512f( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVSQD m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; ZmmReg1 ... & m256 +:VPMOVSQD m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x25; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovsqd_avx512f( ZmmReg1 ); @@ -753,13 +753,13 @@ define pcodeop vpmovsqd_avx512f ; # VPMOVQD/VPMOVSQD/VPMOVUSQD 5-414 PAGE 2238 LINE 115138 define pcodeop vpmovusqd_avx512f ; -:VPMOVUSQD YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVUSQD YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovusqd_avx512f( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVUSQD m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; ZmmReg1 ... & m256 +:VPMOVUSQD m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x15; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovusqd_avx512f( ZmmReg1 ); @@ -767,13 +767,13 @@ define pcodeop vpmovusqd_avx512f ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115748 define pcodeop vpmovwb_avx512vl ; -:VPMOVWB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVWB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovwb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVWB m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; XmmReg1 ... & m64 +:VPMOVWB m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovwb_avx512vl( XmmReg1 ); @@ -781,13 +781,13 @@ define pcodeop vpmovwb_avx512vl ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115751 define pcodeop vpmovswb_avx512vl ; -:VPMOVSWB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSWB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovswb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSWB m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; XmmReg1 ... & m64 +:VPMOVSWB m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovswb_avx512vl( XmmReg1 ); @@ -795,52 +795,52 @@ define pcodeop vpmovswb_avx512vl ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115754 define pcodeop vpmovuswb_avx512vl ; -:VPMOVUSWB XmmReg2 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSWB XmmReg2^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & XmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovuswb_avx512vl( XmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSWB m64 KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; XmmReg1 ... & m64 +:VPMOVUSWB m64^KWriteMask, XmmReg1 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; XmmReg1 ... & m64 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m64 = vpmovuswb_avx512vl( XmmReg1 ); } # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115757 -:VPMOVWB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVWB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovwb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVWB m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; YmmReg1 ... & m128 +:VPMOVWB m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovwb_avx512vl( YmmReg1 ); } # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115760 -:VPMOVSWB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVSWB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovswb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVSWB m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; YmmReg1 ... & m128 +:VPMOVSWB m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovswb_avx512vl( YmmReg1 ); } # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115763 -:VPMOVUSWB XmmReg2 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 +:VPMOVUSWB XmmReg2^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & YmmReg1 & XmmReg2 & ZmmReg2 { XmmReg2 = vpmovuswb_avx512vl( YmmReg1 ); ZmmReg2 = zext(XmmReg2); } -:VPMOVUSWB m128 KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; YmmReg1 ... & m128 +:VPMOVUSWB m128^KWriteMask, YmmReg1 is $(EVEX_NONE) & $(VEX_L256) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; YmmReg1 ... & m128 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m128 = vpmovuswb_avx512vl( YmmReg1 ); @@ -848,13 +848,13 @@ define pcodeop vpmovuswb_avx512vl ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115766 define pcodeop vpmovwb_avx512bw ; -:VPMOVWB YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVWB YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovwb_avx512bw( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVWB m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; ZmmReg1 ... & m256 +:VPMOVWB m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x30; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovwb_avx512bw( ZmmReg1 ); @@ -862,13 +862,13 @@ define pcodeop vpmovwb_avx512bw ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115769 define pcodeop vpmovswb_avx512bw ; -:VPMOVSWB YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVSWB YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovswb_avx512bw( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVSWB m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; ZmmReg1 ... & m256 +:VPMOVSWB m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x20; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovswb_avx512bw( ZmmReg1 ); @@ -876,13 +876,13 @@ define pcodeop vpmovswb_avx512bw ; # VPMOVWB/VPMOVSWB/VPMOVUSWB 5-426 PAGE 2250 LINE 115772 define pcodeop vpmovuswb_avx512bw ; -:VPMOVUSWB YmmReg2 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 +:VPMOVUSWB YmmReg2^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; mod=3 & ZmmReg1 & YmmReg2 & ZmmReg2 { YmmReg2 = vpmovuswb_avx512bw( ZmmReg1 ); ZmmReg2 = zext(YmmReg2); } -:VPMOVUSWB m256 KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; ZmmReg1 ... & m256 +:VPMOVUSWB m256^KWriteMask, ZmmReg1 is $(EVEX_NONE) & $(EVEX_L512) & $(VEX_PRE_F3) & $(VEX_0F38) & $(VEX_W0) & KWriteMask; byte=0x10; ZmmReg1 ... & m256 [ evexD8Type = 1; evexTType = 9; ] # (TupleType HVM) { m256 = vpmovuswb_avx512bw( ZmmReg1 ); diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 832ad98db8..dd8c841131 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -424,8 +424,7 @@ define context contextreg rexprefix=(19,19) # True if the Rex prefix is present - note, if present, vex_mode is not supported # rexWRXB bits can be re-used since they are incompatible. - evexMode=(20,21) # 2 for evex instruction, 1 for vexMode, 0 for normal - vexMode=(21,21) # 1 for vex instruction, 0 for normal + vexMode=(20,21) # 2 for evex instruction, 1 for vexMode, 0 for normal evexL = (22,23) # 0 for 128, 1 for 256, 2 for 512 (also used for rounding control) evexLp=(22,22) # EVEX.L' @@ -947,10 +946,10 @@ evexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=1 [ offs = 5; evexDisp8 evexDisp8N: offs is evexD8Type=1 & evexTType=0xd & evexL=2 [ offs = 6; evexDisp8=offs; ] { export *[const]:1 offs; } -simm8_16: disp8N is evexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:2 disp8N; } -simm8_32: disp8N is evexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:4 disp8N; } +simm8_16: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:2 disp8N; } +simm8_32: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:4 disp8N; } @ifdef IA64 -simm8_64: disp8N is evexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:8 disp8N; } +simm8_64: disp8N is vexMode=2 & evexDisp8N & simm8 [ disp8N = simm8 << evexDisp8; ] { export *[const]:8 disp8N; } @endif usimm8_16: imm8 is imm8 & imm8_7=0 { export *[const]:2 imm8; } @@ -1971,49 +1970,49 @@ macro fucompe(val1, val2) { @define VEX_W0 "rexWprefix=0" @define VEX_W1 "rexWprefix=1" -@define EVEX_NONE "evexMode=2" -@define EVEX_NDS "evexMode=2" -@define EVEX_NDD "evexMode=2" -@define EVEX_DDS "evexMode=2" +@define EVEX_NONE "vexMode=2" +@define EVEX_NDS "vexMode=2" +@define EVEX_NDD "vexMode=2" +@define EVEX_DDS "vexMode=2" @ifdef IA64 # 64-bit 3-byte VEX -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=0; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=1; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_66=1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=2; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f3=1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC4; vex_r & vex_x & vex_b & vex_mmmmm; vex_w & vex_vvvv & vex_l & vex_pp=3; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; vexMMMMM=vex_mmmmm; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexL=vex_l; prefix_f2=1; ] {} # 64-bit 2-byte VEX -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=0; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=0; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=1; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=1; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_66=1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=2; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=2; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f3=1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=3; instruction +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r & vex_vvvv & vex_l & vex_pp=3; instruction [ instrPhase=1; vexMode=1; rexRprefix=~vex_r; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {} # 4-byte EVEX prefix -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=0; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; + [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=1; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; + [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_66=1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=2; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; + [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_f3=1; ] {} -:^instruction is $(LONGMODE_ON) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; +:^instruction is $(LONGMODE_ON) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r & vex_x & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=3; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; + [ instrPhase=1; vexMode=2; rexRprefix=~vex_r; rexXprefix=~vex_x; rexBprefix=~vex_b; rexWprefix=vex_w; vexVVVV=~vex_vvvv; vexMMMMM=evex_mmm; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; prefix_f2=1; ] {} @endif @@ -2037,18 +2036,18 @@ macro fucompe(val1, val2) { :^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover=0 & byte=0xC5; vex_r=1 & vex_x=1 & vex_vvvv & vex_l & vex_pp=3; instruction [ instrPhase=1; vexMode=1; vexVVVV=~vex_vvvv; vexL=vex_l; vexMMMMM=0x1; prefix_f2=1; ] {} -:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=0; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; ] {} -:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; + [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=1; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_66=1; ] {} -:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; + [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_66=1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=2; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f3=1; ] {} -:^instruction is $(LONGMODE_OFF) & instrPhase=0 & evexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; + [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f3=1; ] {} +:^instruction is $(LONGMODE_OFF) & instrPhase=0 & vexMode=0 & rexprefix=0 & mandover & byte=0x62; vex_r=1 & vex_x=1 & vex_b & evex_rp & evex_res=0 & evex_mmm; vex_w & vex_vvvv & evex_res2=1 & vex_pp=3; evex_z & evex_lp & evex_l & evex_b & evex_vp & evex_aaa; instruction - [ instrPhase=1; evexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f2=1; ] {} + [ instrPhase=1; vexMode=2; vexVVVV=~vex_vvvv; rexBprefix=~vex_b; rexWprefix=vex_w; evexRp=~evex_rp; evexVp=~evex_vp; evexLp=evex_lp; vexL=evex_l; evexZ=evex_z; evexB=evex_b; evexAAA=evex_aaa; vexMMMMM=evex_mmm; prefix_f2=1; ] {} # Many of the multimedia instructions have a "mandatory" prefix, either 0x66, 0xf2 or 0xf3 # where the prefix really becomes part of the encoding. We collect the three possible prefixes of this