From f9ed6f4170cf0feffd012ced183ce02501fc22f1 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 29 Jun 2026 12:35:55 -0400 Subject: [PATCH 1/6] GP-7018: Fixed register opsize for mov to/from segment registers --- Ghidra/Processors/x86/data/languages/ia.sinc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 7763d811f9..7b071caba3 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -4035,8 +4035,18 @@ define pcodeop TaskRegister; @ifdef IA64 :MOV Reg64,rm64 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8b; rm64 & Reg64 ... { Reg64 = rm64; } @endif -:MOV rm16,Sreg is vexMode=0 & byte=0x8c; rm16 & Sreg ... { rm16 = Sreg; } -:MOV Sreg,rm16 is vexMode=0 & byte=0x8e; rm16 & Sreg ... { Sreg=rm16; } +:MOV m16,Sreg is vexMode=0 & byte=0x8c; (mod != 3 & Sreg) ... & m16 { m16 = Sreg; } +:MOV Rmr16,Sreg is vexMode=0 & opsize=0 & byte=0x8c; mod=3 & Rmr16 & Sreg { Rmr16 = Sreg; } +:MOV Rmr32,Sreg is vexMode=0 & opsize=1 & byte=0x8c; mod=3 & Rmr32 & check_Rmr32_dest & Sreg { Rmr32 = zext(Sreg); build check_Rmr32_dest; } +@ifdef IA64 +:MOV Rmr64,Sreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8c; mod=3 & Rmr64 & Sreg { Rmr64 = zext(Sreg); } +@endif +:MOV Sreg,m16 is vexMode=0 & byte=0x8e; (mod != 3 & Sreg) ... & m16 { Sreg = m16; } +:MOV Rmr16,Sreg is vexMode=0 & opsize=0 & byte=0x8e; mod=3 & Rmr16 & Sreg { Sreg = Rmr16; } +:MOV Rmr32,Sreg is vexMode=0 & opsize=1 & byte=0x8e; mod=3 & Rmr32 & Sreg { Sreg = Rmr32(0); } +@ifdef IA64 +:MOV Rmr64,Sreg is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0x8e; mod=3 & Rmr64 & Sreg { Sreg = Rmr64(0); } +@endif :MOV AL,moffs8 is vexMode=0 & byte=0xa0; AL & moffs8 { AL=moffs8; } :MOV AX,moffs16 is vexMode=0 & opsize=0 & byte=0xa1; AX & moffs16 { AX=moffs16; } :MOV EAX,moffs32 is vexMode=0 & opsize=1 & byte=0xa1; EAX & check_EAX_dest & moffs32 { EAX=moffs32; build check_EAX_dest; } From d0650fa0ef4a1a3fd5a02385f06be2b385c1e4de Mon Sep 17 00:00:00 2001 From: Sleigh-InSPECtor Date: Tue, 30 Apr 2024 15:05:50 +0930 Subject: [PATCH 2/6] AA64: fix stlrb and stlrh store sizes --- Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc index 2811de5d48..a3d57128ed 100644 --- a/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc +++ b/Ghidra/Processors/AARCH64/data/languages/AARCH64base.sinc @@ -5659,7 +5659,7 @@ is size.ldstr=2 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR :stlrb Rt_GPR32, addrReg is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 { - *addrReg = Rt_GPR32; + *:1 addrReg = Rt_GPR32:1; } # C6.2.312 STLRH page C6-1849 line 108967 MATCH x48808000/mask=xffe08000 @@ -5670,7 +5670,7 @@ is size.ldstr=0 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR :stlrh Rt_GPR32, addrReg is size.ldstr=1 & b_2429=0x8 & b_23=1 & L=0 & b_21=0 & b_15=1 & addrReg & Rt_GPR32 { - *addrReg = Rt_GPR32; + *:2 addrReg = Rt_GPR32:2; } # C6.2.313 STLUR page C6-1850 line 109030 MATCH x99000000/mask=xbfe00c00 From acf4fc7c781f144704f89ed849199b35badde89a Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Mon, 10 Aug 2026 14:59:01 -0400 Subject: [PATCH 3/6] GP-7133: Fixed MIPS 16e variant ldef entries --- Ghidra/Processors/MIPS/data/languages/mips.ldefs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/MIPS/data/languages/mips.ldefs b/Ghidra/Processors/MIPS/data/languages/mips.ldefs index cc6190b54e..59dc5bba94 100644 --- a/Ghidra/Processors/MIPS/data/languages/mips.ldefs +++ b/Ghidra/Processors/MIPS/data/languages/mips.ldefs @@ -132,7 +132,7 @@ Date: Mon, 10 Aug 2026 16:56:11 -0400 Subject: [PATCH 4/6] GP_6767: Corrected OF flag for x86 shift/rotate instructions --- Ghidra/Processors/x86/data/languages/ia.sinc | 244 +++++++++---------- 1 file changed, 122 insertions(+), 122 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index 7763d811f9..972db6df20 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -2188,68 +2188,33 @@ macro multflags(highhalf) { } macro rolflags(result,count) { - - local notzero = (count != 0); - local newCF = ((result & 1) != 0); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = CF ^ (result s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, (result & 1) != 0); + conditionalAssign(OF, count==1, CF ^ (result s< 0), OF); } macro rorflags(result,count) { - - local notzero = (count != 0); - local newCF = (result s< 0); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = (result s< 0) ^ ((result << 1) s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, (result s< 0)); + conditionalAssign(OF, count==1, CF ^ ((result << 1) s< 0), OF); } macro shlflags(op1,result,count) { # works for shld also - - local notzero = (count != 0); - local newCF = ( (op1 << (count - 1)) s< 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = CF ^ (result s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, (op1 << (count - 1)) s< 0); + conditionalAssign(OF, count==1, CF ^ (result s< 0), OF); } macro sarflags(op1,result,count) { - - local notzero = (count != 0); - local newCF = ( ( (op1 s>> (count - 1)) & 1 ) != 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - OF = (!one & OF); + conditionalAssign(CF, count==0, CF, ( (op1 s>> (count - 1)) & 1 ) != 0 ); + conditionalAssign(OF, count==1, 0, OF); } macro shrflags(op1,result,count) { - - local notzero = (count != 0); - local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = (op1 s< 0); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, ( (op1 >> (count - 1)) & 1 ) != 0 ); + conditionalAssign(OF, count==1, 0, (op1 s< 0)); } macro shrdflags(op1,result,count) { - - local notzero = (count != 0); - local newCF = ( ( (op1 >> (count - 1)) & 1 ) != 0 ); - CF = (!notzero & CF) | (notzero & newCF); - - local one = (count == 1); - local newOF = ((op1 s< 0) ^ (result s< 0)); - OF = (!one & OF) | (one & newOF); + conditionalAssign(CF, count==0, CF, ( (op1 >> (count - 1)) & 1 ) != 0 ); + conditionalAssign(OF, count==1, 0, ((op1 s< 0) ^ (result s< 0))); } macro fdec() { @@ -4426,82 +4391,117 @@ define pcodeop ptwrite; :PUSHFQ is $(LONGMODE_ON) & vexMode=0 & byte=0x9c { packflags(rflags); packeflags(rflags); push88(rflags); } @endif -:RCL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm8 s< 0; rm8 = (rm8 << 1) | tmpCF; OF = CF ^ (rm8 s< 0); } -:RCL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=2 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt));rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp<>(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=2 ... { local tmpCF = CF; CF = rm16 s< 0; rm16 = (rm16 << 1) | zext(tmpCF); OF = CF ^ (rm16 s< 0);} -:RCL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=2 ... {local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=2 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp<>(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=2 ... { local tmpCF=CF; CF=rm32 s< 0; rm32=(rm32<<1)|zext(tmpCF); OF=CF^(rm32 s< 0); build check_rm32_dest; } -:RCL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=2 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } -:RCL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=2 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp<>(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } +macro rcl8(dest, rotate_count) { + local cnt:1 = (rotate_count & 0x1f) % 9; + local tmp:2 = (zext(CF) << 8) | zext(dest); + tmp = (tmp << cnt)|(tmp >> (9 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp & 0x100) != 0); + conditionalAssign(OF, cnt == 1, CF ^ (dest s< 0), OF); +} + +:RCL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=2 ... { rcl8(rm8, n1:1); } +:RCL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=2 ... { rcl8(rm8, CL); } +:RCL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=2 ... ; imm8 { rcl8(rm8, imm8:1); } + +macro rcl16(dest, rotate_count) { + local cnt = (rotate_count & 0x1f) % 17; + local tmp:4 = (zext(CF) << 16) | zext(dest); + tmp = (tmp << cnt) | (tmp >> (17 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt==0, CF, (tmp & 0x10000) != 0); + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); +} + +:RCL rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=2 ... { rcl16(rm16, n1:1); } +:RCL rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=2 ... { rcl16(rm16, CL); } +:RCL rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=2 ... ; imm8 { rcl16(rm16, imm8:1); } + + +macro rcl32(dest, rotate_count) { + local cnt = rotate_count & 0x1f; + local tmp:8 = (zext(CF) << 32) | zext(dest); + tmp = (tmp << cnt) | (tmp >> (33 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt==0, CF, (tmp&0x100000000)!=0); + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); +} + +:RCL rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=2 ... { rcl32(rm32, n1:1); build check_rm32_dest; } +:RCL rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=2 ... { rcl32(rm32, CL); build check_rm32_dest; } +:RCL rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=2 ... ; imm8 { rcl32(rm32, imm8:1); build check_rm32_dest; } + @ifdef IA64 -:RCL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=2 ... { local tmpCF=CF; CF=rm64 s< 0; rm64=(rm64<<1)|zext(tmpCF); OF=CF^(rm64 s< 0);} - -:RCL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=2 ... -{ - local cnt:1=CL&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy << cnt; - rotated = rotated | (rm64_copy >> (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << cnt-1; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(64-cnt)) & rm64_copy) != 0); - rm64 = rotated; +macro rcl64(dest, rotate_count) { + local cnt:1 = rotate_count & 0x3f; + local rm64_copy:8 = dest; + local CF_copy:1 = CF; + rotated:8 = rm64_copy << cnt; + rotated = rotated | (rm64_copy >> (65 - cnt)); + local CF_bit:8 = zext(CF_copy) << cnt-1; + rotated = rotated | CF_bit; + dest = rotated; + conditionalAssign(CF, cnt == 0, CF_copy, ((1<<(64-cnt)) & rm64_copy) != 0); + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); } -:RCL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=2 ... ; imm8 -{ - local cnt:1=imm8&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy << cnt; - rotated = rotated | (rm64_copy >> (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << cnt-1; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(64-cnt)) & rm64_copy) != 0); - rm64 = rotated; -} +:RCL rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=2 ... { rcl64(rm64, n1:1); } +:RCL rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=2 ... { rcl64(rm64, CL); } +:RCL rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=2 ... ; imm8 { rcl64(rm64, imm8:1); } @endif -:RCR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm8 s< 0; CF=(rm8&1)!=0; rm8=(rm8>>1)|(tmpCF<<7); OF=OF^(rm8 s< 0); } -:RCR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=3 ... { local cnt=(CL&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%9; tmp:2=(zext(CF)<<8)|zext(rm8); tmp=(tmp>>cnt)|(tmp<<(9-cnt)); rm8=tmp(0); CF=(tmp&0x100)!=0; } -:RCR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm16 s< 0; CF=(rm16&1)!=0; rm16=(rm16>>1)|(zext(tmpCF)<<15); OF=OF^(rm16 s< 0); } -:RCR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=3 ... { local cnt=(CL&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=3 ... ; imm8 { local cnt=(imm8&0x1f)%17; tmp:4=(zext(CF)<<16)|zext(rm16); tmp=(tmp>>cnt)|(tmp<<(17-cnt)); rm16=tmp(0); CF=(tmp&0x10000)!=0; } -:RCR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=3 ... { local tmpCF=CF; OF=rm32 s< 0; CF=(rm32&1)!=0; rm32=(rm32>>1)|(zext(tmpCF)<<31); OF=OF^(rm32 s< 0); build check_rm32_dest; } -:RCR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=3 ... { local cnt=CL&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } -:RCR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=3 ... ; imm8 { local cnt=imm8&0x1f; tmp:8=(zext(CF)<<32)|zext(rm32); tmp=(tmp>>cnt)|(tmp<<(33-cnt)); rm32=tmp(0); CF=(tmp&0x100000000)!=0; build check_rm32_dest; } +macro rcr8(dest, rotate_count) { + local cnt = (rotate_count & 0x1f) % 9; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:2 = (zext(CF) << 8) | zext(dest); tmp = (tmp >> cnt) | (tmp << (9 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp & 0x100) != 0); +} + +:RCR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=3 ... { rcr8(rm8, n1:1); } +:RCR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=3 ... { rcr8(rm8, CL); } +:RCR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=3 ... ; imm8 { rcr8(rm8, imm8:1); } + +macro rcr16(dest, rotate_count) { + local cnt=(rotate_count & 0x1f) % 17; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:4 = (zext(CF) << 16) | zext(dest); + tmp = (tmp >> cnt) | (tmp << (17 - cnt)); + dest=tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp & 0x10000) != 0); +} + +:RCR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=3 ... { rcr16(rm16, n1:1); } +:RCR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=3 ... { rcr16(rm16, CL); } +:RCR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=3 ... ; imm8 { rcr16(rm16, imm8:1); } + +macro rcr32(dest, rotate_count) { + local cnt = rotate_count & 0x1f; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:8 = (zext(CF) << 32) | zext(dest); + tmp = (tmp >> cnt) | (tmp << (33 - cnt)); + dest = tmp(0); + conditionalAssign(CF, cnt == 0, CF, (tmp&0x100000000)!=0); +} + +:RCR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=3 ... { rcr32(rm32, n1:1); build check_rm32_dest; } +:RCR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=3 ... { rcr32(rm32, CL); build check_rm32_dest; } +:RCR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=3 ... ; imm8 { rcr32(rm32, imm8:1); build check_rm32_dest; } + @ifdef IA64 -:RCR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=3 ... { local tmpCF=CF; OF=rm64 s< 0; CF=(rm64&1)!=0; rm64=(rm64>>1)|(zext(tmpCF)<<63); OF=OF^(rm64 s< 0); } +macro rcr64(dest, rotate_count) { + local cnt:1 = rotate_count & 0x3f; + conditionalAssign(OF, cnt==1, CF ^ (dest s< 0), OF); + local tmp:16 = (zext(CF) << 64) | zext(dest); + tmp = (tmp >> cnt) | (tmp << (65 - cnt)); + dest = tmp(0); + local upper:1 = tmp(8) & 0x1; + conditionalAssign(CF, cnt == 0, CF, upper != 0); +} -:RCR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=3 ... -{ - local cnt:1=CL&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy >> cnt; - rotated = rotated | (rm64_copy << (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << 64-cnt; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(cnt-1)) & rm64_copy) != 0); - rm64 = rotated; - } - -:RCR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=3 ... ; imm8 -{ - local cnt:1=imm8&0x3f; - local rm64_copy:8 = rm64; - local CF_copy:1 = CF; - rotated:8 = rm64_copy >> cnt; - rotated = rotated | (rm64_copy << (65 -cnt)); - local CF_bit:8 = zext(CF_copy) << 64-cnt; - rotated = rotated | CF_bit; - conditionalAssign(CF, cnt == 0:1, CF_copy, ((1:8<<(cnt-1)) & rm64_copy) != 0); - rm64 = rotated; - } +:RCR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 & reg_opcode=3 ... { rcr64(rm64, n1:1); } +:RCR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=3 ... { rcr64(rm64, CL); } +:RCR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=3 ... ; imm8 { rcr64(rm64, imm8:1); } @endif @ifdef IA64 @@ -4710,7 +4710,7 @@ define pcodeop serialize; :SHL rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 &(reg_opcode=4|reg_opcode=6) ... { CF = rm8 s< 0; rm8 = rm8 << 1; OF = CF ^ (rm8 s< 0); resultflags(rm8); } -:SHL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 << count; +:SHL rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & (reg_opcode=4|reg_opcode=6) ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 << count; shlflags(tmp, rm8,count); shiftresultflags(rm8,count); } :SHL rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & (reg_opcode=4|reg_opcode=6) ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 << count; shlflags(tmp, rm8,count); shiftresultflags(rm8,count); } @@ -4774,23 +4774,23 @@ define pcodeop serialize; shrdflags(tmp,rm64,count); shiftresultflags(rm64,count); } @endif -:SHR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=5 ... { OF = (rm8 s< 0); CF = rm8 & 1; rm8 = rm8 >> 1; resultflags(rm8); } -:SHR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 >> count; +:SHR rm8,n1 is vexMode=0 & byte=0xD0; rm8 & n1 & reg_opcode=5 ... { CF = rm8 & 1; OF = (rm8 s< 0); rm8 = rm8 >> 1; resultflags(rm8); } +:SHR rm8,CL is vexMode=0 & byte=0xD2; CL & rm8 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm8; rm8 = rm8 >> count; shrflags(tmp, rm8,count); shiftresultflags(rm8,count); } :SHR rm8,imm8 is vexMode=0 & byte=0xC0; rm8 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm8; rm8 = rm8 >> count; shrflags(tmp, rm8,count); shiftresultflags(rm8,count); } -:SHR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=5 ... { OF = (rm16 s< 0); CF = (rm16 & 1) != 0; rm16 = rm16 >> 1; resultflags(rm16); } +:SHR rm16,n1 is vexMode=0 & opsize=0 & byte=0xD1; rm16 & n1 & reg_opcode=5 ... { CF = (rm16 & 1) != 0; OF = (rm16 s< 0); rm16 = rm16 >> 1; resultflags(rm16); } :SHR rm16,CL is vexMode=0 & opsize=0 & byte=0xD3; CL & rm16 & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm16; rm16 = rm16 >> count; shrflags(tmp, rm16,count); shiftresultflags(rm16,count); } :SHR rm16,imm8 is vexMode=0 & opsize=0 & byte=0xC1; rm16 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm16; rm16 = rm16 >> count; shrflags(tmp, rm16,count); shiftresultflags(rm16,count); } -:SHR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=5 ... { OF = (rm32 s< 0); CF = (rm32 & 1) != 0; rm32 = rm32 >> 1; build check_rm32_dest; resultflags(rm32); } +:SHR rm32,n1 is vexMode=0 & opsize=1 & byte=0xD1; rm32 & n1 & check_rm32_dest ... & reg_opcode=5 ... { CF = (rm32 & 1) != 0; OF = (rm32 s< 0); rm32 = rm32 >> 1; build check_rm32_dest; resultflags(rm32); } :SHR rm32,CL is vexMode=0 & opsize=1 & byte=0xD3; CL & rm32 & check_rm32_dest ... & reg_opcode=5 ... { local count = CL & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest; shrflags(tmp, rm32,count); shiftresultflags(rm32,count); } :SHR rm32,imm8 is vexMode=0 & opsize=1 & byte=0xC1; rm32 & check_rm32_dest ... & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x1f; local tmp = rm32; rm32 = rm32 >> count; build check_rm32_dest; shrflags(tmp, rm32,count); shiftresultflags(rm32,count); } @ifdef IA64 -:SHR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 ®_opcode=5 ... { OF = (rm64 s< 0); CF = (rm64 & 1) != 0; rm64 = rm64 >> 1; resultflags(rm64); } +:SHR rm64,n1 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD1; rm64 & n1 ®_opcode=5 ... { CF = (rm64 & 1) != 0; OF = (rm64 s< 0); rm64 = rm64 >> 1; resultflags(rm64); } :SHR rm64,CL is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xD3; CL & rm64 & reg_opcode=5 ... { local count = CL & 0x3f; local tmp = rm64; rm64 = rm64 >> count; shrflags(tmp, rm64,count); shiftresultflags(rm64,count); } :SHR rm64,imm8 is $(LONGMODE_ON) & vexMode=0 & opsize=2 & byte=0xC1; rm64 & reg_opcode=5 ... ; imm8 { local count = imm8 & 0x3f; local tmp = rm64; rm64 = rm64 >> count; From 31ffc98d3b8eabb149009fa99ffa0f0d4c621028 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Tue, 11 Aug 2026 14:53:25 -0400 Subject: [PATCH 5/6] GP-7017: Fixed masking for several PEXT* and PINS* instructions --- Ghidra/Processors/x86/data/languages/avx.sinc | 54 +++++++++++++------ .../Processors/x86/data/languages/avx512.sinc | 48 ++++++----------- Ghidra/Processors/x86/data/languages/ia.sinc | 4 +- 3 files changed, 56 insertions(+), 50 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/avx.sinc b/Ghidra/Processors/x86/data/languages/avx.sinc index 59b3dd6f07..607489e390 100644 --- a/Ghidra/Processors/x86/data/languages/avx.sinc +++ b/Ghidra/Processors/x86/data/languages/avx.sinc @@ -1832,16 +1832,16 @@ define pcodeop vpcmpistrm_avx ; define pcodeop vpextrb_avx ; :VPEXTRB Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8 { - local tmp8:1 = imm8; - local tmp = XmmReg1 >> (tmp8[0,3]*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); Rmr32 = zext(tmp[0,8]); build check_Rmr32_dest; } :VPEXTRB m8, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x14; (XmmReg1 ... & m8); imm8 { - local tmp8:1 = imm8; - local tmp = XmmReg1 >> (tmp8[0,3]*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); m8 = tmp[0,8]; } @@ -1849,39 +1849,52 @@ define pcodeop vpextrb_avx ; define pcodeop vpextrd_avx ; :VPEXTRD Rmr32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; mod=3 & XmmReg1 & Rmr32 & check_Rmr32_dest; imm8 { - local tmp = XmmReg1 >> (imm8*32); + local tmp8:1 = imm8 & 3; + local tmp = XmmReg1 >> (tmp8*32); Rmr32 = tmp(0); build check_Rmr32_dest; } :VPEXTRD m32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & m32; imm8 { - local tmp = XmmReg1 >> (imm8*32); + local tmp8:1 = imm8 & 3; + local tmp = XmmReg1 >> (tmp8*32); m32 = tmp(0); } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72330 -define pcodeop vpextrq_avx ; @ifdef IA64 :VPEXTRQ rm64, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8 { - rm64 = vpextrq_avx( XmmReg1, imm8:1 ); + local tmp8:1 = imm8 & 1; + local tmp = XmmReg1 >> (tmp8*64); + rm64 = tmp(0); } @endif # PEXTRW 4-277 PAGE 1397 LINE 72478 -define pcodeop vpextrw_avx ; -:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 +:VPEXTRW Reg32, XmmReg2, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2); imm8 { - Reg32 = vpextrw_avx( XmmReg2, imm8:1 ); - # TODO Reg64 = zext(Reg32) + local tmp8:1 = imm8 & 7; + local tmp = XmmReg2 >> (tmp8*16); + Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; } # PEXTRW 4-277 PAGE 1397 LINE 72483 -:VPEXTRW Reg32_m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & Reg32_m16; imm8 +:VPEXTRW Reg32, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32 & check_Reg32_dest; imm8 { - Reg32_m16 = vpextrw_avx( XmmReg1, imm8:1 ); - # TODO Reg64 = zext(Reg32) + local tmp8:1 = imm8 & 7; + local tmp = XmmReg1 >> (tmp8*16); + Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; +} + +:VPEXTRW m16, XmmReg1, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & m16; imm8 +{ + local tmp8:1 = imm8 & 7; + local tmp = XmmReg1 >> (tmp8*16); + m16 = tmp[0,16]; } # PHADDW/PHADDD 4-280 PAGE 1400 LINE 72627 @@ -1950,7 +1963,16 @@ define pcodeop vpinsrb_avx ; # PINSRW 4-296 PAGE 1416 LINE 73446 define pcodeop vpinsrw_avx ; -:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 +@ifdef IA64 +:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(LONGMODE_ON) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 +{ + local tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 ); + ZmmReg1 = zext(tmp); +} +@endif + +# Footnote in manual: In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW). +:VPINSRW XmmReg1, vexVVVV_XmmReg, Reg32_m16, imm8 is $(LONGMODE_OFF) & $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_W0) & vexVVVV_XmmReg; byte=0xC4; (XmmReg1 & ZmmReg1) ... & Reg32_m16; imm8 { local tmp:16 = vpinsrw_avx( vexVVVV_XmmReg, Reg32_m16, imm8:1 ); ZmmReg1 = zext(tmp); diff --git a/Ghidra/Processors/x86/data/languages/avx512.sinc b/Ghidra/Processors/x86/data/languages/avx512.sinc index 97ea239c2b..5fbec89db3 100644 --- a/Ghidra/Processors/x86/data/languages/avx512.sinc +++ b/Ghidra/Processors/x86/data/languages/avx512.sinc @@ -3146,30 +3146,27 @@ define pcodeop vpcmpgtq_avx512f ; } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72334 -@ifdef IA64 -:VPEXTRB Reg32, XmmReg1, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32 & Reg64; imm8 +:VPEXTRB Reg32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32 & check_Reg32_dest; imm8 { - local tmp = XmmReg1 >> (imm8*8); - Reg64 = zext(tmp[0,8]); -} -@endif - -:VPEXTRB Reg32, XmmReg1, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 & mod=3 & Reg32; imm8 -{ - local tmp = XmmReg1 >> (imm8*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); Reg32 = zext(tmp[0,8]); + build check_Reg32_dest; } + :VPEXTRB m8, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x14; XmmReg1 ... & m8; imm8 { - local tmp = XmmReg1 >> (imm8*8); + local tmp8:1 = imm8 & 0xf; + local tmp = XmmReg1 >> (tmp8*8); m8 = tmp[0,8]; } # PEXTRB/PEXTRD/PEXTRQ 4-274 PAGE 1394 LINE 72339 :VPEXTRD rm32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0); byte=0x16; XmmReg1 ... & rm32; imm8 { - local tmp = XmmReg1 >> (imm8*32); + local tmp8:1 = imm8 & 0x3; + local tmp = XmmReg1 >> (tmp8*32); rm32 = tmp[0,32]; } @@ -3177,42 +3174,29 @@ define pcodeop vpcmpgtq_avx512f ; @ifdef IA64 :VPEXTRQ rm64, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W1); byte=0x16; XmmReg1 ... & rm64; imm8 { - local tmp = XmmReg1 >> (imm8*64); + local tmp8:1 = imm8 & 0x1; + local tmp = XmmReg1 >> (tmp8*64); rm64 = tmp[0,64]; } @endif # PEXTRW 4-277 PAGE 1397 LINE 72488 -@ifdef IA64 -:VPEXTRW Reg32, XmmReg2, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & Reg64 & (mod=0x3 & XmmReg2); imm8 -{ - local tmp = XmmReg2 >> (imm8*16); - Reg64 = zext(tmp[0,16]); -} -@endif - -:VPEXTRW Reg32, XmmReg2, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & (mod=0x3 & XmmReg2); imm8 +:VPEXTRW Reg32, XmmReg2, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xC5; Reg32 & check_Reg32_dest & (mod=0x3 & XmmReg2); imm8 { local tmp = XmmReg2 >> (imm8*16); Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; } + # PEXTRW 4-277 PAGE 1397 LINE 72494 -@ifdef IA64 -:VPEXTRW Reg32, XmmReg1, imm8 is $(LONGMODE_ON) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32 & Reg64; imm8 -{ - local tmp = XmmReg1 >> (imm8*16); - Reg64 = zext(tmp[0,16]); -} -@endif - -:VPEXTRW Reg32, XmmReg1, imm8 is $(LONGMODE_OFF) & $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32; imm8 +:VPEXTRW Reg32, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 & mod=3 & Reg32 & check_Reg32_dest; imm8 { local tmp = XmmReg1 >> (imm8*16); Reg32 = zext(tmp[0,16]); + build check_Reg32_dest; } - :VPEXTRW m16, XmmReg1, imm8 is $(EVEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_WIG); byte=0x15; XmmReg1 ... & m16; imm8 { local tmp = XmmReg1 >> (imm8*16); diff --git a/Ghidra/Processors/x86/data/languages/ia.sinc b/Ghidra/Processors/x86/data/languages/ia.sinc index bec84c5ba3..9c3482063c 100644 --- a/Ghidra/Processors/x86/data/languages/ia.sinc +++ b/Ghidra/Processors/x86/data/languages/ia.sinc @@ -8691,7 +8691,7 @@ define pcodeop phsubsw; :PINSRW mmxreg, Rmr32, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; mmxmod=3 & Rmr32 & mmxreg; imm8 { - local destIndex:1 = (imm8 & 0x7) * 16:1; + local destIndex:1 = (imm8 & 0x3) * 16:1; mmxreg = mmxreg & ~(0xffff:8 << destIndex); local newVal:8 = zext(Rmr32[0,16]); mmxreg = mmxreg | (newVal << destIndex); @@ -8699,7 +8699,7 @@ define pcodeop phsubsw; :PINSRW mmxreg, m16, imm8 is vexMode=0 & mandover=0 & byte=0x0F; byte=0xC4; m16 & mmxreg ... ; imm8 { - local destIndex:1 = (imm8 & 0x7) * 16:1; + local destIndex:1 = (imm8 & 0x3) * 16:1; mmxreg = mmxreg & ~(0xffff:8 << destIndex); local newVal:8 = zext(m16); mmxreg = mmxreg | (newVal << destIndex); From 90015f129cbe0ff67bc5e9481c8cdf3f256fef10 Mon Sep 17 00:00:00 2001 From: ghidorahrex Date: Wed, 12 Aug 2026 08:36:10 -0400 Subject: [PATCH 6/6] GP-7017: Upped x86 version number --- Ghidra/Processors/x86/data/languages/x86.ldefs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Ghidra/Processors/x86/data/languages/x86.ldefs b/Ghidra/Processors/x86/data/languages/x86.ldefs index 43b1ecf864..089bee449a 100644 --- a/Ghidra/Processors/x86/data/languages/x86.ldefs +++ b/Ghidra/Processors/x86/data/languages/x86.ldefs @@ -5,7 +5,7 @@ endian="little" size="32" variant="default" - version="4.7" + version="4.8" slafile="x86.sla" processorspec="x86.pspec" manualindexfile="../manuals/x86.idx" @@ -37,7 +37,7 @@ endian="little" size="32" variant="System Management Mode" - version="4.7" + version="4.8" slafile="x86.sla" processorspec="x86-16.pspec" manualindexfile="../manuals/x86.idx" @@ -50,7 +50,7 @@ endian="little" size="16" variant="Real Mode" - version="4.7" + version="4.8" slafile="x86.sla" processorspec="x86-16-real.pspec" manualindexfile="../manuals/x86.idx" @@ -70,7 +70,7 @@ endian="little" size="16" variant="Protected Mode" - version="4.7" + version="4.8" slafile="x86.sla" processorspec="x86-16.pspec" manualindexfile="../manuals/x86.idx" @@ -85,7 +85,7 @@ endian="little" size="64" variant="default" - version="4.7" + version="4.8" slafile="x86-64.sla" processorspec="x86-64.pspec" manualindexfile="../manuals/x86.idx" @@ -108,7 +108,7 @@ endian="little" size="64" variant="compat32" - version="4.7" + version="4.8" slafile="x86-64.sla" processorspec="x86-64-compat32.pspec" manualindexfile="../manuals/x86.idx"