Mirrors_Framework/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-05-30 10:55:48 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/GP-3217_emteere_JALCallGotoFix'

Browse Source 
into patch (Closes #5092)
This commit is contained in:
Ryan Kurtz
2023-03-22 11:16:42 -04:00
parent 9b06b08de7 5bf82b8af1
commit 8890844251
2 changed files with 21 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Ghidra/Processors/RISCV/data/languages/riscv.ldefs
+11 -11
View File
@@ -6,7 +6,7 @@
endian="little" endian="little"
size="64" size="64"
variant="RV64I" variant="RV64I"
version="1.2" version="1.3"
slafile="riscv.lp64d.sla" slafile="riscv.lp64d.sla"
processorspec="RV64I.pspec" processorspec="RV64I.pspec"
id="RISCV:LE:64:RV64I"> id="RISCV:LE:64:RV64I">
@@ -19,7 +19,7 @@
endian="little" endian="little"
size="64" size="64"
variant="RV64IC" variant="RV64IC"
version="1.2" version="1.3"
slafile="riscv.lp64d.sla" slafile="riscv.lp64d.sla"
processorspec="RV64IC.pspec" processorspec="RV64IC.pspec"
id="RISCV:LE:64:RV64IC"> id="RISCV:LE:64:RV64IC">
@@ -32,7 +32,7 @@
endian="little" endian="little"
size="64" size="64"
variant="RV64G" variant="RV64G"
version="1.2" version="1.3"
slafile="riscv.lp64d.sla" slafile="riscv.lp64d.sla"
processorspec="RV64G.pspec" processorspec="RV64G.pspec"
id="RISCV:LE:64:RV64G"> id="RISCV:LE:64:RV64G">
@@ -45,7 +45,7 @@
endian="little" endian="little"
size="64" size="64"
variant="RV64GC" variant="RV64GC"
version="1.2" version="1.3"
slafile="riscv.lp64d.sla" slafile="riscv.lp64d.sla"
processorspec="RV64GC.pspec" processorspec="RV64GC.pspec"
id="RISCV:LE:64:RV64GC"> id="RISCV:LE:64:RV64GC">
@@ -58,7 +58,7 @@
endian="little" endian="little"
size="64" size="64"
variant="default" variant="default"
version="1.2" version="1.3"
slafile="riscv.lp64d.sla" slafile="riscv.lp64d.sla"
processorspec="RV64GC.pspec" processorspec="RV64GC.pspec"
id="RISCV:LE:64:default"> id="RISCV:LE:64:default">
@@ -71,7 +71,7 @@
endian="little" endian="little"
size="32" size="32"
variant="RV32I" variant="RV32I"
version="1.2" version="1.3"
slafile="riscv.ilp32d.sla" slafile="riscv.ilp32d.sla"
processorspec="RV32I.pspec" processorspec="RV32I.pspec"
id="RISCV:LE:32:RV32I"> id="RISCV:LE:32:RV32I">
@@ -84,7 +84,7 @@
endian="little" endian="little"
size="32" size="32"
variant="RV32IC" variant="RV32IC"
version="1.2" version="1.3"
slafile="riscv.ilp32d.sla" slafile="riscv.ilp32d.sla"
processorspec="RV32IC.pspec" processorspec="RV32IC.pspec"
id="RISCV:LE:32:RV32IC"> id="RISCV:LE:32:RV32IC">
@@ -97,7 +97,7 @@
endian="little" endian="little"
size="32" size="32"
variant="RV32IMC" variant="RV32IMC"
version="1.2" version="1.3"
slafile="riscv.ilp32d.sla" slafile="riscv.ilp32d.sla"
processorspec="RV32IMC.pspec" processorspec="RV32IMC.pspec"
id="RISCV:LE:32:RV32IMC"> id="RISCV:LE:32:RV32IMC">
@@ -110,7 +110,7 @@
endian="little" endian="little"
size="32" size="32"
variant="RV32G" variant="RV32G"
version="1.2" version="1.3"
slafile="riscv.ilp32d.sla" slafile="riscv.ilp32d.sla"
processorspec="RV32G.pspec" processorspec="RV32G.pspec"
id="RISCV:LE:32:RV32G"> id="RISCV:LE:32:RV32G">
@@ -123,7 +123,7 @@
endian="little" endian="little"
size="32" size="32"
variant="RV32GC" variant="RV32GC"
version="1.2" version="1.3"
slafile="riscv.ilp32d.sla" slafile="riscv.ilp32d.sla"
processorspec="RV32GC.pspec" processorspec="RV32GC.pspec"
id="RISCV:LE:32:RV32GC"> id="RISCV:LE:32:RV32GC">
@@ -136,7 +136,7 @@
endian="little" endian="little"
size="32" size="32"
variant="default" variant="default"
version="1.2" version="1.3"
slafile="riscv.ilp32d.sla" slafile="riscv.ilp32d.sla"
processorspec="RV32GC.pspec" processorspec="RV32GC.pspec"
id="RISCV:LE:32:default"> id="RISCV:LE:32:default">
Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
+10 -10
View File
@@ -123,15 +123,15 @@
} }
# jal d,a 0000006f 0000007f JSR (0, 0) # jal d,a 0000006f 0000007f JSR (0, 0)
# call if RA set, destreg == RA # call for rd = RA|T0 set to inst_next
:jal ra,immUJ is immUJ & ra & r0711=1 & op0001=0x3 & op0204=0x3 & op0506=0x3 :jal rd,immUJ is immUJ & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x3 & op0506=0x3
{ {
ra = inst_next; rd = inst_next;
call immUJ; call immUJ;
} }
# goto if RA not set, destreg != RA # goto for all other rd set to inst_next
:jal rd,immUJ is immUJ & rd & op0001=0x3 & op0204=0x3 & op0506=0x3 :jal rd,immUJ is immUJ & rd & r0711 & op0001=0x3 & op0204=0x3 & op0506=0x3
{ {
rd = inst_next; rd = inst_next;
goto immUJ; goto immUJ;
@@ -144,16 +144,16 @@
} }
# jalr d,s,j 00000067 0000707f JSR (0, 0) # jalr d,s,j 00000067 0000707f JSR (0, 0)
# call if RA set, destreg == RA # call for rd = RA|T0 set to inst_next
:jalr ra,rs1,immI is rs1 & immI & ra & r0711=1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 :jalr rd,rs1,immI is rs1 & immI & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
{ {
local ea:$(XLEN) = (rs1 + immI) & ~1; local ea:$(XLEN) = (rs1 + immI) & ~1;
ra = inst_next; rd = inst_next;
call [ea]; call [ea];
} }
# goto if RA not set, destreg != RA # goto for all other rd set to inst_next
:jalr rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0 :jalr rd,rs1,immI is rs1 & immI & rd & r0711 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
{ {
local ea:$(XLEN) = (rs1 + immI) & ~1; local ea:$(XLEN) = (rs1 + immI) & ~1;
rd = inst_next; rd = inst_next;