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Merge remote-tracking branch 'origin/patch'

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ghidra1
2023-06-12 20:31:15 -04:00
parent 25b68748ae 5970699db1
commit 855a607699
23 changed files with 566 additions and 171 deletions
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Ghidra/Processors/68000/data/languages/68000.cspec
+11 -13
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@@ -22,25 +22,16 @@
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="__stdcall" extrapop="4" stackshift="4" strategy="register">
<prototype name="__stdcall" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D1"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
@@ -64,6 +55,13 @@
<register name="A6"/>
<register name="SP"/>
</unaffected>
<killedbycall>
<register name="D0"/>
<register name="D1"/>
<register name="A0"/>
<register name="A1"/>
</killedbycall>
</prototype>
</default_proto>
</compiler_spec>
Ghidra/Processors/68000/data/languages/68000.ldefs
+1
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@@ -61,6 +61,7 @@
id="68000:BE:32:Coldfire">
<description>Motorola 32-bit Coldfire</description>
<compiler name="default" spec="68000.cspec" id="default"/>
<compiler name="register" spec="68000_register.cspec" id="register"/>
<external_name tool="IDA-PRO" name="colfire"/>
<external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
</language>
Ghidra/Processors/68000/data/languages/68000.sinc
+3 -3
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@@ -1643,7 +1643,7 @@ m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { }
:movem.w (regan)+,m2rfw0 is opbig=0x4c & op67=2 & mode=3 & regan; m2rfw0 { movemptr = regan; build m2rfw0; regan = movemptr; }
:movem.w (d16,regan),m2rfw0 is opbig=0x4c & op67=2 & mode=5 & regan; m2rfw0; d16 { movemptr = regan+d16; build m2rfw0; }
:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=6 & regan; m2rfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfw0; }
:movem.w (d16,PC),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=2; m2rfw0; d16 & PC { movemptr = inst_start+2+d16; build m2rfw0; }
:movem.w (d16,PC),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=2; m2rfw0; d16 & PC { movemptr = inst_start+4+d16; build m2rfw0; }
:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=3; m2rfw0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfw0; }
:movem.w (d16)".w",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=0; m2rfw0; d16 { movemptr = d16; build m2rfw0; }
:movem.w (d32)".l",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=1; m2rfw0; d32 { movemptr = d32; build m2rfw0; }
@@ -1651,7 +1651,7 @@ m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { }
:movem.l (regan)+,m2rfl0 is opbig=0x4c & op67=3 & mode=3 & regan; m2rfl0 { movemptr = regan; build m2rfl0; regan = movemptr; }
:movem.l (d16,regan),m2rfl0 is opbig=0x4c & op67=3 & mode=5 & regan; m2rfl0; d16 { movemptr = regan+d16; build m2rfl0; }
:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=6 & regan; m2rfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfl0; }
:movem.l (d16,PC),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=2; m2rfl0; d16 & PC { movemptr = inst_start+2+d16; build m2rfl0; }
:movem.l (d16,PC),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=2; m2rfl0; d16 & PC { movemptr = inst_start+4+d16; build m2rfl0; }
:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=3; m2rfl0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfl0; }
:movem.l (d16)".w",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=0; m2rfl0; d16 { movemptr = d16; build m2rfl0; }
:movem.l (d32)".l",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=1; m2rfl0; d32 { movemptr = d32; build m2rfl0; }
@@ -1764,7 +1764,7 @@ macro negResFlags(result) {
Txb = result:1;
}
:pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { SP = SP-4; *SP = eaptr; }
:pea eaptr is (opbig=0x48 & op67=1 & $(CTL_ADDR_MODES))... & eaptr { value:4 = eaptr; SP = SP-4; *SP = value; }
@ifdef MC68040
Ghidra/Processors/68000/data/languages/68000_register.cspec
+118
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@@ -0,0 +1,118 @@
<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="10" /> <!-- aligned-length=12 -->
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="4" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
</global>
<stackpointer register="SP" space="ram"/>
<default_proto>
<prototype name="register" extrapop="4" stackshift="4" strategy="register">
<input>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A1"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="FP0"/>
</pentry>
<pentry minsize="1" maxsize="4" metatype="float">
<register name="FP1"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D1"/>
</pentry>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
</output>
<unaffected>
<register name="D2"/>
<register name="D3"/>
<register name="D4"/>
<register name="D5"/>
<register name="D6"/>
<register name="D7"/>
<register name="A2"/>
<register name="A3"/>
<register name="A4"/>
<register name="A5"/>
<register name="A6"/>
<register name="SP"/>
</unaffected>
</prototype>
</default_proto>
<prototype name="standard" extrapop="4" stackshift="4">
<input>
<pentry minsize="1" maxsize="500" align="4">
<addr offset="4" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="4" metatype="ptr">
<register name="A0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="D0"/>
</pentry>
</output>
<unaffected>
<register name="D2"/>
<register name="D3"/>
<register name="D4"/>
<register name="D5"/>
<register name="D6"/>
<register name="D7"/>
<register name="A2"/>
<register name="A3"/>
<register name="A4"/>
<register name="A5"/>
<register name="A6"/>
<register name="SP"/>
</unaffected>
<killedbycall>
<register name="D0"/>
<register name="D1"/>
<register name="A0"/>
<register name="A1"/>
</killedbycall>
</prototype>
</compiler_spec>
Ghidra/Processors/68000/data/patterns/68000_patterns.xml
+41
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@@ -0,0 +1,41 @@
<patternlist>
<patternpairs totalbits="32" postbits="16">
<!-- Higher confidence patterns, after a return and more defined bits -->
<prepatterns>
<data>0x4e 0x75</data> <!-- ret -->
<data>0x4e 0x75 0x4e 0x71 </data> <!-- ret; padding -->
<data>0x4e 0x75 0x00 0x00 </data> <!-- ret; padding -->
<data>0x4e 0x5e 0x4e 0x75</data> <!-- unlk A6; ret -->
<data>0x4e 0x5e 0x4e 0x75 0x4e 0x71 </data> <!-- unlk A6; ret; padding -->
<data>0x4e 0x5e 0x4e 0x75 0x00 0x00 </data> <!-- unlk A6; ret; padding -->
</prepatterns>
<postpatterns>
<data>01001111 11101111 1111.... .......0 </data> <!-- lea (-imm,SP),SP) -->
<data>0x4e 0x56 0x00 0x00 </data> <!-- link.w A6, 0 -->
<data>0x4e 0x56 1111.... .......0 </data> <!-- link.w A6, -imm -->
<data>0101...1 10001111 01001000 11010111 ........ ........ </data> <!-- subq.l +imm, SP; movem.l {}, (SP) -->
<data>0010...0 0.101111 0000.... .......0 </data> <!-- mov.l (+imm, SP), reg -->
<data>0x2f 0x02 </data> <!-- move.l D2,-SP -->
<data>0x2f 0x03 </data> <!-- move.l D3,-SP -->
<data>0x2f 0x0a </data> <!-- move.l A2,-SP -->
<data>0x2f 0x0b </data> <!-- move.l A3,-SP -->
<funcstart/>
</postpatterns>
</patternpairs>
<patternpairs totalbits="32" postbits="16">
<!-- pattern after a bra.w, use more solid patterns for function starts -->
<prepatterns>
<data>0x60 0x00 ........ ........ </data> <!-- bra.w -->
</prepatterns>
<postpatterns>
<data>01001111 11101111 1111.... .......0 </data> <!-- lea (-imm,SP),SP) -->
<data>0x4e 0x56 0x00 0x00 </data> <!-- link.w A6, 0 -->
<data>0x4e 0x56 1111.... .......0 </data> <!-- link.w A6, -imm -->
<funcstart/>
</postpatterns>
</patternpairs>
</patternlist>
Ghidra/Processors/68000/data/patterns/patternconstraints.xml
+5
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@@ -0,0 +1,5 @@
<patternconstraints>
<language id="68000:BE:*:*">
<patternfile>68000_patterns.xml</patternfile>
</language>
</patternconstraints>