diff --git a/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest b/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest
index d7efbaa85e..8b48f96fca 100644
--- a/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest
+++ b/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest
@@ -1,7 +1,12 @@
MODULE FILE LICENSE: pypkg/dist/capstone-5.0.6-py3-none-win_amd64.whl BSD-3-CAPSTONE
MODULE FILE LICENSE: pypkg/dist/comtypes-1.4.13-py3-none-any.whl MIT
MODULE FILE LICENSE: pypkg/dist/pybag-2.2.16-py3-none-any.whl MIT
+MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp39-cp39-win_amd64.whl Python Software Foundation License
+MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp310-cp310-win_amd64.whl Python Software Foundation License
+MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp311-cp311-win_amd64.whl Python Software Foundation License
+MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp312-cp312-win_amd64.whl Python Software Foundation License
MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp313-cp313-win_amd64.whl Python Software Foundation License
+MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp314-cp314-win_amd64.whl Python Software Foundation License
MODULE FILE LICENSE: pypkg/dist/win32more-0.7.0-py3-none-any.whl MIT
MODULE FILE LICENSE: pypkg/dist/win32more_appsdk-0.7.3-py2.py3-none-any.whl MIT
MODULE FILE LICENSE: pypkg/dist/win32more_core-0.7.0-py2.py3-none-any.whl MIT
diff --git a/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle b/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle
index 0bb21286bc..e805db4e6e 100644
--- a/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle
+++ b/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle
@@ -84,7 +84,12 @@ task prebuildTlb(type: Copy) {
distributePyDep("pybag-2.2.16-py3-none-any.whl")
distributePyDep("capstone-5.0.6-py3-none-win_amd64.whl")
distributePyDep("comtypes-1.4.13-py3-none-any.whl")
+distributePyDep("pywin32-311-cp39-cp39-win_amd64.whl")
+distributePyDep("pywin32-311-cp310-cp310-win_amd64.whl")
+distributePyDep("pywin32-311-cp311-cp311-win_amd64.whl")
+distributePyDep("pywin32-311-cp312-cp312-win_amd64.whl")
distributePyDep("pywin32-311-cp313-cp313-win_amd64.whl")
+distributePyDep("pywin32-311-cp314-cp314-win_amd64.whl")
distributePyDep("win32more-0.7.0-py3-none-any.whl")
distributePyDep("win32more_appsdk-0.7.3-py2.py3-none-any.whl")
distributePyDep("win32more_core-0.7.0-py2.py3-none-any.whl")
diff --git a/Ghidra/Processors/Hexagon/Module.manifest b/Ghidra/Processors/Hexagon/Module.manifest
new file mode 100755
index 0000000000..e69de29bb2
diff --git a/Ghidra/Processors/Hexagon/build.gradle b/Ghidra/Processors/Hexagon/build.gradle
new file mode 100755
index 0000000000..8696fe91ea
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/build.gradle
@@ -0,0 +1,35 @@
+/* ###
+ * IP: GHIDRA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
+apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
+apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
+apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
+apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
+apply plugin: 'eclipse'
+eclipse.project.name = 'Processors Hexagon'
+
+dependencies {
+ api project(":BytePatterns")
+ api project(":Emulation")
+
+ testImplementation project(path: ':SoftwareModeling', configuration: 'testArtifacts')
+ testImplementation project(path: ':Emulation', configuration: 'testArtifacts')
+}
+
+sleighCompileOptions = [
+ "-l",
+ "-t"
+]
diff --git a/Ghidra/Processors/Hexagon/certification.manifest b/Ghidra/Processors/Hexagon/certification.manifest
new file mode 100755
index 0000000000..db3305d019
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/certification.manifest
@@ -0,0 +1,16 @@
+##VERSION: 2.0
+Module.manifest||GHIDRA||||END|
+data/languages/Hexagon.opinion||GHIDRA||||END|
+data/languages/hexagon.cspec||GHIDRA||||END|
+data/languages/hexagon.dwarf||GHIDRA||||END|
+data/languages/hexagon.ldefs||GHIDRA||||END|
+data/languages/hexagon.pspec||GHIDRA||||END|
+data/languages/hexagon.sinc||GHIDRA||||END|
+data/languages/hexagon.slaspec||GHIDRA||||END|
+data/languages/hexagon_float.sinc||GHIDRA||||END|
+data/languages/hexagon_hvx.sinc||GHIDRA||||END|
+data/languages/hexagon_hvx.txt||GHIDRA|exclude|||END|
+data/languages/hexagon_left.sinc||GHIDRA||||END|
+data/languages/hexagon_right.sinc||GHIDRA||||END|
+data/patterns/Hexagon_patterns.xml||GHIDRA||||END|
+data/patterns/patternconstraints.xml||GHIDRA||||END|
diff --git a/Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion b/Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion
new file mode 100755
index 0000000000..ba3f687b46
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion
@@ -0,0 +1,5 @@
+
+
+
+
+
diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec b/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec
new file mode 100755
index 0000000000..91e10ecfef
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec
@@ -0,0 +1,154 @@
+
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\ No newline at end of file
diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf b/Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf
new file mode 100644
index 0000000000..7420ce370c
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf
@@ -0,0 +1,19 @@
+
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diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs b/Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs
new file mode 100755
index 0000000000..0c21cea52a
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs
@@ -0,0 +1,17 @@
+
+
+
+
+ Qualcomm Hexagon V69 processor (QDSP6) 32-bit little-endian
+
+
+
+
+
diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.pspec b/Ghidra/Processors/Hexagon/data/languages/hexagon.pspec
new file mode 100755
index 0000000000..a2ad8e872e
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.pspec
@@ -0,0 +1,439 @@
+
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\ No newline at end of file
diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
new file mode 100755
index 0000000000..de29be04da
--- /dev/null
+++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc
@@ -0,0 +1,17384 @@
+# Qualcomm Hexagon (V73) General Instruction Set
+
+#
+# Custom pcode-op
+#
+define pcodeop lock;
+define pcodeop unlock;
+define pcodeop lock_valid;
+define pcodeop bitReverse;
+define pcodeop circularAdd;
+define pcodeop countTrailingZeros;
+define pcodeop countTrailingOnes;
+define pcodeop countLeadingBits;
+define pcodeop saturate8;
+define pcodeop saturate16;
+define pcodeop saturate32;
+define pcodeop usaturate8;
+define pcodeop usaturate16;
+define pcodeop usaturate32;
+
+# roundArithmetic(v,n) (n==0) ? (v) : round( v + 2**(n-1) )) >> n
+# Arithmentic rounding of v to any bit location n (only least significant 5-bits of n are used)
+# round: .5 is rounded up
+define pcodeop roundArithmetic;
+define pcodeop roundArithmeticSaturate;
+
+# roundConvergent(v,n) (n==0) ? v : convround(v + 2**(n-1)) >> n
+# Convergent rounding of v to any bit location n (only least significant 5-bits of n are used)
+# convround: .5 is rounded towards even
+define pcodeop roundConvergent;
+define pcodeop roundConvergentSaturate;
+
+define pcodeop reciprocal;
+define pcodeop reciprocalAdjust;
+define pcodeop multiplyAddScale;
+
+#
+# Macros
+#
+
+macro addSat16(dest, src1, src2) {
+ result:4 = sext(src1) + sext(src2);
+ dest = saturate16(result);
+}
+
+macro adduSat16(dest, src1, src2) {
+ result:4 = zext(src1) + zext(src2);
+ dest = usaturate16(result);
+}
+
+macro subSat16(dest, src1, src2) {
+ result:4 = sext(src1) - sext(src2);
+ dest = saturate16(result);
+}
+
+macro subuSat16(dest, src1, src2) {
+ result:4 = zext(src1) - zext(src2);
+ dest = usaturate16(result);
+}
+
+macro addSat32(dest, src1, src2) {
+ result:8 = sext(src1) + sext(src2);
+ dest = saturate32(result);
+}
+
+macro adduSat32(dest, src1, src2) {
+ result:8 = zext(src1) + zext(src2);
+ dest = usaturate32(result);
+}
+
+macro subSat32(dest, src1, src2) {
+ result:8 = sext(src1) - sext(src2);
+ dest = saturate32(result);
+}
+
+macro subuSat32(dest, src1, src2) {
+ result:8 = zext(src1) - zext(src2);
+ dest = usaturate32(result);
+}
+
+#
+# Sub-constructors
+#
+
+Zero: "#"^val is epsilon [ val = 0; ] { export *[const]:1 val; }
+MinusOne: "#"^val is epsilon [ val = -1; ] { export *[const]:1 val; }
+One: "#"^val is epsilon [ val = 1; ] { export *[const]:1 val; }
+FF: "#"^val is epsilon [ val = 0xff; ] { export *[const]:1 val; }
+
+PCval: val is epsilon [ val = inst_start - (4 * packetOffset); ] { export *[const]:4 val; }
+PacketPC: PC is PC & PCval { export PCval; }
+
+# Source control register (handle PC special)
+Cs5: cs5 is cs5 { export cs5; } # Source use only
+Cs5: PacketPC is cs5=9 & PacketPC { export PacketPC; }
+
+# Destination control register (PC assignment not currently handled)
+Cd5: cd5 is cd5 & cd5_ {
+ export cd5_;
+ <>
+ cd5 = cd5_;
+}
+Cdd5: cdd5 is cdd5 & cdd5_ {
+ export cdd5_;
+ <>
+ cdd5 = cdd5_;
+}
+
+# Destination guest register (shadow not currently supported)
+Gd5: gd5 is gd5 { export gd5; }
+Gdd5: gdd5 is gdd5 { export gdd5; }
+
+# Destination supervisor register (shadow not currently supported)
+Sd6: sd6 is sd6 { export sd6; }
+Sdd6: sdd6 is sdd6 { export sdd6; }
+
+# Destination register (displays reg but exports shadow-reg)
+# NOTE: Unconditional auto-commit use only
+Rdd5: rdd5 is rdd5 & rdd5_ { # facilitates Nreg use in packet
+ export rdd5_;
+ <>
+ rdd5 = rdd5_;
+}
+Rd5: rd5 is rd5 & rd5_ & SetNRegRd5 & cond=0 { # facilitates Nreg use in packet
+ export rd5_;
+ <>
+ rd5 = rd5_;
+}
+Rxx5: rxx5 is rxx5 & rxx5_ { # facilitates Nreg use in packet
+ export rxx5_;
+ <>
+ rxx5 = rxx5_;
+}
+Rx5: rx5 is rx5 & rx5_ & SetNRegRx5 { # facilitates Nreg use in packet
+ export rx5_;
+ <>
+ rx5 = rx5_;
+}
+Rd0812: rd0812 is rd0812 & rd0812_ & SetNRegRd0812 { # facilitates Nreg use in packet
+ export rd0812_;
+ <>
+ rd0812 = rd0812_;
+}
+Rdd0812: rdd0812 is rdd0812 & rdd0812_ & SetNRegRd0812 { # facilitates Nreg use in packet
+ export rdd0812_;
+ <>
+ rdd0812 = rdd0812_;
+}
+Rx5H: rx5H is rx5H & rx5H_ { # TODO: Do we need to set nreg ?
+ export rx5H_;
+ <>
+ rx5H = rx5H_;
+}
+Rx5L: rx5L is rx5L & rx5L_ { # TODO: Do we need to set nreg ?
+ export rx5L_;
+ <>
+ rx5L = rx5L_;
+}
+Rd0811: rd0811 is rd0811 & rd0811_ { # TODO: Do we need to set nreg ?
+ export rd0811_;
+ <>
+ rd0811 = rd0811_;
+}
+Rd1619: rd1619 is rd1619 & rd1619_ { # TODO: Do we need to set nreg ?
+ export rd1619_;
+ <>
+ rd1619 = rd1619_;
+}
+
+Rdd3l: rdd3l is rdd3l & rdd3l_ {
+ export rdd3l_;
+ <>
+ rdd3l = rdd3l_;
+}
+Rdd3r: rdd3r is rdd3r & rdd3r_ {
+ export rdd3r_;
+ <>
+ rdd3r = rdd3r_;
+}
+Rd4l: rd4l is rd4l & rd4l_ {
+ export rd4l_;
+ <>
+ rd4l = rd4l_;
+}
+Rd4r: rd4r is rd4r & rd4r_ {
+ export rd4r_;
+ <>
+ rd4r = rd4r_;
+}
+
+# Source registers
+
+Ru5HL21: ru5L is op21=0 & ru5L { export ru5L; }
+Ru5HL21: ru5H is op21=1 & ru5H { export ru5H; }
+
+Rt5HL21: rt5L is op21=0 & rt5L { export rt5L; }
+Rt5HL21: rt5H is op21=1 & rt5H { export rt5H; }
+
+Rt5HL06: rt5L is op6=0 & rt5L { export rt5L; }
+Rt5HL06: rt5H is op6=1 & rt5H { export rt5H; }
+
+Rt5HL05: rt5L is op5=0 & rt5L { export rt5L; }
+Rt5HL05: rt5H is op5=1 & rt5H { export rt5H; }
+
+Rs5HL06: rs5L is op6=0 & rs5L { export rs5L; }
+Rs5HL06: rs5H is op6=1 & rs5H { export rs5H; }
+
+Rs5HL05: rs5L is op5=0 & rs5L { export rs5L; }
+Rs5HL05: rs5H is op5=1 & rs5H { export rs5H; }
+
+OnesCompRs5: "~"^rs5 is rs5 { tmp:4 = ~rs5; export tmp; }
+OnesCompRss5: "~"^rss5 is rss5 { tmp:8 = ~rss5; export tmp; }
+
+OnesCompRt5: "~"^rt5 is rt5 { tmp:4 = ~rt5; export tmp; }
+
+define pcodeop conjugate;
+Rt5Conjugate: rt5^"*" is rt5 { tmp:4 = conjugate(rt5); export tmp; }
+Rtt5Conjugate: rtt5^"*" is rtt5 { tmp:8 = conjugate(rtt5); export tmp; }
+
+#
+# P0 - P3 register modes
+#
+# NOTE: A predicate destination register must be auto-AND'd with it previous .new state
+# which is initially set to 0xff to allow for this.
+#
+
+# Destination
+# NOTE: Unconditional commit use only
+Pd2: pu0001 is pu0001 & pu0001_ {
+ export pu0001_;
+ <>
+ pu0001 = pu0001_;
+}
+Pd25: pu25 is pu25 & pu25_ {
+ export pu25_;
+ <>
+ pu25 = pu25_;
+}
+Pd12: pu12 is pu12 & pu12_ {
+ export pu12_;
+ <>
+ pu12 = pu12_;
+}
+P0dest: P0 is P0 {
+ export P0.new;
+ <>
+ P0 = P0.new;
+}
+
+Pd0506: pu0506 is pu0506 & pu0506_ {
+ export pu0506_;
+ <>
+ pu0506 = pu0506_;
+}
+
+NotPs2: "!"^pu1617 is pu1617 { tmp:1 = !pu1617; export tmp; }
+
+# Relative Destination Address (relative to start of packet)
+# NOTE: All relative addresses support immext (relative offset is not shifted when immext is present and first two bits always cleared)
+# NOTE: Use of immext only appends 6 low-order bits to immext, although resulting bit-0 and bit-1 are cleared/ignored by hardware.
+@define PKT_START "inst_start - (4 * packetOffset)"
+
+RelDest22x: val is s1624 & i0113 & immexted=0 [ val = (((s1624 << 13) | i0113) << 2) + $(PKT_START); ] { export *[ram]:4 val; }
+RelDest22x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; }
+
+@define r15_2_val "((s2223 << 13) | (i1620 << 8) | (i13 << 7) | i0107)"
+RelDest15x: val is i0107 & i13 & i1620 & s2223 & immexted=0 [ val = ($(r15_2_val) << 2) + $(PKT_START); ] { export *[ram]:4 val; }
+RelDest15x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; }
+
+@define r13_2_val "((s21 << 12) | (op13 << 11) | i0111)"
+RelDest13: val is i0111 & op13 & s21 [ val = ($(r13_2_val) << 2) + $(PKT_START); ] { export *[ram]:4 val; }
+
+RelDest9x: val is i0107 & s2021 & immexted=0 [ val = (((s2021 << 7) | i0107) << 2) + $(PKT_START); ] { export *[ram]:4 val; }
+RelDest9x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; }
+
+#
+# Non-extended Immediates
+#
+
+Simm8_0813: "#"^s0813 is s0813 { export *[const]:1 s0813; }
+Simm8_0512: "#"^s0512 is s0512 { export *[const]:1 s0512; }
+Simm8_0410: "#"^s0410 is s0410 { export *[const]:1 s0410; }
+Simm8_1620_05: "#"^val is s1620 & i5 [ val = (s1620 << 1) | i5; ] { export *[const]:1 val; }
+Simm8_1622_13: "#"^val is s1622 & i13 [ val = (s1622 << 1) | i13; ] { export *[const]:1 val; }
+
+Uimm16_21_0513: "#"^val is op21 & i0513 [ val = (op21 << 9) | i0513; ] { export *[const]:2 val; }
+Uimm16_2223_0013: "#"^val is i2223 & i0013 [ val = (i2223 << 14) | i0013; ] { export *[const]:2 val; }
+
+Uimm10_1617_0812_0204: "#"^val is i1617 & i0812 & i0204 [ val = (i1617 << 8) | (i0812 << 3) | i0204; ] { export *[const]:2 val; }
+
+
+Uimm8_2123_0507: "#"^val is i2123 & i0507 [ val = (i2123 << 3) | i0507; ] { export *[const]:1 val; }
+Uimm8_2122_0507: "#"^val is i2122 & i0507 [ val = (i2122 << 3) | i0507; ] { export *[const]:1 val; }
+
+Uimm8_23_0004: "#"^val is op23 & i0004 [ val = (op23 << 5) | i0004; ] { export *[const]:1 val; }
+Uimm8_21_0507: "#"^val is op21 & i0507 [ val = (op21 << 3) | i0507; ] { export *[const]:1 val; }
+Uimm8_0812_0204: "#"^val is i0812 & i0204 [ val = (i0812 << 3) | i0204; ] { export *[const]:1 val; }
+Uimm8_0813: "#"^i0813 is i0813 { export *[const]:1 i0813; }
+Uimm8_0812: "#"^i0812 is i0812 { export *[const]:1 i0812; }
+Uimm8_0811: "#"^i0811 is i0811 { export *[const]:1 i0811; }
+Uimm8_0512: "#"^i0512 is i0512 { export *[const]:1 i0512; }
+Uimm8_0511: "#"^i0511 is i0511 { export *[const]:1 i0511; }
+Uimm8_0509: "#"^i0509 is i0509 { export *[const]:1 i0509; }
+Uimm8_0507: "#"^i0507 is i0507 { export *[const]:1 i0507; }
+Uimm8_0409: "#"^i0409 is i0409 { export *[const]:1 i0409; }
+Uimm8_0004: "#"^i0004 is i0004 { export *[const]:1 i0004; }
+Uimm8_0001: "#"^i0001 is i0001 { export *[const]:1 i0001; }
+
+Uimm3_0507: "#"^i0507 is i0507 { export *[const]:1 i0507; }
+
+Uimm2_13_07: "#"^val is op13 & op7 [ val = (op13 << 1) | op7; ] { export *[const]:1 val; }
+Uimm2_13_06: "#"^val is op13 & op6 [ val = (op13 << 1) | op6; ] { export *[const]:1 val; }
+Uimm2_13_05: "#"^val is op13 & op5 [ val = (op13 << 1) | op5; ] { export *[const]:1 val; }
+Uimm2_1617: "#"^op1617 is op1617 { export *[const]:1 op1617; }
+Uimm2_2122: "#"^op2122 is op2122 { export *[const]:1 op2122; }
+Uimm2_1920: "#"^op1920 is op1920 { export *[const]:1 op1920; }
+Uimm2_0304: "#"^i0304 is i0304 { export *[const]:1 i0304; }
+Uimm2_0506: "#"^i0506 is i0506 { export *[const]:1 i0506; }
+
+Uimm1_24: "#"^i24 is i24 { export *[const]:1 i24; }
+Uimm1_08: "#"^i8 is i8 { export *[const]:1 i8; }
+Uimm1_05: "#"^i5 is i5 { export *[const]:1 i5; }
+
+#
+# Non-extended Immediates with shift factor
+#
+Uimm8_0408_shift3: "#"^val is i0408 [ val = i0408 << 3; ] { export *[const]:1 val; }
+Uimm8_0409_shift2: "#"^val is i0409 [ val = i0409 << 2; ] { export *[const]:1 val; }
+Uimm16_0010_shift3: "#"^val is i0010 [ val = i0010 << 3; ] { export *[const]:2 val; }
+Uimm8_2025_shift2: "#"^val is i2025 [ val = i2025 << 2; ] { export *[const]:1 val; }
+Uimm32_2122_13_0507_shift2: "#"^val is i2122 & i13 & i0507 [ val = ((i2122 << 4) | (i13 << 3) | i0507) << 2; ] { export *[const]:4 val; }
+
+
+#
+# Extended Immediates (see immext)
+# Double-# indicates use of extended immediate value
+
+Simm32_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:4 val; }
+Simm32_13_0006x: "##"^val is s13 & i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:4 val; } # u32
+
+Simm32_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:4 val; }
+Simm32_13_0004x: "##"^val is op13 & i0004 & immexted=1 [ val = (immext << 6) | (op13 << 5) | i0004; ] { export *[const]:4 val; } # u32
+
+Simm32_0512x: "#"^s0512 is s0512 & immexted=0 { export *[const]:4 s0512; }
+Simm32_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32
+
+Simm32_2127_0513x: "#"^val is s2127 & i0513 & immexted=0 [ val = (s2127 << 9) | i0513; ] { export *[const]:4 val; }
+Simm32_2127_0513x: "##"^val is i0510 & immexted=1 [ val = (simmext << 6) | i0510; ] { export *[const]:4 val; } # s32
+
+Simm32_2223_1620_0513x: "#"^val is s2223 & i1620 & i0513 & immexted=0 [ val = (s2223 << 14) | (i1620 << 9) | i0513; ] { export *[const]:4 val; }
+Simm32_2223_1620_0513x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32
+
+Simm32_2122_13_0507x: "#"^val is s2122 & i13 & i0507 & immexted=0 [ val = (s2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; }
+Simm32_2122_13_0507x: "##"^val is i2122 & i13 & i0507 & immexted=1 [ val = (immext << 6) | (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } # u32
+
+Simm32_21_0513x: "#"^val is s21 & i0513 & immexted=0 [ val = (s21 << 9) | i0513; ] { export *[const]:4 val; }
+Simm32_21_0513x: "##"^val is s21 & i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32
+
+Simm32_1619_0512x: "#"^val is s1619 & i0512 & immexted=0 [ val = (s1619 << 8) | i0512; ] { export *[const]:4 val; }
+Simm32_1619_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32
+
+Simm32_2026x: "#"^s2026 is s2026 & immexted=0 { export *[const]:4 s2026; }
+Simm32_2026x: "##"^val is i2025 & immexted=1 [ val = (simmext << 6) | i2025; ] { export *[const]:4 val; } # s32
+
+Uimm32_2123_13_0507_03x: "#"^val is i2123 & i13 & i0507 & i3 & immexted=0 [ val = (i2123 << 5) | (i13 << 4) | (i0507 << 1) | i3; ] { export *[const]:4 val; }
+Uimm32_2123_13_0507_03x: "##"^val is op21 & i13 & i0507 & i3 & immexted=1 [ val = (immext << 6) | (op21 << 5) | (i13 << 4) | (i0507 << 1) | i3; ] { export *[const]:4 val; }
+
+Uimm32_2122_13_0507x: "#"^val is i2122 & i13 & i0507 & immexted=0 [ val = (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; }
+Uimm32_2122_13_0507x: "##"^val is i2122 & i13 & i0507 & immexted=1 [ val = (immext << 6) | (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; }
+
+Uimm32_1620_13x: "#"^val is i1620 & i13 & immexted=0 [ val = (i1620 << 1) | i13; ] { export *[const]:4 val; }
+Uimm32_1620_13x: "##"^val is i1620 & i13 & immexted=1 [ val = (immext << 6) | (i1620 << 1) | i13; ] { export *[const]:4 val; }
+
+Uimm32_1620_08x: "#"^val is i1620 & i8 & immexted=0 [ val = (i1620 << 1) | i8; ] { export *[const]:4 val; }
+Uimm32_1620_08x: "##"^val is i1620 & i8 & immexted=1 [ val = (immext << 6) | (i1620 << 1) | i8; ] { export *[const]:4 val; }
+
+Uimm32_1617_0306x: "#"^val is i1617 & i0306 & immexted=0 [ val = (i1617 << 4) | i0306; ] { export *[const]:4 val; }
+Uimm32_1617_0306x: "##"^val is i1617 & i0306 & immexted=1 [ val = (immext << 6) | (i1617 << 4) | i0306; ] { export *[const]:4 val; }
+
+Uimm32_0811_0506x: "#"^val is i0811 & i0506 & immexted=0 [ val = (i0811 << 2) | i0506; ] { export *[const]:4 val; }
+Uimm32_0811_0506x: "##"^val is i0811 & i0506 & immexted=1 [ val = (immext << 6) | (i0811 << 2) | i0506; ] { export *[const]:4 val; }
+
+Uimm32_0712x: "#"^i0712 is i0712 & immexted=0 { export *[const]:4 i0712; }
+Uimm32_0712x: "##"^val is i0712 & immexted=1 [ val = (simmext << 6) | i0712; ] { export *[const]:4 val; } # s32
+
+Uimm32_0513x: "#"^i0513 is i0513 & immexted=0 { export *[const]:4 i0513; }
+Uimm32_0513x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; }
+
+Uimm32_0512x: "#"^i0512 is i0512 & immexted=0 { export *[const]:4 i0512; }
+Uimm32_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; }
+
+Uimm32_2025x: "#"^i2025 is i2025 & immexted=0 { export *[const]:4 i2025; }
+Uimm32_2025x: "##"^val is i2025 & immexted=1 [ val = (immext << 6) | i2025; ] { export *[const]:4 val; }
+
+Uimm32_0005x: "#"^i0005 is i0005 & immexted=0 { export *[const]:4 i0005; }
+Uimm32_0005x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:4 val; }
+
+# Truncated Extended Immediates
+# TODO: Should we be truncating extended constant values? Maybe not
+# Assembler does permit extended immediate +/- values larger than operation size:
+# p0 = cmpb.gtu (r1, ##212321)
+
+Simm16_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:2 val; }
+Simm16_13_0006x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:2 val; } # u32
+
+Simm8_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:1 val; }
+Simm8_13_0006x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:1 val; } # u32
+
+Simm8_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:1 val; }
+Simm8_13_0004x: "##"^val is i13 & i0004 & immexted=1 [ val = (immext << 6) | (i13 << 5) | i0004; ] { export *[const]:1 val; } # u32
+
+Simm16_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:2 val; }
+Simm16_13_0004x: "##"^val is i13 & i0004 & immexted=1 [ val = (immext << 6) | (i13 << 5) | i0004; ] { export *[const]:2 val; } # u32
+
+Uimm8_0511x: "#"^i0511 is i0511 & immexted=0 { export *[const]:1 i0511; }
+Uimm8_0511x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:1 val; }
+
+Uimm16_0511x: "#"^i0511 is i0511 & immexted=0 { export *[const]:2 i0511; }
+Uimm16_0511x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:2 val; }
+
+Simm16_0512x: "#"^s0512 is s0512 & immexted=0 { export *[const]:2 s0512; }
+Simm16_0512x: "##"^val is i0510 & immexted=1 [ val = (simmext << 6) | i0510; ] { export *[const]:2 val; }
+
+# Clear mask which can be and-ed with source
+ClrBit_0004w: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:4 = ~(1 << Uimm8_0004); export mask; }
+ClrBit_0004h: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:2 = ~(1 << Uimm8_0004); export mask; }
+ClrBit_0004b: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:1 = ~(1 << Uimm8_0004); export mask; }
+
+# Set mask which can be or-ed with source
+SetBit_0004w: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:4 = 1 << Uimm8_0004; export mask; }
+SetBit_0004h: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:2 = 1 << Uimm8_0004; export mask; }
+SetBit_0004b: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:1 = 1 << Uimm8_0004; export mask; }
+
+# embedded shift operand (Class-13): asl(Rx32,#U5) and lsr(Rx32,#U5)
+ShiftRx_D04_I0812: "asl("^rx5,Uimm8_0812^")" is op4=0 & rx5 & Uimm8_0812 { tmp:4 = rx5 << Uimm8_0812; export tmp; }
+ShiftRx_D04_I0812: "lsr("^rx5,Uimm8_0812^")" is op4=1 & rx5 & Uimm8_0812 { tmp:4 = rx5 >> Uimm8_0812; export tmp; }
+
+# embedded predicate and/or logic operand (Class-6): and(Pt4,[!]Pu4) and or(Pt4,[!]Pu4 )
+# NOTE: Decided to implement as full byte logic instead of single-bit boolean logic
+PredLogic_S23_P0607: pu0607 is op23=0 & pu0607 { export pu0607; }
+PredLogic_S23_P0607: "!"^pu0607 is op23=1 & pu0607 { tmp:1 = ~pu0607; export tmp; }
+PredLogic_L21_S23_P0809_P0607: "and("^pu0809,PredLogic_S23_P0607^")" is op21=0 & pu0809 & PredLogic_S23_P0607 { tmp:1 = pu0809 & PredLogic_S23_P0607; export tmp; }
+PredLogic_L21_S23_P0809_P0607: "or("^pu0809,PredLogic_S23_P0607^")" is op21=1 & pu0809 & PredLogic_S23_P0607 { tmp:1 = pu0809 | PredLogic_S23_P0607; export tmp; }
+
+
+# Taken/Not-Taken (decoration only)
+
+Taken13: ":t" is op13=1 { }
+Taken13: ":nt" is op13=0 { }
+
+Taken12: ":t" is op12=1 { }
+Taken12: ":nt" is op12=0 { }
+
+NotTaken01: ":nt" is op1=1 { }
+NotTaken01: is op1=0 { }
+
+# Predicate Register Condition for jump/call (least significant bit only)
+FlowCondUU: ".if("pu0809name")" is op21=0 & pu0809name & pu0809 {
+ condition:1 = (pu0809 & 1);
+ <>
+ ConditionReg = condition;
+}
+FlowCondUU: ".if(!"pu0809name")" is op21=1 & pu0809name & pu0809 {
+ condition:1 = !(pu0809 & 1);
+ <>
+ ConditionReg = condition;
+}
+
+# .new Predicate Register Condition for jump/call (least significant bit only)
+FlowCondNewUU: ".if("pu0809name".new)" is op21=0 & pu0809name & pu0809 {
+ <>
+ ConditionReg = (pu0809 & 1); # predicate will already be comitted
+}
+FlowCondNewUU: ".if(!"pu0809name".new)" is op21=1 & pu0809name & pu0809 {
+ <>
+ ConditionReg = !(pu0809 & 1); # predicate will already be comitted
+}
+
+# Predicate Register Condition for dealloc_return (least significant bit only)
+
+FlowCond0809_N11_S13: ".if("pu0809name")" is op13=0 & op11=0 & pu0809 & pu0809name {
+ condition:1 = (pu0809 & 1);
+ <>
+ ConditionReg = condition;
+}
+FlowCond0809_N11_S13: ".if(!"pu0809name")" is op13=1 & op11=0 & pu0809 & pu0809name {
+ condition:1 = !(pu0809 & 1);
+ <>
+ ConditionReg = condition;
+}
+FlowCond0809_N11_S13: ".if("pu0809name".new)" is op13=0 & op11=1 & pu0809 & pu0809name {
+ <>
+ ConditionReg = (pu0809 & 1); # predicate will already be comitted
+}
+FlowCond0809_N11_S13: ".if(!"pu0809name".new)" is op13=1 & op11=1 & pu0809 & pu0809name {
+ <>
+ ConditionReg = !(pu0809 & 1); # predicate will already be comitted
+}
+
+
+# Predicate Register Condition for Right Packed EE jumpr (least significant bit only, includes .new handling)
+
+FlowP0Cond_N01_S00: ".if(P0)" is op0=0 & op1=0 {
+ condition:1 = (P0 & 1);
+ <>
+ ConditionReg = condition;
+}
+FlowP0Cond_N01_S00: ".if(!P0)" is op0=1 & op1=0 {
+ condition:1 = !(P0 & 1);
+ <>
+ ConditionReg = condition;
+}
+FlowP0Cond_N01_S00: ".if(P0.new)" is op0=0 & op1=1 {
+ <>
+ ConditionReg = (P0 & 1); # P0 will already be comitted
+}
+FlowP0Cond_N01_S00: ".if(!P0.new)" is op0=1 & op1=1 {
+ <>
+ ConditionReg = !(P0 & 1); # P0 will already be comitted
+}
+
+
+# Predicate Register Condition for Right Packed EE conditional ops (least significant bit only, includes .new handling)
+
+P0Cond_N05_S04: ".if(P0)" is op4=0 & op5=1 {
+ condition:1 = (P0 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+P0Cond_N05_S04: ".if(!P0)" is op4=1 & op5=1 {
+ condition:1 = !(P0 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+P0Cond_N05_S04: ".if(P0.new)" is op4=0 & op5=0 {
+ condition:1 = 0;
+ <>
+ condition = (P0.new & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+P0Cond_N05_S04: ".if(!P0.new)" is op4=1 & op5=0 {
+ condition:1 = 0;
+ <>
+ condition = !(P0.new & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition for Left Packed EE conditional ops (least significant bit only, includes .new handling)
+
+P0Cond_N21_S20: ".if(P0)" is op20=0 & op21=1 {
+ condition:1 = (P0 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+P0Cond_N21_S20: ".if(!P0)" is op20=1 & op21=1 {
+ condition:1 = !(P0 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+P0Cond_N21_S20: ".if(P0.new)" is op20=0 & op21=0 {
+ condition:1 = 0;
+ <>
+ condition = (P0.new & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+P0Cond_N21_S20: ".if(!P0.new)" is op20=1 & op21=0 {
+ condition:1 = 0;
+ <>
+ condition = !(P0.new & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory store which must be in last slot.
+
+PuCond0001_N07_S02: ".if("pu0001name")" is op2=0 & op7=0 & pu0001 & pu0001name {
+ condition:1 = (pu0001 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N07_S02: ".if(!"pu0001name")" is op2=1 & op7=0 & pu0001 & pu0001name {
+ condition:1 = !(pu0001 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N07_S02: ".if("pu0001name".new)" is op2=0 & op7=1 & pu0001_ & pu0001name {
+ condition:1 = 0;
+ <>
+ condition = (pu0001_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N07_S02: ".if(!"pu0001name".new)" is op2=1 & op7=1 & pu0001_ & pu0001name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0001_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory store which must be in last slot.
+
+PuCond0001_N13_S02: ".if("pu0001name")" is op2=0 & op13=0 & pu0001 & pu0001name {
+ condition:1 = (pu0001 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N13_S02: ".if(!"pu0001name")" is op2=1 & op13=0 & pu0001 & pu0001name {
+ condition:1 = !(pu0001 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N13_S02: ".if("pu0001name".new)" is op2=0 & op13=1 & pu0001_ & pu0001name {
+ condition:1 = 0;
+ <>
+ condition = (pu0001_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N13_S02: ".if(!"pu0001name".new)" is op2=1 & op13=1 & pu0001_ & pu0001name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0001_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory store which must be in last slot.
+
+PuCond0001_N25_S26: ".if("pu0001name")" is op26=0 & op25=0 & pu0001 & pu0001name {
+ condition:1 = (pu0001 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N25_S26: ".if(!"pu0001name")" is op26=1 & op25=0 & pu0001 & pu0001name {
+ condition:1 = !(pu0001 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N25_S26: ".if("pu0001name".new)" is op26=0 & op25=1 & pu0001_ & pu0001name {
+ condition:1 = 0;
+ <>
+ condition = (pu0001_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0001_N25_S26: ".if(!"pu0001name".new)" is op26=1 & op25=1 & pu0001_ & pu0001name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0001_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+
+PuCond0809_N10_S11: ".if("pu0809name")" is op11=0 & op10=0 & pu0809 & pu0809name {
+ condition:1 = (pu0809 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0809_N10_S11: ".if(!"pu0809name")" is op11=1 & op10=0 & pu0809 & pu0809name {
+ condition:1 = !(pu0809 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0809_N10_S11: ".if("pu0809name".new)" is op11=0 & op10=1 & pu0809_ & pu0809name {
+ condition:1 = 0;
+ <>
+ condition = (pu0809_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0809_N10_S11: ".if(!"pu0809name".new)" is op11=1 & op10=1 & pu0809_ & pu0809name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0809_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory load which must be in last slot.
+
+PuCond0910_N12_S11: ".if("pu0910name")" is op11=0 & op12=0 & pu0910 & pu0910name {
+ condition:1 = (pu0910 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0910_N12_S11: ".if(!"pu0910name")" is op11=1 & op12=0 & pu0910 & pu0910name {
+ condition:1 = !(pu0910 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0910_N12_S11: ".if("pu0910name".new)" is op11=0 & op12=1 & pu0910_ & pu0910name {
+ condition:1 = 0;
+ <>
+ condition = (pu0910_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0910_N12_S11: ".if(!"pu0910name".new)" is op11=1 & op12=1 & pu0910_ & pu0910name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0910_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory load which must be in last slot.
+
+PuCond1112_N25_S26: ".if("pu1112name")" is op26=0 & op25=0 & pu1112 & pu1112name {
+ condition:1 = (pu1112 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond1112_N25_S26: ".if(!"pu1112name")" is op26=1 & op25=0 & pu1112 & pu1112name {
+ condition:1 = !(pu1112 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond1112_N25_S26: ".if("pu1112name".new)" is op26=0 & op25=1 & pu1112_ & pu1112name {
+ condition:1 = 0;
+ <>
+ condition = (pu1112_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond1112_N25_S26: ".if(!"pu1112name".new)" is op26=1 & op25=1 & pu1112_ & pu1112name {
+ condition:1 = 0;
+ <>
+ condition = !(pu1112_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+
+PuCond2122_N13_S23: ".if("pu2122name")" is op23=0 & op13=0 & pu2122 & pu2122name {
+ condition:1 = (pu2122 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond2122_N13_S23: ".if(!"pu2122name")" is op23=1 & op13=0 & pu2122 & pu2122name {
+ condition:1 = !(pu2122 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond2122_N13_S23: ".if("pu2122name".new)" is op23=0 & op13=1 & pu2122_ & pu2122name {
+ condition:1 = 0;
+ <>
+ condition = (pu2122_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond2122_N13_S23: ".if(!"pu2122name".new)" is op23=1 & op13=1 & pu2122_ & pu2122name {
+ condition:1 = 0;
+ <>
+ condition = !(pu2122_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+
+PuCond0506_N13_S07: ".if("pu0506name")" is op7=0 & op13=0 & pu0506 & pu0506name {
+ condition:1 = (pu0506 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N13_S07: ".if(!"pu0506name")" is op7=1 & op13=0 & pu0506 & pu0506name {
+ condition:1 = !(pu0506 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N13_S07: ".if("pu0506name".new)" is op7=0 & op13=1 & pu0506_ & pu0506name {
+ condition:1 = 0;
+ <>
+ condition = (pu0506_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N13_S07: ".if(!"pu0506name".new)" is op7=1 & op13=1 & pu0506_ & pu0506name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0506_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory load/store which must be in last slot.
+
+PuCond0506_N25_S24: ".if("pu0506name")" is op24=0 & op25=0 & pu0506 & pu0506name {
+ condition:1 = (pu0506 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N25_S24: ".if(!"pu0506name")" is op24=1 & op25=0 & pu0506 & pu0506name {
+ condition:1 = !(pu0506 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N25_S24: ".if("pu0506name".new)" is op24=0 & op25=1 & pu0506_ & pu0506name {
+ condition:1 = 0;
+ <>
+ condition = (pu0506_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N25_S24: ".if(!"pu0506name".new)" is op24=1 & op25=1 & pu0506_ & pu0506name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0506_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+# Predicate Register Condition (least significant bit only, includes .new handling)
+# Only used by memory store which must be in last slot.
+
+PuCond0506_N24_S23: ".if("pu0506name")" is op23=0 & op24=0 & pu0506 & pu0506name {
+ condition:1 = (pu0506 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N24_S23: ".if(!"pu0506name")" is op23=1 & op24=0 & pu0506 & pu0506name {
+ condition:1 = !(pu0506 & 1);
+ <>
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N24_S23: ".if("pu0506name".new)" is op23=0 & op24=1 & pu0506_ & pu0506name {
+ condition:1 = 0;
+ <>
+ condition = (pu0506_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+PuCond0506_N24_S23: ".if(!"pu0506name".new)" is op23=1 & op24=1 & pu0506_ & pu0506name {
+ condition:1 = 0;
+ <>
+ condition = !(pu0506_ & 1); # use new predicate
+ ConditionReg = condition;
+ <>
+ ConditionReg = condition;
+}
+
+
+#
+# Class-3 Memory Access
+#
+
+# Class-3 Store Memory: Rs+#u6 - (u6 is NOT extended)
+StAddrRsRelC3: "("^rs5^")" is rs5 & i0712=0 {
+ ptr:4 = rs5; # must use temp for delayed reference
+ export ptr;
+}
+StAddrRsRelC3: "("^rs5^"+#"^offs^")" is rs5 & i0712 [ offs = i0712 << shift; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+#StMemRsRelC3d: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 3; ] { export *[ram]:8 StAddrRsRelC3; }
+StMemRsRelC3w: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 2; ] { export *[ram]:4 StAddrRsRelC3; }
+StMemRsRelC3h: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 1; ] { export *[ram]:2 StAddrRsRelC3; }
+StMemRsRelC3b: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 0; ] { export *[ram]:1 StAddrRsRelC3; }
+
+# Class-3 Store Memory: Rs+#u6x - (u6 is extended)
+StAddrRsRelxC3: "("^rs5^")" is rs5 & i0712=0 & immexted=0 {
+ ptr:4 = rs5; # must use temp for delayed reference
+ export ptr;
+}
+StAddrRsRelxC3: "("^rs5^"+#"^offs^")" is rs5 & i0712 & immexted=0 [ offs = i0712 << shift; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+StAddrRsRelxC3: "("^rs5^"+##"^offs^")" is rs5 & i0712 & immexted=1 [ offs = (immext << 6) | i0712; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+#StMemRsRelxC3d: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC3; }
+StMemRsRelxC3w: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC3; }
+StMemRsRelxC3h: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC3; }
+StMemRsRelxC3b: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC3; }
+
+
+# Class-3 Memory: Rs+Rt<<#n2
+AddrRsRelShiftC3: "("^rs5^"+"^rt5^")" is rs5 & rt5 & op13=0 & op7=0 {
+ tmp:4 = rs5 + rt5;
+ export tmp;
+}
+AddrRsRelShiftC3: "("^rs5^"+"^rt5^"<<"^Uimm2_13_07^")" is rs5 & rt5 & Uimm2_13_07 {
+ # TODO: verify order of operation
+ # TODO: Is there an alignment shift?
+ tmp:4 = rs5 + (rt5 << Uimm2_13_07);
+ export tmp;
+}
+MemRsRelShiftC3d: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:8 AddrRsRelShiftC3; }
+MemRsRelShiftC3w: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:4 AddrRsRelShiftC3; }
+MemRsRelShiftC3h: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:2 AddrRsRelShiftC3; }
+MemRsRelShiftC3b: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:1 AddrRsRelShiftC3; }
+
+
+#
+# Class-4 Memory Access
+#
+
+# Class-4 Load Memory: Rs+#u6x
+LdAddrRsRelxC4: "("^rs5^")" is rs5 & i0510=0 & immexted=0 {
+ ptr:4 = rs5; # must use temp for delayed reference
+ export ptr;
+}
+LdAddrRsRelxC4: "("^rs5^"+#"^offs^")" is rs5 & i0510 & immexted=0 [ offs = i0510 << shift; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+LdAddrRsRelxC4: "("^rs5^"+##"^offs^")" is rs5 & i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+LdMemRsRelxC4d: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 3; ] { export *[ram]:8 LdAddrRsRelxC4; }
+LdMemRsRelxC4w: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 2; ] { export *[ram]:4 LdAddrRsRelxC4; }
+LdMemRsRelxC4h: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 1; ] { export *[ram]:2 LdAddrRsRelxC4; }
+LdMemRsRelxC4b: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 0; ] { export *[ram]:1 LdAddrRsRelxC4; }
+
+# Class-4 Store Memory: Rs+#u6x
+StAddrRsRelxC4: "("^rs5^")" is rs5 & i13=0 & i0307=0 & immexted=0 {
+ ptr:4 = rs5; # must use temp for delayed reference
+ export ptr;
+}
+StAddrRsRelxC4: "("^rs5^"+#"^offs^")" is rs5 & i13 & i0307 & immexted=0 [ offs = ((i13 << 5) | i0307) << shift; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+StAddrRsRelxC4: "("^rs5^"+##"^offs^")" is rs5 & i13 & i0307 & immexted=1 [ offs = (immext << 6) | (i13 << 5) | i0307; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+StMemRsRelxC4d: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC4; }
+StMemRsRelxC4w: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC4; }
+StMemRsRelxC4h: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC4; }
+StMemRsRelxC4b: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC4; }
+
+# Class-4 Load Memory: GP+#u16x
+LdAddrGPRelxC4: "("^GP^"+#"^offs^")" is i2526 & i1620 & i0513 & GP & immexted=0
+ [ offs = ((i2526 << 14) | (i1620 << 9) | i0513) << shift; ] {
+ local ptr = GP + offs;
+ export ptr;
+}
+LdAddrGPRelxC4: "(##"^offs^")" is i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] {
+ export *[const]:4 offs;
+}
+LdMemGPRelxC4d: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 3; ] { export *[ram]:8 LdAddrGPRelxC4; }
+LdMemGPRelxC4w: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 2; ] { export *[ram]:4 LdAddrGPRelxC4; }
+LdMemGPRelxC4h: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 1; ] { export *[ram]:2 LdAddrGPRelxC4; }
+LdMemGPRelxC4b: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 0; ] { export *[ram]:1 LdAddrGPRelxC4; }
+
+# Class-4 Store Memory: GP+#u16x
+StAddrGPRelxC4: "("^GP^"+#"^offs^")" is i2526 & i1620 & i13 & i0007 & GP & immexted=0
+ [ offs = ((i2526 << 14) | (i1620 << 9) | (i13 << 8) | i0007) << shift; ] {
+ local ptr = GP + offs;
+ export ptr;
+}
+StAddrGPRelxC4: "(##"^offs^")" is i0005 & immexted=1 [ offs = (immext << 6) | i0005; ] {
+ export *[const]:4 offs;
+}
+StMemGPRelxC4d: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 3; ] { export *[ram]:8 StAddrGPRelxC4; }
+StMemGPRelxC4w: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 2; ] { export *[ram]:4 StAddrGPRelxC4; }
+StMemGPRelxC4h: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 1; ] { export *[ram]:2 StAddrGPRelxC4; }
+StMemGPRelxC4b: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 0; ] { export *[ram]:1 StAddrGPRelxC4; }
+
+
+#
+# Class-9 Memory Access
+#
+
+# Class-9 Load Memory: (Rs32)
+LdAddrRsRelC9: "("^rs5^")" is rs5 { export rs5; }
+LdMemRsRelC9d: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:8 LdAddrRsRelC9; }
+LdMemRsRelC9w: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:4 LdAddrRsRelC9; }
+#LdMemRsRelC9h: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:2 LdAddrRsRelC9; }
+#LdMemRsRelC9b: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:1 LdAddrRsRelC9; }
+
+# Class-9 Load Memory: Rf=#U6x
+LdAddrRsAssignxC9: "("^rf5^"="^Uimm32_0811_0506x^")" is rf5 & rf5_ & Uimm32_0811_0506x {
+ # TODO: Need to verify behavior !!
+ rf5_ = Uimm32_0811_0506x;
+ export Uimm32_0811_0506x;
+ <>
+ rf5 = rf5_;
+}
+LdMemRsAssignxC9d: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:8 LdAddrRsAssignxC9; }
+LdMemRsAssignxC9w: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:4 LdAddrRsAssignxC9; }
+LdMemRsAssignxC9h: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:2 LdAddrRsAssignxC9; }
+LdMemRsAssignxC9b: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:1 LdAddrRsAssignxC9; }
+
+# Class-9 Load Memory: #u6x
+LdAddrAbsU6xC9: "("^Uimm32_1620_08x^")" is Uimm32_1620_08x { export Uimm32_1620_08x; }
+
+LdMemAbsU6xC9d: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:8 LdAddrAbsU6xC9; }
+LdMemAbsU6xC9w: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:4 LdAddrAbsU6xC9; }
+LdMemAbsU6xC9h: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:2 LdAddrAbsU6xC9; }
+LdMemAbsU6xC9b: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:1 LdAddrAbsU6xC9; }
+
+
+# Class-9 Load Memory: ( Rs32 << #n2 + #U6x )
+LdAddrRsRelShiftxC9: "("^rs5^"+"^Uimm32_0811_0506x^")" is rs5 & op13=0 & op7=0 & Uimm32_0811_0506x {
+ tmp:4 = rs5 + Uimm32_0811_0506x;
+ export tmp;
+}
+LdAddrRsRelShiftxC9: "("^rs5^"<<"^Uimm2_13_07^"+"^Uimm32_0811_0506x^")" is rs5 & Uimm2_13_07 & Uimm32_0811_0506x {
+ # TODO: verify order of operation
+ # TODO: Is there an alignment shift?
+ tmp:4 = (rs5 << Uimm2_13_07) + Uimm32_0811_0506x;
+ export tmp;
+}
+LdMemRsRelShiftxC9d: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:8 LdAddrRsRelShiftxC9; }
+LdMemRsRelShiftxC9w: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:4 LdAddrRsRelShiftxC9; }
+LdMemRsRelShiftxC9h: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:2 LdAddrRsRelShiftxC9; }
+LdMemRsRelShiftxC9b: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:1 LdAddrRsRelShiftxC9; }
+
+
+# Class-9 Load Memory: Rs+#s11x
+LdAddrRsRelxC9: "("^rs5^")" is op27=0 & rs5 & i2526=0 & i0513=0 & immexted=0 {
+ ptr:4 = rs5; # must use temp for delayed reference
+ export ptr;
+}
+LdAddrRsRelxC9: "("^rs5^"+#"^offs^")" is op27=0 & rs5 & s2526 & i0513 & immexted=0
+ [ offs = ((s2526 << 9) | i0513) << shift; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+LdAddrRsRelxC9: "("^rs5^"+##"^offs^")" is op27=0 & rs5 & i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+LdMemRsRelxC9d: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 3; ] { export *[ram]:8 LdAddrRsRelxC9; }
+LdMemRsRelxC9w: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 2; ] { export *[ram]:4 LdAddrRsRelxC9; }
+LdMemRsRelxC9h: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 1; ] { export *[ram]:2 LdAddrRsRelxC9; }
+LdMemRsRelxC9b0: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 0; ] { export *[ram]:1 LdAddrRsRelxC9; }
+LdMemRsRelxC9b1: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 1; ] { export *[ram]:1 LdAddrRsRelxC9; }
+LdMemRsRelxC9b2: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 2; ] { export *[ram]:1 LdAddrRsRelxC9; }
+
+# Class-9 Load Memory: Rx++#s4 -- 'cond=1' context must be set by conditional instructions!
+LdAddrAIS4C9: "("^rx5^"++#"^inc^")" is cond=0 & rx5 & rx5_ & s0508 [ inc = s0508 << shift; ] {
+ tmp:4 = rx5 + inc;
+ export rx5;
+ <>
+ rx5 = tmp;
+}
+LdAddrAIS4C9: "("^rx5^"++#"^inc^")" is cond=1 & rx5 & rx5_ & s0508 [ inc = s0508 << shift; ] {
+ tmp:4 = rx5 + inc;
+ export rx5;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+LdMemAIS4C9d: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 3; ] { export *[ram]:8 LdAddrAIS4C9; }
+LdMemAIS4C9w: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 2; ] { export *[ram]:4 LdAddrAIS4C9; }
+LdMemAIS4C9h: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 1; ] { export *[ram]:2 LdAddrAIS4C9; }
+LdMemAIS4C9b0: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 0; ] { export *[ram]:1 LdAddrAIS4C9; }
+LdMemAIS4C9b1: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 1; ] { export *[ram]:1 LdAddrAIS4C9; }
+LdMemAIS4C9b2: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 2; ] { export *[ram]:1 LdAddrAIS4C9; }
+
+# Class-9 Load Memory: Rx++#s4:circ(Mu) -- 'cond=1' context must be set by conditional instructions!
+LdAddrAIS4CircMuC9: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu & s0508
+ [ inc = s0508 << shift; ] {
+ tmp:4 = circularAdd(rx5, inc:1, mu);
+ export rx5;
+ <>
+ rx5 = tmp;
+}
+LdAddrAIS4CircMuC9: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu & s0508
+ [ inc = s0508 << shift; ] {
+ tmp:4 = circularAdd(rx5, inc:1, mu);
+ export rx5;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+LdMemAIS4CircMuC9d: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 3; ] { export *[ram]:8 LdAddrAIS4CircMuC9; }
+LdMemAIS4CircMuC9w: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { export *[ram]:4 LdAddrAIS4CircMuC9; }
+LdMemAIS4CircMuC9h: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 1; ] { export *[ram]:2 LdAddrAIS4CircMuC9; }
+LdMemAIS4CircMuC9b0: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 0; ] { export *[ram]:1 LdAddrAIS4CircMuC9; }
+LdMemAIS4CircMuC9b1: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 1; ] { export *[ram]:1 LdAddrAIS4CircMuC9; }
+LdMemAIS4CircMuC9b2: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { export *[ram]:1 LdAddrAIS4CircMuC9; }
+
+# Class-9 Load Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions!
+LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu {
+ i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg
+ tmp:4 = circularAdd(rx5, i, mu);
+ export rx5;
+ <>
+ rx5 = tmp;
+}
+LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu {
+ i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg
+ tmp:4 = circularAdd(rx5, i, mu);
+ export rx5;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+LdMemAIICircMuC9d: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:8 LdAddrAIICircMuC9; }
+LdMemAIICircMuC9w: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:4 LdAddrAIICircMuC9; }
+LdMemAIICircMuC9h: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:2 LdAddrAIICircMuC9; }
+LdMemAIICircMuC9b: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:1 LdAddrAIICircMuC9; }
+
+# Class-9 Load Memory: Rx++Mu and Rx++Mu:brev - op25 selects mode -- 'cond=1' context must be set by conditional instructions!
+LdAddrAIMuC9: "("^rx5^"++"^mu^")" is cond=0 & op25=0 & rx5 & rx5_ & mu {
+ tmp:4 = rx5 + mu;
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+LdAddrAIMuC9: "("^rx5^"++"^mu^")" is cond=1 & op25=0 & rx5 & rx5_ & mu {
+ tmp:4 = rx5 + mu;
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+LdAddrAIMuC9: "("^rx5^"++"^mu^":brev)" is cond=0 & op25=1 & rx5 & rx5_ & mu {
+ ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff);
+ tmp:4 = rx5 + mu;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+LdAddrAIMuC9: "("^rx5^"++"^mu^":brev)" is cond=1 & op25=1 & rx5 & rx5_ & mu {
+ ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff);
+ tmp:4 = rx5 + mu;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+LdMemAIMuC9d: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:8 LdAddrAIMuC9; }
+LdMemAIMuC9w: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:4 LdAddrAIMuC9; }
+LdMemAIMuC9h: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:2 LdAddrAIMuC9; }
+LdMemAIMuC9b: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:1 LdAddrAIMuC9; }
+
+
+# Class-9 Load Memory: #u6x - (no shift factor)
+LdAddrU6xC9: "(#"^offs^")" is i1620 & i8 & immexted=0 [ offs = (i1620 << 1) | i8; ] {
+ export *[const]:4 offs;
+}
+LdAddrU6xC9: "(##"^offs^")" is i1620 & i8 & immexted=1 [ offs = (immext << 6) | (i1620 << 1) | i8; ] {
+ export *[const]:4 offs;
+}
+#LdMemU6xC9d: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:8 LdAddrU6xC9; }
+#LdMemU6xC9w: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:4 LdAddrU6xC9; }
+LdMemU6xC9h: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:2 LdAddrU6xC9; }
+#LdMemU6xC9b: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:1 LdAddrU6xC9; }
+
+
+#
+# Class-10 Memory Access
+#
+
+# Class-9 Load Memory: (Rs32, Pd4) # predicate displayed only!
+StAddrRsRelPdC9: "("^rs5,pu0001^")" is rs5 & pu0001 { export rs5; }
+StMemRsRelPdC9w: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:4 StAddrRsRelPdC9; }
+StMemRsRelPdC9d: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:8 StAddrRsRelPdC9; }
+#StMemRsRelPdC9h: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:2 StAddrRsRelPdC9; }
+#StMemRsRelPdC9b: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:1 StAddrRsRelPdC9; }
+
+# Class-10 Store Memory: Rf=#U6x -- 'cond=1' context must be set by conditional instructions!
+StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=0 & rf5 & rf5_ & Uimm32_0005x {
+ # TODO: Need to verify behavior !!
+ rf5_ = Uimm32_0005x;
+ export rf5_;
+ <>
+ rf5 = rf5_;
+}
+StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=1 & rf5 & rf5_ & Uimm32_0005x {
+ # TODO: Need to verify behavior !!
+ rf5_ = Uimm32_0005x;
+ export rf5_;
+ <>
+ if (ConditionReg == 0) goto ;
+ rf5 = rf5_;
+
+}
+StMemRsAssignxC10d: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:8 StAddrRsAssignxC10; }
+StMemRsAssignxC10w: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:4 StAddrRsAssignxC10; }
+StMemRsAssignxC10h: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:2 StAddrRsAssignxC10; }
+StMemRsAssignxC10b: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:1 StAddrRsAssignxC10; }
+
+# Class-10 Store Memory: #u6x
+StAddrAbsU6xC10: "("^Uimm32_1617_0306x^")" is Uimm32_1617_0306x { export Uimm32_1617_0306x; }
+
+StMemAbsU6xC10d: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:8 StAddrAbsU6xC10; }
+StMemAbsU6xC10w: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:4 StAddrAbsU6xC10; }
+StMemAbsU6xC10h: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:2 StAddrAbsU6xC10; }
+StMemAbsU6xC10b: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:1 StAddrAbsU6xC10; }
+
+# Class-10 Store Memory: ( Rs32 << #n2 + #U6x )
+StAddrRsRelShiftxC10: "("^rs5^"+"^Uimm32_0005x^")" is rs5 & op13=0 & op6=0 & Uimm32_0005x {
+ tmp:4 = rs5 + Uimm32_0005x;
+ export tmp;
+}
+StAddrRsRelShiftxC10: "("^rs5^"<<"^Uimm2_13_06^"+"^Uimm32_0005x^")" is rs5 & Uimm2_13_06 & Uimm32_0005x {
+ # TODO: verify order of operation
+ # TODO: Is there an alignment shift?
+ tmp:4 = (rs5 << Uimm2_13_06) + Uimm32_0005x;
+ export tmp;
+}
+StMemRsRelShiftxC10d: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:8 StAddrRsRelShiftxC10; }
+StMemRsRelShiftxC10w: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:4 StAddrRsRelShiftxC10; }
+StMemRsRelShiftxC10h: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:2 StAddrRsRelShiftxC10; }
+StMemRsRelShiftxC10b: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:1 StAddrRsRelShiftxC10; }
+
+# Class-10 Store Memory: Rs+#s11x
+StAddrRsRelxC10: "("^rs5^")" is op27=0 & rs5 & s2526=0 & i13=0 & i0007=0 & immexted=0 {
+ ptr:4 = rs5; # must use temp for delayed reference
+ export ptr;
+}
+StAddrRsRelxC10: "("^rs5^"+#"^offs^")" is op27=0 & rs5 & s2526 & i13 & i0007 & immexted=0
+ [ offs = ((s2526 << 9) | (i13 << 8) | i0007) << shift; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+StAddrRsRelxC10: "("^rs5^"+##"^offs^")" is op27=0 & rs5 & i0005 & immexted=1 [ offs = (immext << 6) | i0005; ] {
+ ptr:4 = rs5 + offs;
+ export ptr;
+}
+StMemRsRelxC10d: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC10; }
+StMemRsRelxC10w: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC10; }
+StMemRsRelxC10h: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC10; }
+StMemRsRelxC10b: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC10; }
+
+# Class-10 Store Memory: Rx++#s4 -- 'cond=1' context must be set by conditional instructions!
+StAddrAIS4C10: "("^rx5^"++#"^inc^")" is cond=0 & op2527=5 & rx5 & rx5_ & s0306
+ [ inc = s0306 << shift; ] {
+ tmp:4 = rx5 + inc;
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+StAddrAIS4C10: "("^rx5^"++#"^inc^")" is cond=1 & op2527=5 & rx5 & rx5_ & s0306
+ [ inc = s0306 << shift; ] {
+ tmp:4 = rx5 + inc;
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+StMemAIS4C10d: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 3; ] { export *[ram]:8 StAddrAIS4C10; }
+StMemAIS4C10w: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 2; ] { export *[ram]:4 StAddrAIS4C10; }
+StMemAIS4C10h: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 1; ] { export *[ram]:2 StAddrAIS4C10; }
+StMemAIS4C10b: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 0; ] { export *[ram]:1 StAddrAIS4C10; }
+
+# Class-10 Store Memory: Rx++#s4:circ(Mu) -- 'cond=1' context must be set by conditional instructions!
+StAddrAIS4CircMuC10: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=0 & s0306
+ [ inc = s0306 << shift; ] {
+ tmp:4 = circularAdd(rx5, inc:1, mu);
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+StAddrAIS4CircMuC10: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=0 & s0306
+ [ inc = s0306 << shift; ] {
+ tmp:4 = circularAdd(rx5, inc:1, mu);
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+StMemAIS4CircMuC10d: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 3; ] { export *[ram]:8 StAddrAIS4CircMuC10; }
+StMemAIS4CircMuC10w: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 2; ] { export *[ram]:4 StAddrAIS4CircMuC10; }
+StMemAIS4CircMuC10h: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 1; ] { export *[ram]:2 StAddrAIS4CircMuC10; }
+StMemAIS4CircMuC10b: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 0; ] { export *[ram]:1 StAddrAIS4CircMuC10; }
+
+# Class-10 Store Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions!
+StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=1 {
+ i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg
+ tmp:4 = circularAdd(rx5, i, mu);
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=1 {
+ i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg
+ tmp:4 = circularAdd(rx5, i, mu);
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+StMemAIICircMuC10d: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:8 StAddrAIICircMuC10; }
+StMemAIICircMuC10w: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:4 StAddrAIICircMuC10; }
+StMemAIICircMuC10h: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:2 StAddrAIICircMuC10; }
+StMemAIICircMuC10b: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:1 StAddrAIICircMuC10; }
+
+# Class-10 Store Memory: Rx++Mu and Rx++Mu:brev - op25 selects mode -- 'cond=1' context must be set by conditional instructions!
+StAddrAIMuC10: "("^rx5^"++"^mu^")" is cond=0 & op2527=6 & rx5 & rx5_ & mu {
+ tmp:4 = rx5 + mu;
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+StAddrAIMuC10: "("^rx5^"++"^mu^")" is cond=1 & op2527=6 & rx5 & rx5_ & mu {
+ tmp:4 = rx5 + mu;
+ ptr:4 = rx5;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+StAddrAIMuC10: "("^rx5^"++"^mu^":brev)" is cond=0 & op2527=7 & rx5 & rx5_ & mu {
+ ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff);
+ tmp:4 = rx5 + mu;
+ export ptr;
+ <>
+ rx5 = tmp;
+}
+StAddrAIMuC10: "("^rx5^"++"^mu^":brev)" is cond=1 & op2527=7 & rx5 & rx5_ & mu {
+ ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff);
+ tmp:4 = rx5 + mu;
+ export ptr;
+ <>
+ if (ConditionReg == 0) goto ;
+ rx5 = tmp;
+
+}
+StMemAIMuC10d: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:8 StAddrAIMuC10; }
+StMemAIMuC10w: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:4 StAddrAIMuC10; }
+StMemAIMuC10h: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:2 StAddrAIMuC10; }
+StMemAIMuC10b: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:1 StAddrAIMuC10; }
+
+
+#
+# Left Memory Access
+#
+
+# Left Sp-Relative Memory (Sp+#u5:2)
+MemSpRelU5Lw: "("^SP^"+#"^offs^")" is SP & i2024 [ offs = i2024 << 2; ] {
+ ptr:4 = SP + offs;
+ export *[ram]:4 ptr;
+}
+
+# Left Sp-Relative Memory (Sp+#u5:3)
+MemSpRelU5Ld: "("^SP^"+#"^offs^")" is SP & i1923 [ offs = i1923 << 3; ] {
+ ptr:4 = SP + offs;
+ export *[ram]:8 ptr;
+}
+
+# Left Sp-Relative Memory (Sp+#s6:3)
+MemSpRelS6Ld: "("^SP^"+#"^offs^")" is SP & s1924 [ offs = s1924 << 3; ] {
+ ptr:4 = SP + offs;
+ export *[ram]:8 ptr;
+}
+
+
+# Left Rs-Relative Memory (Rs16+#u4:2)
+MemRsRelU4Lw: "("^rs4l^")" is rs4l & i2427=0 {
+ ptr:4 = rs4l;
+ export *[ram]:4 ptr;
+}
+MemRsRelU4Lw: "("^rs4l^"+#"^offs^")" is rs4l & i2427 [ offs = i2427 << 2; ] {
+ ptr:4 = rs4l + offs;
+ export *[ram]:4 ptr;
+}
+
+# Left Rs-Relative Memory (Rs16+#u4:0)
+MemRsRelU4Lb: "("^rs4l^")" is rs4l & i2427=0 {
+ ptr:4 = rs4l;
+ export *[ram]:1 ptr;
+}
+MemRsRelU4Lb: "("^rs4l^"+#"^i2427^")" is rs4l & i2427 {
+ ptr:4 = rs4l + i2427;
+ export *[ram]:1 ptr;
+}
+
+# Left Rs-Relative Memory (Rs16+#u3:1)
+MemRsRelU3Lh: "("^rs4l^")" is rs4l & i2426=0 {
+ ptr:4 = rs4l;
+ export *[ram]:2 ptr;
+}
+MemRsRelU3Lh: "("^rs4l^"+#"^offs^")" is rs4l & i2426 [ offs = i2426 << 1; ] {
+ ptr:4 = rs4l + offs;
+ export *[ram]:2 ptr;
+}
+
+# Left Rs-Relative Memory (Rs16+#u3:0)
+MemRsRelU3Lb: "("^rs4l^")" is rs4l & i2426=0 {
+ ptr:4 = rs4l;
+ export *[ram]:1 ptr;
+}
+MemRsRelU3Lb: "("^rs4l^"+#"^i2426^")" is rs4l & i2426 {
+ ptr:4 = rs4l + i2426;
+ export *[ram]:1 ptr;
+}
+
+#
+# Class-15-Left Memory Access
+#
+
+# Class-15 (LEFT) Store Rs-Relative Memory (Rs16+#u4:2)
+StMemRsRelC15Lw: "("^rs4l^")" is rs4l & i1619=0 {
+ ptr:4 = rs4l;
+ export *[ram]:4 ptr;
+}
+StMemRsRelC15Lw: "("^rs4l^"+#"^offs^")" is rs4l & i1619 [ offs = i1619 << 2; ] {
+ ptr:4 = rs4l + offs;
+ export *[ram]:4 ptr;
+}
+
+# Class-15 (LEFT) Store Rs-Relative Memory (Rs16+#u4:0)
+StMemRsRelC15Lb: "("^rs4l^")" is rs4l & i1619=0 {
+ ptr:4 = rs4l;
+ export *[ram]:1 ptr;
+}
+StMemRsRelC15Lb: "("^rs4l^"+#"^i1619^")" is rs4l & i1619 {
+ ptr:4 = rs4l + i1619;
+ export *[ram]:1 ptr;
+}
+
+
+#
+# Right Memory Access (used with both Load and Store)
+#
+
+# Right Rs-Relative Memory (Rs16+#u4:2)
+MemRsRelU4Rw: "("^rs4r^")" is rs4r & i0811=0 {
+ ptr:4 = rs4r;
+ export *[ram]:4 ptr;
+}
+MemRsRelU4Rw: "("^rs4r^"+#"^offs^")" is rs4r & i0811 [ offs = i0811 << 2; ] {
+ ptr:4 = rs4r + offs;
+ export *[ram]:4 ptr;
+}
+
+# Right Rs-Relative Memory (Rs16+#u4:0)
+MemRsRelU4Rb: "("^rs4r^")" is rs4r & i0811=0 {
+ ptr:4 = rs4r;
+ export *[ram]:1 ptr;
+}
+MemRsRelU4Rb: "("^rs4r^"+#"^i0811^")" is rs4r & i0811 {
+ ptr:4 = rs4r + i0811;
+ export *[ram]:1 ptr;
+}
+
+# Right Rs-Relative Memory (Rs16+#u4:0)
+MemRsRelU4Rnb: "("^rs4r^")" is rs4r & i0003=0 {
+ ptr:4 = rs4r;
+ export *[ram]:1 ptr;
+}
+MemRsRelU4Rnb: "("^rs4r^"+#"^i0003^")" is rs4r & i0003 {
+ ptr:4 = rs4r + i0003;
+ export *[ram]:1 ptr;
+}
+
+# Right Rs-Relative Memory (Rs16+#u3:0)
+MemRsRelU3Rb: "("^rs4r^")" is rs4r & i0810=0 {
+ ptr:4 = rs4r;
+ export *[ram]:1 ptr;
+}
+MemRsRelU3Rb: "("^rs4r^"+#"^i0810^")" is rs4r & i0810 {
+ ptr:4 = rs4r + i0810;
+ export *[ram]:1 ptr;
+}
+
+# Right Rs-Relative Memory (Rs16+#u3:1)
+MemRsRelU3Rh: "("^rs4r^")" is rs4r & i0810=0 {
+ ptr:4 = rs4r;
+ export *[ram]:2 ptr;
+}
+MemRsRelU3Rh: "("^rs4r^"+#"^offs^")" is rs4r & i0810 [ offs = i0810 << 1; ] {
+ ptr:4 = rs4r + offs;
+ export *[ram]:2 ptr;
+}
+
+# Right Sp-Relative Memory (Sp+#u5:2)
+MemSpRelU5Rw: "("^SP^"+#"^offs^")" is SP & i0408 [ offs = i0408 << 2; ] {
+ ptr:4 = SP + offs;
+ export *[ram]:4 ptr;
+}
+
+# Right Sp-Relative Memory (Sp+#u5:3)
+MemSpRelU5Rd: "("^SP^"+#"^offs^")" is SP & i0307 [ offs = i0307 << 3; ] {
+ ptr:4 = SP + offs;
+ export *[ram]:8 ptr;
+}
+
+# Right Sp-Relative Memory (Sp+#s6:3)
+MemSpRelS6Rd: "("^SP^"+#"^offs^")" is SP & s0308 [ offs = s0308 << 3; ] {
+ ptr:4 = SP + offs;
+ export *[ram]:8 ptr;
+}
+
+
+#
+# Class-15-Right Memory Access
+#
+
+# Class-15 (RIGHT) Store Rs-Relative Memory (Rs16+#u4:2)
+StMemRsRelC15Rw: "("^rs4r^")" is rs4r & i0003=0 {
+ ptr:4 = rs4r;
+ export *[ram]:4 ptr;
+}
+StMemRsRelC15Rw: "("^rs4r^"+#"^offs^")" is rs4r & i0003 [ offs = i0003 << 2; ] {
+ ptr:4 = rs4r + offs;
+ export *[ram]:4 ptr;
+}
+
+#
+# ^instruction phases
+#
+
+# Pcode Phases:
+# All constructors and subconstructors must support the following named pcode
+# phases which are assembled at the end of each packet:
+# <> - this phase performs all conditional executions to allow for new predicate use
+# <> - this phase performs all unconditional writes
+# <> - this phase performs all conditional writes
+# <> - this phase performs all conditional and unconditional flows
+
+# 'parse' bits (PP,EE) decoding (see V2 manual section 10.5 Loop packets for additional detail):
+#
+# '01' & '10' normal 'PP' instruction
+# '11' normal 'PP' instruction when last instruction in packet
+# '00' duplex/packed 'EE' instruction (v4, always last instruction in packet)
+#
+
+# reset packetBits if this is first instruction in packet
+ResetPacketBits: is packetOffset=0 [ packetBits=0; ] { }
+ResetPacketBits: is epsilon { }
+
+# Phase-0: Update packet offset for next instruction (does not alter packetOffset)
+:^instruction is phase=0 & (parse=1 | parse=2) & ResetPacketBits & instruction
+ [ tmpCtx2 = packetOffset;
+ packetOffset=packetOffset+1;
+ globalset(inst_next,packetOffset);
+ packetOffset = tmpCtx2;
+ phase = 1; ] { }
+:^instruction is phase=0 & (parse=3 | parse=0) & ResetPacketBits & instruction [
+# Rely on default context packetOffset=0 to be used for start of next packet
+# tmpCtx2 = packetOffset;
+# packetOffset=0; # next instr would start new execute packet (slot-0)
+# globalset(inst_next,packetOffset);
+# packetOffset = tmpCtx2;
+ phase=1; ] { }
+
+# Phase-1: End of H/W Loop packet detection (update parse1 or parse2 context)
+# if (start-of-packet) init shadow registers
+:^instruction is phase=1 & instruction [ phase = 2; ] { }
+:^instruction is phase=1 & packetOffset=1 & parse & instruction [ parse2 = parse; phase = 2; ] { }
+:^instruction is phase=1 & packetOffset=0 & parse & instruction [ parse1 = parse; phase = 2; ]
+{
+ # NOTE: The following execution packet intitialization appears at the start
+ # of every execute packet.
+
+ # Initilize Auto-AND predicates at start of execute packet.
+ # We rely on the hexagon compiler to enforce and predicate/auto-AND restrictions.
+ P0.new = 0xff;
+ P1.new = 0xff;
+ P2.new = 0xff;
+ P3.new = 0xff;
+
+ build instruction;
+}
+
+# Phase-2: Identify instruction parse phase
+# 'PP' instructions parsed in Phase-3
+# 'EE' duplex/packed-instructions parsed in Phase-4
+:^instruction is phase=2 & (parse_0=1 | parse_1=1) & instruction [ phase = 3; ] { }
+:^instruction is phase=2 & parse=0 & instruction [ phase = 4; ] { }
+
+# Phase-3: Actual instruction decode for packet-based (PP) instructions
+# - instructions may use packetOffset context to obtain adjusted inst_start
+# - instructions may alter other packedBits context sub-registers
+#
+# All packet type instructions (PP) must use the following pattern:
+# Note: flow/loop instructions must also manipulate certain context
+#
+# : EndPacket is & $(END_PACKET) {
+#
+# build EndPacket;
+# }
+#
+# End of Packet Handling ('PP' instructions only, resumes phase processing via EndPacket
+# subconstructors following constructor match)
+# - EndPacket subconstructor must be included with all non-packed instructions as
+# the last operand and 'build EndPacket' must appear at end of pcode.
+# - END_PACKET Can't specify [ ] since this may be specified by instruction
+#
+@define END_PACKET "phase=3 & EndPacket "
+
+# Phase-4: Parse Left subinstruction within duplex/packed 'EE' instruction
+# This phase relies on instruction constructors to match the first/left-side
+# subinstruction. All such instructions must employ the following pattern:
+#
+# : EndPackedLeft is & $(END_PACKED_LEFT) {
+#
+# build EndPackedLeft;
+# }
+#
+# Sample:
+#
+# :assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & op1920=0 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) {
+# Rdd3l = zext(Uimm2_2122);
+# build EndPackedLeft;
+# }
+#
+# - END_PACKET_LEFT Can't specify [ ] since this may be specified by instruction
+#
+@define END_PACKED_LEFT "phase=4 & EndPackedLeft "
+
+# Phase-5: Parse Right subinstruction within duplex/packed 'EE' instruction
+# This phase relies on instruction constructors to match the second/right-side
+# subinstruction. All such instructions must employ the following pattern:
+#
+# : EndPackedRight is & $(END_PACKED_RIGHT) {
+#
+# build EndPackedRight;
+# }
+#
+# Sample:
+#
+# :deallocframe EndPackedRight is op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) {
+# deallocframe();
+# build EndPackedRight;
+# }
+#
+# - END_PACKET_RIGHT Can't specify [ ] since this may be specified by instruction
+#
+@define END_PACKED_RIGHT "phase=5 & EndPackedRight "
+
+#
+PropogateLoopCfg: is useLoopCfg=1 [ globalset(inst_next,useLoopCfg); ] { }
+PropogateLoopCfg: is useLoopCfg=0 { }
+
+# Check for pipelined loop count and inject pcode if needed
+CheckLpcfg: is useLoopCfg=0 { }
+CheckLpcfg: is useLoopCfg=1 [ useLoopCfg=0; ] {
+ lpcfg:1 = $(LPCFG);
+ if (lpcfg == 0) goto ;
+ lpcfg = lpcfg - 1;
+ $(LPCFG) = lpcfg;
+ P3 = (lpcfg == 0); # set P3 once pipeline count (1-3) has lapsed
+ # NOTE: may be incorrect to clear P3 if not done yet
+
+}
+
+# EndPacket: End of HW Loop handling (uses parse1 and parse2)
+
+EndOfLoop: is PropogateLoopCfg { } # not end-of-loop - propogate useLoopCfg if active
+EndOfLoop: " :endloop0" is parse1=2 & CheckLpcfg { # Last in HW Loop 0
+ # :endloop0 - TODO: not sure how to display
+ build CheckLpcfg;
+ if (LC0 <= 1) goto inst_next;
+ LC0 = LC0 - 1;
+ goto [SA0];
+}
+EndOfLoop: " :endloop1" is parse1=1 & parse2=2 & PropogateLoopCfg { # Last in HW Loop 1 - propogate useLoopCfg if active
+ # :endloop1 - TODO: not sure how to display
+ if (LC1 <= 1) goto inst_next;
+ LC1 = LC1 - 1;
+ goto [SA1];
+}
+EndOfLoop: " :endloop0 :endloop1" is parse1=2 & parse2=2 & CheckLpcfg { # Last in HW Loop 0 & 1
+ # :endloop0:endloop1 - TODO: not sure how to display
+ build CheckLpcfg;
+ if (LC0 <= 1) goto inst_next;
+ LC0 = LC0 - 1;
+ goto [SA0];
+ if (LC1 <= 1) goto inst_next;
+ LC1 = LC1 - 1;
+ goto [SA1];
+}
+
+# CrossBuild:
+# - include <> <> and <> pcode for all instructions in packet
+
+CrossBuildAddr0: loc is epsilon [ loc = inst_start; ] { export *:4 loc; }
+CrossBuildAddr1: loc is epsilon [ loc = inst_start - 4; ] { export *:4 loc; }
+CrossBuildAddr2: loc is epsilon [ loc = inst_start - 8; ] { export *:4 loc; }
+CrossBuildAddr3: loc is epsilon [ loc = inst_start - 12; ] { export *:4 loc; }
+
+CrossBuild: is packetOffset=0 & CrossBuildAddr0 [ phase=8; ] {
+ crossbuild CrossBuildAddr0,EXEC_COND;
+ crossbuild CrossBuildAddr0,COMMIT;
+ crossbuild CrossBuildAddr0,COMMIT_COND;
+ ReturnAddr = inst_next;
+ crossbuild CrossBuildAddr0,FLOW;
+}
+CrossBuild: is packetOffset=1 & CrossBuildAddr0 & CrossBuildAddr1 [ phase=8; ] {
+ crossbuild CrossBuildAddr1,EXEC_COND;
+ crossbuild CrossBuildAddr0,EXEC_COND;
+ crossbuild CrossBuildAddr1,COMMIT;
+ crossbuild CrossBuildAddr0,COMMIT;
+ crossbuild CrossBuildAddr1,COMMIT_COND;
+ crossbuild CrossBuildAddr0,COMMIT_COND;
+ ReturnAddr = inst_next;
+ crossbuild CrossBuildAddr1,FLOW;
+ crossbuild CrossBuildAddr0,FLOW;
+}
+CrossBuild: is packetOffset=2 & CrossBuildAddr0 & CrossBuildAddr1 & CrossBuildAddr2 [ phase=8; ] {
+ crossbuild CrossBuildAddr2,EXEC_COND;
+ crossbuild CrossBuildAddr1,EXEC_COND;
+ crossbuild CrossBuildAddr0,EXEC_COND;
+ crossbuild CrossBuildAddr2,COMMIT;
+ crossbuild CrossBuildAddr1,COMMIT;
+ crossbuild CrossBuildAddr0,COMMIT;
+ crossbuild CrossBuildAddr2,COMMIT_COND;
+ crossbuild CrossBuildAddr1,COMMIT_COND;
+ crossbuild CrossBuildAddr0,COMMIT_COND;
+ ReturnAddr = inst_next;
+ crossbuild CrossBuildAddr2,FLOW;
+ crossbuild CrossBuildAddr1,FLOW;
+ crossbuild CrossBuildAddr0,FLOW;
+}
+CrossBuild: is packetOffset=3 & CrossBuildAddr0 & CrossBuildAddr1 & CrossBuildAddr2 & CrossBuildAddr3 [ phase=8; ] {
+ crossbuild CrossBuildAddr3,EXEC_COND;
+ crossbuild CrossBuildAddr2,EXEC_COND;
+ crossbuild CrossBuildAddr1,EXEC_COND;
+ crossbuild CrossBuildAddr0,EXEC_COND;
+ crossbuild CrossBuildAddr3,COMMIT;
+ crossbuild CrossBuildAddr2,COMMIT;
+ crossbuild CrossBuildAddr1,COMMIT;
+ crossbuild CrossBuildAddr0,COMMIT;
+ crossbuild CrossBuildAddr3,COMMIT_COND;
+ crossbuild CrossBuildAddr2,COMMIT_COND;
+ crossbuild CrossBuildAddr1,COMMIT_COND;
+ crossbuild CrossBuildAddr0,COMMIT_COND;
+ ReturnAddr = inst_next;
+ crossbuild CrossBuildAddr3,FLOW;
+ crossbuild CrossBuildAddr2,FLOW;
+ crossbuild CrossBuildAddr1,FLOW;
+ crossbuild CrossBuildAddr0,FLOW;
+}
+
+# End of Packet pcode
+# - if NOT end-of-packet propogate packet context bits and skip further checks
+# - if end-of-packet include CrossBuild and EndOfLoop pcode
+EndPacket: is (parse=1 | parse=2) & PropogateLoopCfg [ globalset(inst_next,packetBits); ] { } # this is not end-of-packet - propogate packetBits and useLoopCfg if needed
+EndPacket: EndOfLoop is (parse=0 | parse=3) & CrossBuild & EndOfLoop { # EndOfLoop will propogate useLoopCfg if needed
+ build CrossBuild;
+ build EndOfLoop;
+}
+
+# End of First/Left packed 'EE' instruction helper
+EndPackedLeft: "; "^instruction is instruction [ phase = 5; ] { build instruction; }
+
+# End of Second/Left packed 'EE' instruction helper
+EndPackedRight: is EndPacket [ phase = 6; ] { build EndPacket; } # resume EndPacket processing
+
+
+#
+# MACROS
+#
+
+#
+# frame layout
+#
+# +-----------+
+# | | <- SP.new
+# | local |
+# | |
+# | |
+# +-----------+
+# | saved FP | <- FP.new
+# +-----------+
+# | saved LR |
+# +-----------+
+# | | (initial SP)
+#
+
+# NOTE: allocframe and dealloc_frame macro should be invoked from the
+# <>, <> or <> pcode section only
+
+macro deallocframe(reg) {
+ ptr:4 = reg;
+ FP = *[ram]:4 ptr;
+ ptr = ptr + 4;
+ LR = (*[ram]:4 ptr) ^ FRAMEKEY;
+ SP = ptr + 4;
+}
+
+macro allocframe(reg,sze) {
+ ptr:4 = reg - 4;
+ *[ram]:4 ptr = (LR ^ FRAMEKEY);
+ ptr = ptr - 4;
+ *[ram]:4 ptr = FP;
+ FP = ptr;
+ reg = ptr - zext(sze);
+}
+
+#
+# INSTRUCTIONS
+#
+# Pattern convention:
+# '-' indicates don't-care bit (bit should not be constrained)
+# '+' indicates don't care bit (bit should be constrained as '0')
+#
+
+
+# (v2,8) abs -- "Rd32 = abs ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d
+
+:abs Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x04 & Rd5 & rs5 & $(END_PACKET) {
+ neg:1 = (rs5 s< 0);
+ Rd5 = (zext(neg) * -rs5) + (zext(!neg) * rs5);
+ build EndPacket;
+}
+
+# (v2,8) abs -- "Rd32 = abs ( Rs32 ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d
+
+define pcodeop absSat;
+
+:abs":sat" Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x05 & Rd5 & rs5 & $(END_PACKET) {
+
+ pos:1 = (rs5 s>= 0);
+ toobig:1 = (rs5 == 0x80000000); # Only one saturation case
+ Rd5 = (zext(pos) * rs5) + (zext(!pos) * ((zext(toobig) * 0x7fffffff) + (zext(!toobig) * -rs5)));
+ build EndPacket;
+ <>
+ $(OVF) = $(OVF) | toobig;
+}
+
+# (v2,8) abs -- "Rdd32 = abs ( Rss32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 0 d d d d d
+
+:abs Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET)
+{
+ neg:1 = (rss5 s< 0);
+ Rdd5 = (zext(neg) * -rss5) + (zext(!neg) * rss5);
+ build EndPacket;
+}
+
+# (v2,11) add -- "Rd32 = add ( Rs32 , #s16x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 1 1 i i i i i i i s s s s s P P i i i i i i i i i d d d d d
+
+:add Rd5,rs5,Simm32_2127_0513x EndPacket is iclass=0xb & Rd5 & rs5 & Simm32_2127_0513x & $(END_PACKET) {
+ Rd5 = rs5 + Simm32_2127_0513x;
+ build EndPacket;
+}
+
+# (v2,15) add -- "Rd32 = add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t + + + d d d d d
+
+:add Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x18 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) {
+ Rd5 = rs5 + rt5;
+ build EndPacket;
+}
+
+# (v4,15) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 0 1 1 0 0 1 0 s s s s s P P + t t t t t + + + d d d d d
+
+:add^":sat" Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x32 & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET)
+{
+ sat:1 = scarry(rs5, rt5);
+ addSat32(Rd5, rs5, rt5);
+ build EndPacket;
+ <>
+ $(OVF) = $(OVF) | sat;
+}
+
+# (v2,13) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat :deprecated"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 + + d d d d d
+
+:add^":sat:deprecated" Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2c & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET)
+{
+ sat:1 = scarry(rs5, rt5);
+ addSat32(Rd5, rs5, rt5);
+ build EndPacket;
+ <>
+ $(OVF) = $(OVF) | sat;
+}
+
+# (v4,13) add -- "Rd32 = add ( Rs32 , add ( Ru32 , #s6x ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 0 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u
+#
+# (v4,13) add -- "Rd32 = add ( Rs32 , sub ( #s6x , Ru32 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 0 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u
+
+AddSubOp23: "add("ru5,Simm32_2122_13_0507x")" is op23=0 & ru5 & Simm32_2122_13_0507x {
+ tmp:4 = ru5 + Simm32_2122_13_0507x;
+ export tmp;
+}
+AddSubOp23: "sub("Simm32_2122_13_0507x,ru5")" is op23=1 & ru5 & Simm32_2122_13_0507x {
+ tmp:4 = Simm32_2122_13_0507x - ru5;
+ export tmp;
+}
+
+:add Rd0812,rs5,AddSubOp23 EndPacket is iclass=13 & op2427=11 & Rd0812 & rs5 & AddSubOp23 & $(END_PACKET) {
+ Rd0812 = rs5 + AddSubOp23;
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rd32 = add ( Ru32 , mpyi ( #u6:2 , Rs32 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 1 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u
+#
+# (v4,13) add -- "Rd32 = add ( Ru32 , mpyi ( Rs32 , #u6x ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 1 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u
+
+MpyiOp23: "mpyi("Uimm32_2122_13_0507_shift2,rs5")" is op23=0 & rs5 & Uimm32_2122_13_0507_shift2 {
+ tmp:4 = rs5 * Uimm32_2122_13_0507_shift2;
+ export tmp;
+}
+MpyiOp23: "mpyi("Uimm32_2122_13_0507x,rs5")" is op23=1 & rs5 & Uimm32_2122_13_0507x {
+ tmp:4 = rs5 * Uimm32_2122_13_0507x;
+ export tmp;
+}
+
+:add Rd0812,ru5,MpyiOp23 EndPacket is iclass=13 & op2427=15 & Rd0812 & ru5 & MpyiOp23 & $(END_PACKET) {
+ Rd0812 = ru5 + MpyiOp23;
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rd32 = add ( #u6x , mpyi ( Rs32 , #U6 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 0 0 0 I i i s s s s s P P i d d d d d i i i I I I I I
+
+MpyiRs32U6: "mpyi("rs5,Uimm8_23_0004")" is rs5 & Uimm8_23_0004 {
+ tmp:4 = rs5 * zext(Uimm8_23_0004);
+ export tmp;
+}
+
+:add Rd0812,Uimm32_2122_13_0507x,MpyiRs32U6 EndPacket is iclass=13 & op2427=8 & Rd0812 & Uimm32_2122_13_0507x & MpyiRs32U6 & $(END_PACKET) {
+ Rd0812 = Uimm32_2122_13_0507x + MpyiRs32U6;
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rd32 = add ( #u6x , mpyi ( Rs32 , Rt32 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 1 1 0 i i s s s s s P P i t t t t t i i i d d d d d
+
+MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 {
+ tmp:4 = rs5 * rt5;
+ export tmp;
+}
+
+:add Rd5,Uimm32_2122_13_0507x,MpyiRs32Rt32 EndPacket is iclass=13 & op2327=0x0e & Rd5 & Uimm32_2122_13_0507x & MpyiRs32Rt32 & $(END_PACKET) {
+ Rd5 = Uimm32_2122_13_0507x + MpyiRs32Rt32;
+ build EndPacket;
+}
+
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 + d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 + d d d d d
+
+:add Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET)
+{
+ Rd5 = sext(rt5L + Rs5HL06);
+ build EndPacket;
+}
+
+# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d
+
+:add^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET)
+{
+ Rd5 = zext(Rs5HL05 + Rt5HL06) << 16;
+ build EndPacket;
+}
+
+# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :sat :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :sat :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat :<<16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d
+
+:add^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET)
+{
+ temp:2 = 0;
+ addSat16(temp, Rs5HL05, Rt5HL06);
+ Rd5 = zext(temp) << 16;
+ sat:1 = scarry(Rt5HL06, Rs5HL05);
+ build EndPacket;
+ <>
+ $(OVF) = $(OVF) | sat;
+}
+
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 + d d d d d
+#
+# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 + d d d d d
+
+:add^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=1 & op5=0 & Rs5HL06 & rt5L & Rd5 & $(END_PACKET)
+{
+ temp:2 = 0;
+ addSat16(temp, Rs5HL06, rt5L);
+ Rd5 = zext(temp);
+ sat:1 = scarry(Rs5HL06, rt5L);
+ build EndPacket;
+ <>
+ $(OVF) = $(OVF) | sat;
+}
+
+# (v4,8) add -- "Rd32 = add ( clb ( Rs32 ) , #s6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 0 1 s s s s s P P i i i i i i 0 0 0 d d d d d
+
+ClbRs: "clb("^rs5")" is rs5 { cnt:4 = countLeadingBits(rs5); export cnt; }
+
+:add Rd5,ClbRs,Simm8_0813 EndPacket is iclass=8 & op2127=0x61 & op0507=0 & Rd5 & ClbRs & Simm8_0813 & $(END_PACKET)
+{
+ Rd5 = ClbRs + sext(Simm8_0813);
+ build EndPacket;
+}
+
+# (v4,8) add -- "Rd32 = add ( clb ( Rss32 ) , #s6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P i i i i i i 0 1 + d d d d d
+
+ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; }
+
+:add Rd5,ClbRss,Simm8_0813 EndPacket is iclass=8 & op2127=0x43 & op0507=2 & Rd5 & ClbRss & Simm8_0813 & $(END_PACKET)
+{
+ Rd5 = ClbRss + sext(Simm8_0813);
+ build EndPacket;
+}
+
+# (v4,6) add -- "Rd32 = add ( pc , #u6x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P + i i i i i i + + d d d d d
+
+:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET)
+{
+ Rd5 = PacketPC;
+ build EndPacket;
+}
+
+:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET)
+{
+ Rd5 = PacketPC + Uimm32_0712x;
+ build EndPacket;
+}
+
+# (v2,13) add -- "Rdd32 = add ( Rss32 , Rtt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d
+
+:add Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET)
+{
+ Rdd5 = rss5 + rtt5;
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :hi"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d
+
+define pcodeop addRawHi;
+
+:add":raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET)
+{
+ Rdd5 = rtt5 + sext(rss5[32,32]);
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :lo"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d
+
+define pcodeop addRawLo;
+
+:add":raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x6 & Rdd5 & $(END_PACKET)
+{
+ Rdd5 = rtt5 + sext(rss5[0,32]);
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d
+
+define pcodeop addSat;
+
+:add":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x5 & Rdd5 & $(END_PACKET)
+{
+ Rdd5 = addSat(rss5, rtt5);
+ build EndPacket;
+}
+
+# (v4,12) add -- "Rdd32 = add ( Rss32 , Rtt32 , Px4 ) :carry"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 0 1 0 1 1 0 s s s s s P P + t t t t t + x x d d d d d
+
+:add":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=0xc & op2127=0x16 & rss5 & op13=0 & rtt5 & op7=0 & Rdd5 & pu0506 & pu0506_ & $(END_PACKET)
+unimpl
+
+# (v2,14) add -- "Rx32 += add ( Rs32 , #s8x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 0 0 1 0 0 + + s s s s s P P + i i i i i i i i x x x x x
+
+:add+= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x10 & rs5 & op13=0 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 + rs5 + Simm32_0512x;
+ build EndPacket;
+}
+
+# (v2,14) add -- "Rx32 += add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 1 x x x x x
+
+:add+= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x1 & rt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 + rs5 + rt5;
+ build EndPacket;
+}
+
+# (v2,14) add -- "Rx32 -= add ( Rs32 , #s8x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 0 0 1 0 1 + + s s s s s P P + i i i i i i i i x x x x x
+
+:add-= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x14 & op13=0 & rs5 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 - rs5 + Simm32_0512x;
+ build EndPacket;
+}
+
+# (v2,14) add -- "Rx32 -= add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 0 1 x x x x x
+
+:add-= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & rs5 & op13=0 & rt5 & op0507=0x1 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 - ( rs5 + rt5 );
+ build EndPacket;
+}
+
+# (v4,13) add -- "Rx32 = add ( #u8x , asl ( Rx32 , #U5 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 0 +
+#
+# (v4,13) add -- "Rx32 = add ( #u8x , lsr ( Rx32 , #U5 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 0 +
+
+:add Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=4 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET)
+{
+ Rx5 = Uimm32_2123_13_0507_03x + ShiftRx_D04_I0812;
+ build EndPacket;
+}
+
+# (v4,14) add -- "Rx32 = add ( Ru32 , mpyi ( Rx32 , Rs32 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 0 0 1 1 0 0 0 s s s s s P P + x x x x x + + + u u u u u
+
+MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 {
+ tmp:4 = rs5 * rt5;
+ export tmp;
+}
+
+:add Rd0812,ru5,MpyiRx32Rs32 EndPacket is iclass=14 & op2127=0x18 & op13=0 & op0507=0 & Rd0812 & MpyiRx32Rs32 & ru5 & $(END_PACKET)
+{
+ Rd0812 = ru5 + MpyiRx32Rs32;
+ build EndPacket;
+}
+
+# (v2,7) add -- "if ( Pu4 ) Rd32 = add ( Rs32 , #s8x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 1 0 0 0 u u s s s s s P P 0 i i i i i i i i d d d d d
+#
+# (v2,7) add -- "if ( ! Pu4 ) Rd32 = add ( Rs32 , #s8x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 1 0 0 1 u u s s s s s P P 0 i i i i i i i i d d d d d
+#
+# (v2,7) add -- "if ( Pu4 .new ) Rd32 = add ( Rs32 , #s8x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 1 0 0 0 u u s s s s s P P 1 i i i i i i i i d d d d d
+#
+# (v2,7) add -- "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , #s8x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 1 0 0 1 u u s s s s s P P 1 i i i i i i i i d d d d d
+
+:add^PuCond2122_N13_S23 rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & Simm32_0512x & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) {
+ build PuCond2122_N13_S23;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = rs5 + Simm32_0512x;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# if ([!]Pu4[.new]) Rd32 = Rs32 ( simplification of if ([!]Pu4[.new]) Rd32 = add(Rs32,#0)
+:assign^PuCond2122_N13_S23 rd5,rs5 EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & op0512=0 & immexted=0 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) {
+ build PuCond2122_N13_S23;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = rs5;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# (v2,15) add -- "if ( Pu4 ) Rd32 = add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 0 u u d d d d d
+#
+# (v2,15) add -- "if ( ! Pu4 ) Rd32 = add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 1 u u d d d d d
+#
+# (v2,15) add -- "if ( Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 0 u u d d d d d
+#
+# (v2,15) add -- "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 1 u u d d d d d
+
+:add^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) {
+ build PuCond0506_N13_S07;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = rs5 + rt5;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# (v2,12) addasl -- "Rd32 = addasl ( Rt32 , Rs32 , #u3 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 0 0 0 0 0 s s s s s P P 0 t t t t t i i i d d d d d
+
+:addasl Rd5,rt5,rs5,Uimm3_0507 EndPacket is iclass=12 & op2127=0x20 & op13=0 & Rd5 & rt5 & rs5 & Uimm3_0507 & $(END_PACKET)
+{
+ Rd5 = rt5 + (rs5 << Uimm3_0507);
+ build EndPacket;
+}
+
+# (v2,6) all8 -- "Pd4 = all8 ( Ps4 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 1 0 1 0 - - s s P P 0 - - - - - - - - - - - d d
+
+:all8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5d & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) {
+ Pd2 = Pd2 & ((pu1617 == 0xff) * 0xff);
+ build EndPacket;
+}
+
+# (v2,10) allocframe -- "allocframe ( #u11:3 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 P P 0 0 0 i i i i i i i i i i i
+
+:allocframe Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & op1620=0x1d & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) {
+ allocframe(SP, Uimm16_0010_shift3);
+ build EndPacket;
+}
+
+# (v2,10) allocframe -- "allocframe ( Rx32, #u11:3 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 1 0 0 0 0 0 1 0 0 x x x x x P P 0 0 0 i i i i i i i i i i i
+
+:allocframe rx5, Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & rx5 & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) {
+ allocframe(rx5, Uimm16_0010_shift3);
+ build EndPacket;
+}
+
+# (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , Pu4 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 0 - - - t t u u - - - - d d
+#
+# (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , ! Pu4 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 1 0 0 1 + + s s P P 0 - - - t t u u - - - - d d
+#
+# (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , Pu4 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 0 0 1 1 + + s s P P 0 - - - t t u u - - - - d d
+#
+# (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , ! Pu4 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 1 0 1 1 + + s s P P 0 - - - t t u u - - - - d d
+
+:and Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=0 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) {
+ Pd2 = Pd2 & (pu1617 & PredLogic_L21_S23_P0809_P0607);
+ build EndPacket;
+}
+
+# (v2,6) and -- "Pd4 = and ( Pt4 , Ps4 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 0 - - - t t - - - - - - d d
+
+:and Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) {
+ Pd2 = Pd2 & (pu1617 & pu0809);
+ build EndPacket;
+}
+
+# (v2,6) and -- "Pd4 = and ( Pt4 , ! Ps4 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 0 1 1 0 - - s s P P 0 - - - t t - - - - - - d d
+
+:and Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5b & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) {
+ Pd2 = Pd2 & (NotPs2 & pu0809);
+ build EndPacket;
+}
+
+# (v2,7) and -- "Rd32 = and ( Rs32 , #s10x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 1 1 0 0 0 i s s s s s P P i i i i i i i i i d d d d d
+
+:and Rd5,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x18 & Rd5 & rs5 & Simm32_21_0513x & $(END_PACKET) {
+ Rd5 = rs5 & Simm32_21_0513x;
+ build EndPacket;
+}
+
+# (v2,15) and -- "Rd32 = and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 0 0 0 1 0 0 0 s s s s s P P - t t t t t - - - d d d d d
+
+:and Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x08 & Rd5 & rs5 & rt5 & $(END_PACKET) {
+ Rd5 = rs5 & rt5;
+ build EndPacket;
+}
+
+# (v4,15) and -- "Rd32 = and ( Rt32 , ~ Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 0 0 0 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d
+
+:and Rd5,rt5,OnesCompRs5 EndPacket is iclass=15 & op2127=0x0c & Rd5 & OnesCompRs5 & rt5 & $(END_PACKET) {
+ Rd5 = rt5 & OnesCompRs5;
+ build EndPacket;
+}
+
+# (v2,13) and -- "Rdd32 = and ( Rss32 , Rtt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d
+
+:and Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) {
+ Rdd5 = rss5 & rtt5;
+ build EndPacket;
+}
+
+# (v4,13) and -- "Rdd32 = and ( Rtt32 , ~ Rss32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d
+
+:and Rdd5,rtt5,OnesCompRss5 EndPacket is iclass=13 & op2127=0x1f & op0507=1 & Rdd5 & OnesCompRss5 & rtt5 & $(END_PACKET) {
+ Rdd5 = rtt5 & OnesCompRss5;
+ build EndPacket;
+}
+
+# (v4,14) and -- "Rx32 &= and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 0 x x x x x
+
+:and&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 & rs5 & rt5;
+ build EndPacket;
+}
+
+# (v4,14) and -- "Rx32 &= and ( Rs32 , ~ Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 1 x x x x x
+
+:and&= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=1 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 & rs5 & OnesCompRt5;
+ build EndPacket;
+}
+
+# (v4,13) and -- "Rx32 = and ( #u8x , asl ( Rx32 , #U5 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 0 -
+#
+# (v4,13) and -- "Rx32 = and ( #u8x , lsr ( Rx32 , #U5 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 0 +
+
+:and Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=0 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET)
+{
+ Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812;
+ build EndPacket;
+}
+
+# (v4,14) and -- "Rx32 ^= and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 0 x x x x x
+
+:and"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 ^ (rs5 & rt5);
+ build EndPacket;
+}
+
+# (v4,14) and -- "Rx32 ^= and ( Rs32 , ~ Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 1 0 x x x x x
+
+:and"^=" Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=2 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 ^ (rs5 & OnesCompRt5);
+ build EndPacket;
+}
+
+# (v4,13) and -- "Rx32 |= and ( Rs32 , #s10x )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 1 0 1 0 0 0 i s s s s s P P i i i i i i i i i x x x x x
+
+:and|= Rd5,rs5,Simm32_21_0513x EndPacket is iclass=13 & op2227=0x28 & Rd5 & rd5 & Simm32_21_0513x & rs5 & $(END_PACKET) {
+ Rd5 = rd5 | (rs5 & Simm32_21_0513x);
+ build EndPacket;
+}
+
+# (v4,14) and -- "Rx32 |= and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 1 x x x x x
+
+:and|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 | (rs5 & rt5);
+ build EndPacket;
+}
+
+# (v4,14) and -- "Rx32 |= and ( Rs32 , ~ Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 0 x x x x x
+
+:and|= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=0 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET)
+{
+ Rd5 = rd5 | (rs5 & OnesCompRt5);
+ build EndPacket;
+}
+
+# (v2,15) and -- "if ( Pu4 ) Rd32 = and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 0 u u d d d d d
+#
+# (v2,15) and -- "if ( ! Pu4 ) Rd32 = and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 1 u u d d d d d
+#
+# (v2,15) and -- "if ( Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 0 u u d d d d d
+#
+# (v2,15) and -- "if ( ! Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d
+
+:and^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) {
+ build PuCond0506_N13_S07;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = rs5 & rt5;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# (v2,6) any8 -- "Pd4 = any8 ( Ps4 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 1 1 0 0 0 + + s s P P 0 + + + + + + + + + + + d d
+
+:any8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5c & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) {
+ Pd2 = Pd2 & ((pu1617 != 0) * 0xff);
+ build EndPacket;
+}
+
+# any8 -- "Pd4 = any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 0 0 + + + d d
+
+define pcodeop vcmpb.eq;
+
+VcmpbEq: "vcmpb.eq("^rss5,rtt5^")" is rss5 & rtt5 { tmp:1 = vcmpb.eq(rss5,rtt5); export tmp; }
+
+:any8 Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) {
+ Pd2 = Pd2 & ((VcmpbEq != 0) * 0xff);
+ build EndPacket;
+}
+
+# (v4,13) any8 -- "Pd4 = !any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 0 1 - - - d d
+
+:any8! Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=8 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) {
+ Pd2 = Pd2 & ~((VcmpbEq != 0) * 0xff);
+ build EndPacket;
+}
+
+
+# (v2,8) rol -- "Rd32 = rol ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 1 d d d d d
+
+:rol Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=3 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = (rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1);
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rd32 = asl ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d
+
+:asl Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rs5 << Uimm8_0812;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rd32 = asl ( Rs32 , #u5 ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d
+
+define pcodeop aslSat;
+
+:asl":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x62 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = aslSat(rs5, Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d
+
+:asl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ Rd5 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d
+
+:asl":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) {
+ Rd5 = aslSat(rs5, rt5);
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rdd32 = asl ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 0 d d d d d
+
+:asl Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rss5 << Uimm8_0813;
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rdd32 = rol ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 1 d d d d d
+
+:rol Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=3 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = (rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1);
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rdd32 = asl ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d
+
+:asl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rss5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ Rdd5 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5));
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rx32 &= asl ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 x x x x x
+
+:asl&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 & (rs5 << Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rx32 &= rol ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 1 x x x x x
+
+:rol&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 & ((rs5 << Uimm8_0812) | zext((rs5 s<0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rx32 &= asl ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5));
+ Rd5 = rd5 & result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rx32 += asl ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 0 x x x x x
+
+:asl+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 + (rs5 << Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rx32 += rol ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 1 x x x x x
+
+:rol+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 + ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rx32 += asl ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5));
+ Rd5 = rd5 + result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rx32 -= asl ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x
+
+:asl-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 - (rs5 << Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rx32 -= rol ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x
+
+:rol-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 - ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rx32 -= asl ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5));
+ Rd5 = rd5 - result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rx32 ^= asl ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x
+
+:asl"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 ^ (rs5 << Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rx32 ^= rol ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x
+
+:rol"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 ^ ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rx32 |= asl ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 0 x x x x x
+
+:asl|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 | (rs5 << Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rx32 |= rol ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 1 x x x x x
+
+:rol|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 | ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rx32 |= asl ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5));
+ Rd5 = rd5 | result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rxx32 &= asl ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 0 x x x x x
+
+:asl&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 & (rss5 << Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rxx32 &= rol ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 1 x x x x x
+
+:rol&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 & ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rxx32 &= asl ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5));
+ Rdd5 = rdd5 & result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rxx32 += asl ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 0 x x x x x
+
+:asl+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 + (rss5 << Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rxx32 += rol ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 1 x x x x x
+
+:rol+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 + ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rxx32 += asl ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5));
+ Rdd5 = rdd5 + result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rxx32 -= asl ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 0 x x x x x
+
+:asl-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 - (rss5 << Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rxx32 -= rol ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 1 x x x x x
+
+:rol-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 - ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rxx32 -= asl ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5));
+ Rdd5 = rdd5 - result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rxx32 ^= asl ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 0 x x x x x
+
+:asl"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 ^ (rss5 << Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rxx32 ^= rol ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 1 x x x x x
+
+:rol"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 ^ ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v4,12) asl -- "Rxx32 ^= asl ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5));
+ Rdd5 = rdd5 ^ result;
+ build EndPacket;
+}
+
+# (v2,8) asl -- "Rxx32 |= asl ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 0 x x x x x
+
+:asl|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 | (rss5 << Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,8) rol -- "Rxx32 |= rol ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 1 x x x x x
+
+:rol|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 | ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1));
+ build EndPacket;
+}
+
+# (v2,12) asl -- "Rxx32 |= asl ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 + x x x x x
+
+:asl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ right:1 = rt5 s< 0;
+ result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5));
+ Rdd5 = rdd5 | result;
+ build EndPacket;
+}
+
+# (v2,7) aslh -- "Rd32 = aslh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 0 + + + + + + + + d d d d d
+
+:aslh Rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) {
+ Rd5 = rs5 << 16;
+ build EndPacket;
+}
+
+# (v4,7) aslh -- "if ( Pu4 ) Rd32 = aslh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 0 u u - - - d d d d d
+#
+# (v4,7) aslh -- "if ( ! Pu4 ) Rd32 = aslh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 0 u u - - - d d d d d
+#
+# (v4,7) aslh -- "if ( Pu4 .new ) Rd32 = aslh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 1 u u - - - d d d d d
+#
+# (v4,7) aslh -- "if ( ! Pu4 .new ) Rd32 = aslh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 1 u u - - - d d d d d
+
+:aslh^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=1 & rd5 & rd5_ & SetNRegRd5 & rs5 & PuCond0809_N10_S11 & $(END_PACKET) {
+ build PuCond0809_N10_S11;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = rs5 << 16;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# (v2,8) asr -- "Rd32 = asr ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d
+
+:asr Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rs5 s>> Uimm8_0812;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rd32 = asr ( Rs32 , #u5 ) :rnd"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d
+
+:asr":rnd" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = roundArithmetic(rs5 s>> Uimm8_0812, 1:1);
+ build EndPacket;
+}
+
+# (v5,8) asr -- "Rdd32 = asr ( Rss32 , #u6 ) :rnd"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 0 0 1 1 0 s s s s s P P i i i i i i 1 1 1 d d d d d
+
+:asr":rnd" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x06 & op0507=7 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = roundArithmetic(rss5 s>> Uimm8_0813, 1:1);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d
+
+:asr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ Rd5 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5));
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 ) :sat"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d
+
+define pcodeop asrSat;
+
+:asr":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) {
+ Rd5 = asrSat(rs5, rt5);
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rdd32 = asr ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 0 d d d d d
+
+:asr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=0 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rss5 s>> Uimm8_0813;
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rdd32 = asr ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d
+
+:asr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rss5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ Rdd5 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5));
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rx32 &= asr ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 x x x x x
+
+:asr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 & (rs5 s>> Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rx32 &= asr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5));
+ Rd5 = rd5 & result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rx32 += asr ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 0 x x x x x
+
+:asr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 + (rs5 s>> Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rx32 += asr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5));
+ Rd5 = rd5 + result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rx32 -= asr ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 0 x x x x x
+
+:asr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 - (rs5 s>> Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rx32 -= asr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5));
+ Rd5 = rd5 - result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rx32 |= asr ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 0 x x x x x
+
+:asr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) {
+ Rd5 = rd5 | (rs5 s>> Uimm8_0812);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rx32 |= asr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5));
+ Rd5 = rd5 | result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rxx32 &= asr ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 0 x x x x x
+
+:asr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 & (rss5 s>> Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rxx32 &= asr ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5));
+ Rdd5 = rdd5 & result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rxx32 += asr ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 0 x x x x x
+
+:asr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 + (rss5 s>> Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rxx32 += asr ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5));
+ Rdd5 = rdd5 + result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rxx32 -= asr ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 0 x x x x x
+
+:asr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 - (rss5 s>> Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rxx32 -= asr ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5));
+ Rdd5 = rdd5 - result;
+ build EndPacket;
+}
+
+# (v4,12) asr -- "Rxx32 ^= asr ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5));
+ Rdd5 = rdd5 ^ result;
+ build EndPacket;
+}
+
+# (v2,8) asr -- "Rxx32 |= asr ( Rss32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 0 x x x x x
+
+:asr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) {
+ Rdd5 = rdd5 | (rss5 s>> Uimm8_0813);
+ build EndPacket;
+}
+
+# (v2,12) asr -- "Rxx32 |= asr ( Rss32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 + x x x x x
+
+:asr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) {
+ left:1 = rt5 s< 0;
+ result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5));
+ Rdd5 = rdd5 | result;
+ build EndPacket;
+}
+
+# (v2,7) asrh -- "Rd32 = asrh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 0 + + + + + + + + d d d d d
+
+:asrh Rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) {
+ Rd5 = rs5 s>> 16;
+ build EndPacket;
+}
+
+# (v4,7) asrh -- "if ( Pu4 ) Rd32 = asrh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 0 u u - - - d d d d d
+#
+# (v4,7) asrh -- "if ( ! Pu4 ) Rd32 = asrh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 0 u u - - - d d d d d
+#
+# (v4,7) asrh -- "if ( Pu4 .new ) Rd32 = asrh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 1 u u - - - d d d d d
+#
+# (v4,7) asrh -- "if ( ! Pu4 .new ) Rd32 = asrh ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 1 u u - - - d d d d d
+
+:asrh^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=1 & rd5 & rd5_ & SetNRegRd5 & rs5 & PuCond0809_N10_S11 & $(END_PACKET) {
+ build PuCond0809_N10_S11;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = rs5 s>> 16;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# (v2,6) assign -- "Cd32 = Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Cd5,rs5 EndPacket is iclass=6 & op2127=0x11 & op0513=0 & Cd5 & rs5 & $(END_PACKET) {
+ # NOTE: Assuming that PC will not be directly assigned
+ Cd5 = rs5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Cdd32 = Rss32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 0 0 1 1 0 0 1 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Cdd5,rss5 EndPacket is iclass=6 & op2127=0x19 & op0513=0 & Cdd5 & rss5 & $(END_PACKET) {
+ # NOTE: Assuming that PC will not be directly assigned
+ Cdd5 = rss5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Gd32 = Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 0 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Gd5,rs5 EndPacket is iclass=6 & op2127=0x10 & op0513=0 & Gd5 & rs5 & $(END_PACKET) {
+ Gd5 = rs5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Gdd32 = Rss32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 0 0 1 1 0 0 0 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Gdd5,rss5 EndPacket is iclass=6 & op2127=0x18 & op0513=0 & Gdd5 & rss5 & $(END_PACKET) {
+ Gdd5 = rss5;
+ build EndPacket;
+}
+
+# (v2,8) assign -- "Pd4 = Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 1 0 1 0 1 + s s s s s P P + + + + + + + + + + + + d d
+
+:assign Pd2,rs5 EndPacket is iclass=8 & op2127=0x2a & rs5 & op0213=0 & Pd2 & $(END_PACKET) {
+ Pd2 = Pd2 & rs5:1;
+ build EndPacket;
+}
+
+# (v2,7) assign -- "Rd32 = #s16x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 1 0 0 0 i i - i i i i i P P i i i i i i i i i d d d d d
+
+:assign Rd5,Simm32_2223_1620_0513x EndPacket is iclass=7 & op2427=8 & op21=0 & Rd5 & Simm32_2223_1620_0513x & $(END_PACKET) {
+ Rd5 = Simm32_2223_1620_0513x;
+ build EndPacket;
+}
+
+# (v2,6) assign -- "Rd32 = Cs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Rd5,Cs5 EndPacket is iclass=6 & op2127=0x50 & op0513=0 & Rd5 & Cs5 & $(END_PACKET) {
+ Rd5 = Cs5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Rd32 = Gs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Rd5,gs5 EndPacket is iclass=6 & op2127=0x51 & op0513=0 & Rd5 & gs5 & $(END_PACKET) {
+ Rd5 = gs5;
+ build EndPacket;
+}
+
+# (v2,8) assign -- "Rd32 = Ps4"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 0 0 1 + 1 + + + + s s P P + + + + + + + + + d d d d d
+
+:assign Rd5,pu1617 EndPacket is iclass=8 & op1827=0x250 & pu1617 & op0513=0 & Rd5 & $(END_PACKET) {
+ Rd5 = zext( pu1617 );
+ build EndPacket;
+}
+
+# (v2,7) assign -- "Rd32 = Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 0 0 1 1 s s s s s P P 0 - - - - - - - - d d d d d
+
+:assign Rd5,rs5 EndPacket is iclass=7 & op2127=0x03 & op0513=0 & Rd5 & rs5 & $(END_PACKET) {
+ Rd5 = rs5;
+ build EndPacket;
+}
+
+# (v2,6) assign -- "Rd32 = Ss64"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 1 1 0 1 + s s s s s s P P + + + + + + + + + d d d d d
+
+:assign Rd5,ss6 EndPacket is iclass=6 & op2227=0x3a & op0513=0 & Rd5 & ss6 & $(END_PACKET) {
+ Rd5 = ss6;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Rdd32 = Css32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Rdd5,css5 EndPacket is iclass=6 & op2127=0x40 & op0513=0 & Rdd5 & css5 & $(END_PACKET) {
+ Rdd5 = css5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Rdd32 = Gss32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d
+
+:assign Rdd5,gss5 EndPacket is iclass=6 & op2127=0x41 & op0513=0 & Rdd5 & gss5 & $(END_PACKET) {
+ Rdd5 = gss5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Rdd32 = Sss64"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 1 1 1 + + s s s s s s P P + + + + + + + + + d d d d d
+
+:assign Rdd5,sss6 EndPacket is iclass=6 & op2227=0x3c & op0513=0 & Rdd5 & sss6 & $(END_PACKET) {
+ Rdd5 = sss6;
+ build EndPacket;
+}
+
+# (v2,7) assign -- "Rx32.h = #u16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 1 0 i i 1 x x x x x P P i i i i i i i i i i i i i i
+
+:assign Rx5H,Uimm16_2223_0013 EndPacket is iclass=7 & op2427=2 & op21=1 & Rx5H & Uimm16_2223_0013 & $(END_PACKET) {
+ Rx5H = Uimm16_2223_0013;
+ build EndPacket;
+}
+
+# (v2,7) assign -- "Rx32.l = #u16"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 0 0 0 1 i i 1 x x x x x P P i i i i i i i i i i i i i i
+
+:assign Rx5L,Uimm16_2223_0013 EndPacket is iclass=7 & op2427=1 & op21=1 & Rx5L & Uimm16_2223_0013 & $(END_PACKET) {
+ Rx5L = Uimm16_2223_0013;
+ build EndPacket;
+}
+
+# (v2,6) assign -- "Sd64 = Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 0 1 1 1 0 0 + s s s s s P P + + + + + + + + d d d d d d
+
+:assign Sd6,rs5 EndPacket is iclass=6 & op2127=0x38 & op0613=0 & Sd6 & rs5 & $(END_PACKET) {
+ Sd6 = rs5;
+ build EndPacket;
+}
+
+# (v4,6) assign -- "Sdd64 = Rss32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 1 0 1 0 + + s s s s s P P + + + + + + + + d d d d d d
+
+:assign Sdd6,rss5 EndPacket is iclass=6 & op2127=0x68 & op0613=0 & Sdd6 & rss5 & $(END_PACKET) {
+ Sdd6 = rss5;
+ build EndPacket;
+}
+
+# (v2,7) assign -- "if ( Pu4 ) Rd32 = #s12x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 0 i i i i i i i i d d d d d
+#
+# (v2,7) assign -- "if ( ! Pu4 ) Rd32 = #s12x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 0 i i i i i i i i d d d d d
+#
+# (v2,7) assign -- "if ( Pu4 .new ) Rd32 = #s12x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 1 i i i i i i i i d d d d d
+#
+# (v2,7) assign -- "if ( ! Pu4 .new ) Rd32 = #s12x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 1 i i i i i i i i d d d d d
+
+:assign^PuCond2122_N13_S23 rd5,Simm32_1619_0512x EndPacket is iclass=7 & op2427=0xe & op20=0 & PuCond2122_N13_S23 & rd5 & rd5_ & SetNRegRd5 & Simm32_1619_0512x & $(END_PACKET) {
+ build PuCond2122_N13_S23;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5_ = Simm32_1619_0512x;
+
+ <>
+ if (ConditionReg == 0) goto ;
+ rd5 = rd5_;
+
+}
+
+# (v2,10) barrier -- "barrier"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 1 0 1 0 0 0 0 0 0 + + + + + P P + + + + + + + + + + + + + +
+
+define pcodeop barrier;
+
+:barrier EndPacket is iclass=10 & op2127=0x40 & op1620=0 & op0013=0 & $(END_PACKET) {
+ barrier();
+ build EndPacket;
+}
+
+# (v2,8) bitsclr -- "Pd4 = bitsclr ( Rs32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 1 0 1 1 0 0 s s s s s P P i i i i i i + + + + + + d d
+
+:bitsclr Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2c & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) {
+ isClr:1 = (rs5 & zext(Uimm8_0813)) == 0;
+ Pd2 = Pd2 & (isClr * 0xff);
+ build EndPacket;
+}
+
+# (v4,8) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , #u6 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 1 0 1 1 0 1 s s s s s P P i i i i i i + + + + + + d d
+
+:bitsclr! Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2d & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) {
+ notClr:1 = (rs5 & zext(Uimm8_0813)) != 0;
+ Pd2 = Pd2 & (notClr * 0xff);
+ build EndPacket;
+}
+
+# (v2,12) bitsclr -- "Pd4 = bitsclr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t + + + + + + d d
+
+:bitsclr Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3c & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) {
+ isClr:1 = (rs5 & rt5) == 0;
+ Pd2 = Pd2 & (isClr * 0xff);
+ build EndPacket;
+}
+
+# (v4,12) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t + + + + + + d d
+
+:bitsclr! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3d & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) {
+ notClr:1 = (rs5 & rt5) != 0;
+ Pd2 = Pd2 & (notClr * 0xff);
+ build EndPacket;
+}
+
+# (v4,8) bitsplit -- "Rdd32 = bitsplit ( Rs32 , #u5 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 0 + d d d d d
+
+:bitsplit Rdd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rdd5h_ & rd5_ & rs5 & Uimm8_0812 & $(END_PACKET) {
+ build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis
+ rdd5h_ = rs5 >> Uimm8_0812;
+ mask:4 = ~(-1 << Uimm8_0812);
+ rd5_ = rs5 & mask;
+ build EndPacket;
+}
+
+# (v4,13) bitsplit -- "Rdd32 = bitsplit ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 1 0 0 + + 1 s s s s s P P + t t t t t + + + d d d d d
+
+:bitsplit Rdd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x21 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) {
+ build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis
+ cnt:4 = rt5 & 0x1f;
+ rdd5h_ = rs5 >> cnt;
+ mask:4 = ~(-1 << cnt);
+ rd5_ = rs5 & mask;
+ build EndPacket;
+}
+
+# (v2,12) bitsset -- "Pd4 = bitsset ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t + + + + + + d d
+
+:bitsset Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3a & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) {
+ isSet:1 = (rs5 & rt5) == rt5;
+ Pd2 = Pd2 & (isSet * 0xff);
+ build EndPacket;
+}
+
+# (v4,12) bitsset -- "Pd4 = ! bitsset ( Rs32 , Rt32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t + + + + + + d d
+
+:bitsset! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3b & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) {
+ notSet:1 = (rs5 & rt5) != rt5;
+ Pd2 = Pd2 & (notSet * 0xff);
+ build EndPacket;
+}
+
+# (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :hi"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 1 + + + d d
+
+:boundscheck":raw:hi" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x28 & rss5 & rtt5 & Pd2 & $(END_PACKET) {
+ upper:4 = rtt5(4);
+ lower:4 = rtt5:4;
+ src:4 = rss5(4);
+ # TODO: unclear if comparison should be signed or unsigned
+ bool:1 = (src >= lower) && (src < upper);
+ Pd2 = Pd2 & (bool * 0xff);
+ build EndPacket;
+}
+
+# (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :lo"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 0 + + + d d
+
+:boundscheck":raw:lo" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) {
+ upper:4 = rtt5(4);
+ lower:4 = rtt5:4;
+ src:4 = rss5:4;
+ # TODO: unclear if comparison should be signed or unsigned
+ bool:1 = (src >= lower) && (src < upper);
+ Pd2 = Pd2 & (bool * 0xff);
+ build EndPacket;
+}
+
+# (v2,8) brev -- "Rd32 = brev ( Rs32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d
+
+:brev Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) {
+ Rd5 = bitReverse(rs5);
+ build EndPacket;
+}
+
+# (v4,8) brev -- "Rdd32 = brev ( Rss32 )"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 1 0 d d d d d
+
+:brev Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) {
+ Rdd5 = bitReverse(rss5);
+ build EndPacket;
+}
+
+# (v2,6) brkpt -- "brkpt"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 0 0 - - - - -
+
+define pcodeop brkpt;
+
+:brkpt EndPacket is iclass=6 & op2127=0x61 & op0507=0 & $(END_PACKET) {
+ brkpt();
+ build EndPacket;
+}
+
+# (v2,5) call -- "call #r22:2x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 1 0 1 i i i i i i i i i P P i i i i i i i i i i i i i 0
+
+:call RelDest22x EndPacket is iclass=5 & op2527=5 & op0=0 & RelDest22x & $(END_PACKET) {
+ build EndPacket;
+ <>
+ LR = ReturnAddr;
+ call RelDest22x;
+}
+
+# (v2,5) call -- "if ( Pu4 ) call #r15:2x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 1 1 0 1 i i 0 i i i i i P P i 0 0 + u u i i i i i i i +
+#
+# (v2,5) call -- "if ( ! Pu4 ) call #r15:2x"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 1 1 0 1 i i 1 i i i i i P P i 0 0 + u u i i i i i i i +
+
+:call^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xd & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) {
+ build FlowCondUU;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ LR = ReturnAddr;
+ call RelDest15x;
+
+}
+
+# (v2,5) callr -- "callr Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 0 0 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + +
+
+:callr rs5 EndPacket is iclass=5 & op2127=0x05 & op0013=0 & rs5 & $(END_PACKET) {
+ dest:4 = rs5;
+ build EndPacket;
+ <>
+ LR = ReturnAddr;
+ call [dest];
+}
+
+# callrh -- "callrh Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 0 0 0 0 1 1 0 s s s s s P P + + + + + + + + + + + + + +
+
+:callrh rs5 EndPacket is iclass=5 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) {
+ dest:4 = rs5;
+ build EndPacket;
+ <>
+ LR = ReturnAddr;
+ call [dest];
+}
+
+# (v2,5) callr -- "if ( Pu4 ) callr Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 0 0 0 1 0 0 0 s s s s s P P + + + + u u + + + + + + + +
+#
+# (v2,5) callr -- "if ( ! Pu4 ) callr Rs32"
+# _________________________________________________________________________________________________
+# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+# 0 1 0 1 0 0 0 1 0 0 1 s s s s s P P + + + + u u + + + + + + + +
+
+:callr^FlowCondUU rs5 EndPacket is iclass=5 & op2227=0x04 & op1013=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) {
+ dest:4 = rs5;
+ build FlowCondUU;
+ build EndPacket;
+ <>
+ if (ConditionReg == 0) goto ;
+ LR = ReturnAddr;
+ call [dest];
+