From 8215297c8377399b976b399c2ae5f6d2f2de5079 Mon Sep 17 00:00:00 2001 From: Shawn Hoffman Date: Thu, 7 May 2026 15:53:35 -0700 Subject: [PATCH] hexagon: add V68 memw_aq decode-only stub Acquire-load form L2_loadw_aq from V68; same iclass/op2127 family as the existing memw_phys constructor but distinguished by op0513=0x40. --- Ghidra/Processors/Hexagon/data/languages/hexagon.sinc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc index 8b05f67b7e..8beaf84cb2 100755 --- a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc @@ -11642,6 +11642,14 @@ define pcodeop memw_phys; build EndPacket; } +# (v68,9) memw_aq -- "Rd32 = memw_aq ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 1 0 0 0 0 0 0 d d d d d + +:memw_aq Rd5,rs5 EndPacket is iclass=9 & op2127=0x10 & op0513=0x40 & Rd5 & rs5 & $(END_PACKET) +unimpl + # (v2,13) min -- "Rd32 = min ( Rt32 , Rs32 )" # _________________________________________________________________________________________________ # |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|