diff --git a/Ghidra/Processors/68000/certification.manifest b/Ghidra/Processors/68000/certification.manifest
index 2107f5c99c..c8eb60ade0 100644
--- a/Ghidra/Processors/68000/certification.manifest
+++ b/Ghidra/Processors/68000/certification.manifest
@@ -6,8 +6,11 @@ data/languages/68000.ldefs||GHIDRA||||END|
 data/languages/68000.opinion||GHIDRA||||END|
 data/languages/68000.pspec||GHIDRA||||END|
 data/languages/68000.sinc||GHIDRA||||END|
+data/languages/68000_register.cspec||GHIDRA||||END|
 data/languages/68020.slaspec||GHIDRA||reviewed||END|
 data/languages/68030.slaspec||GHIDRA||||END|
 data/languages/68040.slaspec||GHIDRA||||END|
 data/languages/coldfire.slaspec||GHIDRA||||END|
 data/manuals/68000.idx||GHIDRA||||END|
+data/patterns/68000_patterns.xml||GHIDRA||||END|
+data/patterns/patternconstraints.xml||GHIDRA||||END|
diff --git a/Ghidra/Processors/68000/data/languages/68000.cspec b/Ghidra/Processors/68000/data/languages/68000.cspec
index fe7c760943..f5395e61a4 100644
--- a/Ghidra/Processors/68000/data/languages/68000.cspec
+++ b/Ghidra/Processors/68000/data/languages/68000.cspec
@@ -22,25 +22,16 @@
 		<entry size="8" alignment="4" />
 	</size_alignment_map>
   </data_organization>
+  
   <global>
     <range space="ram"/>
   </global>
+  
   <stackpointer register="SP" space="ram"/>
+  
   <default_proto>
-    <prototype name="__stdcall" extrapop="4" stackshift="4" strategy="register">
+    <prototype name="__stdcall" extrapop="4" stackshift="4">
       <input>
-        <pentry minsize="1" maxsize="4" metatype="ptr">
-          <register name="A0"/>
-        </pentry>
-        <pentry minsize="1" maxsize="4" metatype="ptr">
-          <register name="A1"/>
-        </pentry>
-        <pentry minsize="1" maxsize="4">
-          <register name="D0"/>
-        </pentry>
-        <pentry minsize="1" maxsize="4">
-          <register name="D1"/>
-        </pentry>
         <pentry minsize="1" maxsize="500" align="4">
           <addr offset="4" space="stack"/>
         </pentry>
@@ -64,6 +55,13 @@
         <register name="A6"/>
         <register name="SP"/>
       </unaffected>
+      <killedbycall>
+        <register name="D0"/>
+        <register name="D1"/>
+        <register name="A0"/>
+        <register name="A1"/>
+      </killedbycall>
     </prototype>
   </default_proto>
+  
 </compiler_spec>
diff --git a/Ghidra/Processors/68000/data/languages/68000.ldefs b/Ghidra/Processors/68000/data/languages/68000.ldefs
index e065db0c51..c93a4c0df0 100644
--- a/Ghidra/Processors/68000/data/languages/68000.ldefs
+++ b/Ghidra/Processors/68000/data/languages/68000.ldefs
@@ -61,6 +61,7 @@
             id="68000:BE:32:Coldfire">
     <description>Motorola 32-bit Coldfire</description>
     <compiler name="default" spec="68000.cspec" id="default"/>
+    <compiler name="register" spec="68000_register.cspec" id="register"/>
     <external_name tool="IDA-PRO" name="colfire"/>
     <external_name tool="DWARF.register.mapping.file" name="68000.dwarf"/>
   </language>
diff --git a/Ghidra/Processors/68000/data/languages/68000_register.cspec b/Ghidra/Processors/68000/data/languages/68000_register.cspec
new file mode 100644
index 0000000000..b058885afd
--- /dev/null
+++ b/Ghidra/Processors/68000/data/languages/68000_register.cspec
@@ -0,0 +1,118 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<compiler_spec>
+  <data_organization>
+	<absolute_max_alignment value="0" />
+	<machine_alignment value="8" />
+	<default_alignment value="1" />
+	<default_pointer_alignment value="4" />
+	<pointer_size value="4" />
+	<wchar_size value="4" />
+	<short_size value="2" />
+	<integer_size value="4" />
+	<long_size value="4" />
+	<long_long_size value="8" />
+	<float_size value="4" />
+	<double_size value="8" />
+	<long_double_size value="10" /> <!-- aligned-length=12 -->
+	<size_alignment_map>
+		<entry size="1" alignment="1" />
+		<entry size="2" alignment="2" />
+		<entry size="4" alignment="4" />
+		<entry size="8" alignment="4" />
+	</size_alignment_map>
+  </data_organization>
+  
+  <global>
+    <range space="ram"/>
+  </global>
+  
+  <stackpointer register="SP" space="ram"/>
+  
+  <default_proto>
+    <prototype name="register" extrapop="4" stackshift="4" strategy="register">
+      <input>
+        <pentry minsize="1" maxsize="4" metatype="ptr">
+          <register name="A0"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" metatype="ptr">
+          <register name="A1"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" metatype="float">
+          <register name="FP0"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4" metatype="float">
+          <register name="FP1"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4">
+          <register name="D0"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4">
+          <register name="D1"/>
+        </pentry>
+        <pentry minsize="1" maxsize="500" align="4">
+          <addr offset="4" space="stack"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="4" metatype="ptr">
+          <register name="A0"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4">
+          <register name="D0"/>
+        </pentry>
+      </output>
+      <unaffected>
+        <register name="D2"/>
+        <register name="D3"/>
+        <register name="D4"/>
+        <register name="D5"/>
+        <register name="D6"/>
+        <register name="D7"/>
+        <register name="A2"/>
+        <register name="A3"/>
+        <register name="A4"/>
+        <register name="A5"/>
+        <register name="A6"/>
+        <register name="SP"/>
+      </unaffected>
+    </prototype>
+  </default_proto>
+  
+  <prototype name="standard" extrapop="4" stackshift="4">
+      <input>
+        <pentry minsize="1" maxsize="500" align="4">
+          <addr offset="4" space="stack"/>
+        </pentry>
+      </input>
+      <output>
+        <pentry minsize="1" maxsize="4" metatype="ptr">
+          <register name="A0"/>
+        </pentry>
+        <pentry minsize="1" maxsize="4">
+          <register name="D0"/>
+        </pentry>
+      </output>
+      <unaffected>
+        <register name="D2"/>
+        <register name="D3"/>
+        <register name="D4"/>
+        <register name="D5"/>
+        <register name="D6"/>
+        <register name="D7"/>
+        <register name="A2"/>
+        <register name="A3"/>
+        <register name="A4"/>
+        <register name="A5"/>
+        <register name="A6"/>
+        <register name="SP"/>
+      </unaffected>
+      <killedbycall>
+        <register name="D0"/>
+        <register name="D1"/>
+        <register name="A0"/>
+        <register name="A1"/>
+      </killedbycall>
+  </prototype>
+
+</compiler_spec>
diff --git a/Ghidra/Processors/68000/data/patterns/68000_patterns.xml b/Ghidra/Processors/68000/data/patterns/68000_patterns.xml
new file mode 100644
index 0000000000..6a271ccd39
--- /dev/null
+++ b/Ghidra/Processors/68000/data/patterns/68000_patterns.xml
@@ -0,0 +1,41 @@
+<patternlist>
+
+  <patternpairs totalbits="32" postbits="16">
+    <!--  Higher confidence patterns, after a return and more defined bits -->
+    <prepatterns>
+      <data>0x4e 0x75</data>            <!-- ret -->
+      <data>0x4e 0x75 0x4e 0x71 </data> <!-- ret; padding -->
+      <data>0x4e 0x75 0x00 0x00 </data> <!-- ret; padding -->
+      <data>0x4e 0x5e 0x4e 0x75</data>            <!-- unlk A6; ret -->
+      <data>0x4e 0x5e 0x4e 0x75 0x4e 0x71 </data> <!-- unlk A6; ret; padding -->
+      <data>0x4e 0x5e 0x4e 0x75 0x00 0x00 </data> <!-- unlk A6; ret; padding -->
+    </prepatterns>
+    <postpatterns>
+      <data>01001111 11101111 1111.... .......0 </data>   <!-- lea (-imm,SP),SP) -->
+      <data>0x4e 0x56 0x00 0x00 </data>                   <!-- link.w A6, 0 -->
+      <data>0x4e 0x56 1111.... .......0 </data>           <!-- link.w A6, -imm -->
+      <data>0101...1 10001111   01001000 11010111 ........ ........ </data> <!-- subq.l +imm, SP; movem.l {}, (SP) -->
+      <data>0010...0 0.101111 0000.... .......0 </data>  <!-- mov.l (+imm, SP), reg -->
+      <data>0x2f 0x02 </data>  <!-- move.l D2,-SP -->
+      <data>0x2f 0x03 </data>  <!-- move.l D3,-SP -->
+      <data>0x2f 0x0a </data>  <!-- move.l A2,-SP -->
+      <data>0x2f 0x0b </data>  <!-- move.l A3,-SP -->
+      <funcstart/>
+    </postpatterns>
+  </patternpairs>
+  
+  <patternpairs totalbits="32" postbits="16">
+    <!--  pattern after a bra.w, use more solid patterns for function starts -->
+    <prepatterns>
+      <data>0x60 0x00 ........ ........ </data>            <!-- bra.w  -->
+    </prepatterns>
+    <postpatterns>
+      <data>01001111 11101111 1111.... .......0 </data>   <!-- lea (-imm,SP),SP) -->
+      <data>0x4e 0x56 0x00 0x00 </data>                   <!-- link.w A6, 0 -->
+      <data>0x4e 0x56 1111.... .......0 </data>           <!-- link.w A6, -imm -->
+      <funcstart/>
+    </postpatterns>
+  </patternpairs>
+  
+ 
+</patternlist>
\ No newline at end of file
diff --git a/Ghidra/Processors/68000/data/patterns/patternconstraints.xml b/Ghidra/Processors/68000/data/patterns/patternconstraints.xml
new file mode 100644
index 0000000000..085dc1e213
--- /dev/null
+++ b/Ghidra/Processors/68000/data/patterns/patternconstraints.xml
@@ -0,0 +1,5 @@
+<patternconstraints>
+  <language id="68000:BE:*:*">
+    <patternfile>68000_patterns.xml</patternfile>
+  </language>
+</patternconstraints>