diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
index 28881ba825..d242f70dcd 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
@@ -13,6 +13,7 @@
RISC-V 64 little base
+
RISC-V 64 little base compressed
+
RISC-V 64 little general purpose
+
RISC-V 64 little general purpose compressed
+
RISC-V 32 little default
+
RISC-V 32 little base
+
RISC-V 32 little base compressed
+
RISC-V 32 little base compressed
+
RISC-V 32 little general purpose
+
RISC-V 32 little general purpose compressed
+
RISC-V 32 little default
+
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
index 0a25874e8e..92a0c90fae 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.table.sinc
@@ -31,7 +31,7 @@ rs3: r2731 is r2731 { export r2731; }
rs3: zero is zero & op2731=0 { export 0:$(XLEN); }
rd: r0711 is r0711 { export r0711; }
-rd: zero is r0711 & zero & op0711=0 { export 0:$(XLEN); }
+rd: zero is r0711 & zero & op0711=0 { local tempZero:$(XLEN) = 0; export tempZero; }
rdDst: r0711 is r0711 { export r0711; }