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emteere_GT-2902 minor syntax changes to sleigh file. No effect to

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languages.
This commit is contained in:
emteere
2019-06-10 17:44:49 -04:00
parent d0ee2aa26b
commit 6ea9e0a93f
9 changed files with 270 additions and 269 deletions
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Ghidra/Processors/6805/data/languages/6805.slaspec
+46 -46
View File
@@ -55,16 +55,16 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1 :ADC OP1 is (op=0xA9 | op=0xB9 | op=0xC9 | op=0xD9 | op=0xE9 | op=0xF9) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
# compute half carry # compute half carry
halfop1 = op1 & 0xF; local halfop1 = op1 & 0xF;
halfA = A & 0xF; local halfA = A & 0xF;
halfresult = halfop1 + halfA + C; local halfresult = halfop1 + halfA + C;
H = (halfresult >> 4) & 1; H = (halfresult >> 4) & 1;
result = A + op1; local result = A + op1;
tmpC = carry(A, op1); local tmpC = carry(A, op1);
A = result + C; A = result + C;
C = carry(result, C); C = carry(result, C);
@@ -74,12 +74,12 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1 :ADD OP1 is (op=0xAB | op=0xBB | op=0xCB | op=0xDB | op=0xEB | op=0xFB) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
# compute half carry # compute half carry
halfop1 = op1 & 0xF; local halfop1 = op1 & 0xF;
halfA = A & 0xF; local halfA = A & 0xF;
halfresult = halfop1 + halfA; local halfresult = halfop1 + halfA;
H = (halfresult >> 4) & 1; H = (halfresult >> 4) & 1;
C = carry(A, op1); C = carry(A, op1);
@@ -111,7 +111,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1 :ASL OP1 is (op=0x38 | op=0x68 | op=0x78) ... & OP1
{ {
tmp = OP1; local tmp = OP1;
C = tmp >> 7; C = tmp >> 7;
tmp = tmp << 1; tmp = tmp << 1;
OP1 = tmp; OP1 = tmp;
@@ -134,7 +134,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1 :ASR OP1 is (op=0x37 | op=0x67 | op=0x77) ... & OP1
{ {
tmp = OP1; local tmp = OP1;
C = tmp & 1; C = tmp & 1;
tmp = tmp s>> 1; tmp = tmp s>> 1;
OP1 = tmp; OP1 = tmp;
@@ -148,7 +148,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:BCLR n,DIRECT is op4_7=1 & bit_0=1 & n; DIRECT { :BCLR n,DIRECT is op4_7=1 & bit_0=1 & n; DIRECT {
mask = ~(1 << n); local mask = ~(1 << n);
DIRECT = DIRECT & mask; DIRECT = DIRECT & mask;
} }
:BCS REL is op=0x25;REL :BCS REL is op=0x25;REL
@@ -169,7 +169,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:BHI REL is op=0x22;REL :BHI REL is op=0x22;REL
{ {
tmp = C + Z; local tmp = C + Z;
if (tmp == 0) goto REL; if (tmp == 0) goto REL;
} }
@@ -187,7 +187,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1 :BIT OP1 is (op=0xA5 | op=0xB5 | op=0xC5 | op=0xD5 | op=0xE5 | op=0xF5) ... & OP1
{ {
result = A & OP1; local result = A & OP1;
Z = (result == 0); Z = (result == 0);
N = (result s< 0); N = (result s< 0);
} }
@@ -195,7 +195,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:BLS REL is op=0x23;REL :BLS REL is op=0x23;REL
{ {
tmp = C + Z; local tmp = C + Z;
if (tmp) goto REL; if (tmp) goto REL;
} }
@@ -230,18 +230,18 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:BRCLR n,DIRECT,REL is op4_7=0 & bit_0=1 & n; DIRECT; REL :BRCLR n,DIRECT,REL is op4_7=0 & bit_0=1 & n; DIRECT; REL
{ {
mask = (1 << n); local mask = (1 << n);
result = DIRECT & mask; local result = DIRECT & mask;
if (result == 0) goto REL; if (result == 0) goto REL;
} }
:BRSET n,DIRECT,REL is op4_7=0 & bit_0=0 & n; DIRECT; REL :BRSET n,DIRECT,REL is op4_7=0 & bit_0=0 & n; DIRECT; REL
{ {
mask = (1 << n); local mask = (1 << n);
result = DIRECT & mask; local result = DIRECT & mask;
if (result != 0) goto REL; if (result != 0) goto REL;
} }
:BSET n,DIRECT is op4_7=1 & bit_0=0 & n; DIRECT { :BSET n,DIRECT is op4_7=1 & bit_0=0 & n; DIRECT {
mask = ~(1 << n); local mask = ~(1 << n);
DIRECT = DIRECT & mask; DIRECT = DIRECT & mask;
} }
:BSR REL is op=0xAD; REL :BSR REL is op=0xAD; REL
@@ -281,8 +281,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1 :CMP OP1 is (op=0xA1 | op=0xB1 | op=0xC1 | op=0xD1 | op=0xE1 | op=0xF1) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
tmp = A - op1; local tmp = A - op1;
Z = tmp == 0; Z = tmp == 0;
N = tmp s< 0; N = tmp s< 0;
C = (A < op1); C = (A < op1);
@@ -304,7 +304,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1 :COM OP1 is (op=0x33 | op=0x63 | op=0x73) ... & OP1
{ {
tmp = ~OP1; local tmp = ~OP1;
OP1 = tmp; OP1 = tmp;
Z = (tmp == 0); Z = (tmp == 0);
N = (tmp s< 0); N = (tmp s< 0);
@@ -312,8 +312,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1 :CPX OP1 is (op=0xA3 | op=0xB3 | op=0xC3 | op=0xD3 | op=0xE3 | op=0xF3) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
tmp = X - op1; local tmp = X - op1;
Z = tmp == 0; Z = tmp == 0;
N = tmp s< 0; N = tmp s< 0;
C = (A < op1); C = (A < op1);
@@ -332,14 +332,14 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1 :DEC OP1 is (op=0x3A | op=0x6A | op=0x7A) ... & OP1
{ {
tmp = OP1 - 1; local tmp = OP1 - 1;
OP1 = tmp; OP1 = tmp;
Z = (tmp == 0); Z = (tmp == 0);
N = (tmp s< 0); N = (tmp s< 0);
} }
:EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1 :EOR OP1 is (op=0xA8 | op=0xB8 | op=0xC8 | op=0xD8 | op=0xE8 | op=0xF8) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
A = A ^ op1; A = A ^ op1;
Z = A == 0; Z = A == 0;
N = A s< 0; N = A s< 0;
@@ -358,7 +358,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1 :INC OP1 is (op=0x3C | op=0x6C | op=0x7C) ... & OP1
{ {
tmp = OP1 + 1; local tmp = OP1 + 1;
OP1 = tmp; OP1 = tmp;
Z = (tmp == 0); Z = (tmp == 0);
N = (tmp s< 0); N = (tmp s< 0);
@@ -421,7 +421,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1 :LSR OP1 is (op=0x34 | op=0x64 | op=0x74) ... & OP1
{ {
tmp = OP1; local tmp = OP1;
C = tmp & 1; C = tmp & 1;
tmp = tmp >> 1; tmp = tmp >> 1;
OP1 = tmp; OP1 = tmp;
@@ -433,7 +433,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
{ {
op1:2 = zext(A); op1:2 = zext(A);
op2:2 = zext(X); op2:2 = zext(X);
result = op1 * op2; local result = op1 * op2;
A = result:1; A = result:1;
result = result >> 8; result = result >> 8;
X = result:1; X = result:1;
@@ -455,7 +455,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1 :NEG OP1 is (op=0x30 | op=0x60 | op=0x70) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
C = op1 != 0; C = op1 != 0;
OP1 = -op1; OP1 = -op1;
Z = (op1 == 0); Z = (op1 == 0);
@@ -475,7 +475,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:ROLA is op=0x49 :ROLA is op=0x49
{ {
tmp = C ; local tmp = C ;
C = A >> 7; C = A >> 7;
A = A << 1; A = A << 1;
A = A | tmp; A = A | tmp;
@@ -484,7 +484,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:ROLX is op=0x59 :ROLX is op=0x59
{ {
tmp = C; local tmp = C;
C = X >> 7; C = X >> 7;
X = X << 1; X = X << 1;
X = X | tmp; X = X | tmp;
@@ -493,10 +493,10 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1 :ROL OP1 is (op=0x39 | op=0x69 | op=0x79) ... & OP1
{ {
tmpC = C; local tmpC = C;
op1 = OP1; local op1 = OP1;
C = op1 >> 7; C = op1 >> 7;
result = op1 << 1; local result = op1 << 1;
result = result | tmpC; result = result | tmpC;
OP1 = result; OP1 = result;
Z = (result == 0); Z = (result == 0);
@@ -504,7 +504,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:RORA is op=0x46 :RORA is op=0x46
{ {
tmpC = C << 7; local tmpC = C << 7;
C = A & 1; C = A & 1;
A = A s>> 1; A = A s>> 1;
A = A | tmpC; A = A | tmpC;
@@ -513,7 +513,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:RORX is op=0x56 :RORX is op=0x56
{ {
tmpC = C << 7; local tmpC = C << 7;
C = X & 1; C = X & 1;
X = X s>> 1; X = X s>> 1;
X = X | tmpC; X = X | tmpC;
@@ -522,8 +522,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1 :ROR OP1 is (op=0x36 | op=0x66 | op=0x76) ... & OP1
{ {
tmpC = C << 7; local tmpC = C << 7;
tmp = OP1; local tmp = OP1;
C = tmp & 1; C = tmp & 1;
tmp = tmp s>> 1; tmp = tmp s>> 1;
tmp = tmp | tmpC; tmp = tmp | tmpC;
@@ -540,7 +540,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:RTI is op = 0x80 :RTI is op = 0x80
{ {
SP = SP+1; SP = SP+1;
ccr = *:1 SP; local ccr = *:1 SP;
H = ccr[4,1]; H = ccr[4,1];
I = ccr[3,1]; I = ccr[3,1];
N = ccr[2,1]; N = ccr[2,1];
@@ -570,8 +570,8 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1 :SBC OP1 is (op=0xA2 | op=0xB2 | op=0xC2 | op=0xD2 | op=0xE2 | op=0xF2) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
tmp = A - op1 - C; local tmp = A - op1 - C;
Z = tmp == 0; Z = tmp == 0;
N = tmp s< 0; N = tmp s< 0;
C = ((A <= op1) * C) | (A < op1); C = ((A <= op1) * C) | (A < op1);
@@ -609,7 +609,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
:SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1 :SUB OP1 is (op=0xA0 | op=0xB0 | op=0xC0 | op=0xD0 | op=0xE0 | op=0xF0) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
C = (A < op1); C = (A < op1);
A = A - op1; A = A - op1;
Z = A == 0; Z = A == 0;
@@ -648,7 +648,7 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
} }
:TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1 :TST OP1 is (op=0x3D | op=0x6D | op=0x7D) ... & OP1
{ {
op1 = OP1; local op1 = OP1;
Z = (op1 == 0); Z = (op1 == 0);
N = (op1 s< 0); N = (op1 s< 0);
} }
Ghidra/Processors/8051/data/languages/mx51.sinc
+1 -1
View File
@@ -190,7 +190,7 @@ EBitByteAddr: byteaddr is bitbank=0 & lowbyte & sfrbit [ byteaddr = lowbyte + 0
:movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg { :movx "@"eptrReg,Areg is opfull=0xa5; opfull=0xf0 & Areg & eptrReg {
*:1 EPTR = ACC; *:1 EPTR = ACC;
} }
:movc Areg,"@"APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr { :movc Areg,APlusEptr is opfull=0xa5; opfull=0x93 & Areg & APlusEptr {
ACC = *:1 APlusEptr; ACC = *:1 APlusEptr;
} }
:inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR { :inc EPTR is opfull=0xa5; opfull=0xa3 & EPTR {
Ghidra/Processors/8085/data/languages/8085.slaspec
+1 -1
View File
@@ -90,7 +90,7 @@ macro setAddFlags(op1,op2) {
} }
macro setSubtractCarryFlags(op1,op2) { macro setSubtractCarryFlags(op1,op2) {
notC = ~CY_flag; local notC = ~CY_flag;
CY_flag = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC)))); CY_flag = ((op1 < sext(notC)) || (op2 < (op1 - sext(notC))));
} }
Ghidra/Processors/AARCH64/data/languages/AARCH64neon.sinc
+20 -20
View File
@@ -432,10 +432,10 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=0 & b_2121=1 & Rm_VPR128.16
simd_address_at(tmp3, Rd_VPR128.16B, 15, 1, 16); simd_address_at(tmp3, Rd_VPR128.16B, 15, 1, 16);
* [register]:1 tmp3 = (* [register]:1 tmp1) + (* [register]:1 tmp2); * [register]:1 tmp3 = (* [register]:1 tmp1) + (* [register]:1 tmp2);
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_INT_ADD(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); local tmpd:16 = SIMD_INT_ADD(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
Zd = zext(tmpd); # assigning to Rd_VPR128.16B Zd = zext(tmpd); # assigning to Rd_VPR128.16B
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR128.16B = NEON_add(Rn_VPR128.16B, Rm_VPR128.16B, 1:1); Rd_VPR128.16B = NEON_add(Rn_VPR128.16B, Rm_VPR128.16B, 1:1);
@endif @endif
} }
@@ -526,10 +526,10 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR128.4S
simd_address_at(tmp3, Rd_VPR128.4S, 3, 4, 16); simd_address_at(tmp3, Rd_VPR128.4S, 3, 4, 16);
* [register]:4 tmp3 = (* [register]:4 tmp1) + (* [register]:4 tmp2); * [register]:4 tmp3 = (* [register]:4 tmp1) + (* [register]:4 tmp2);
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_INT_ADD(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); local tmpd:16 = SIMD_INT_ADD(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
Zd = zext(tmpd); # assigning to Rd_VPR128.4S Zd = zext(tmpd); # assigning to Rd_VPR128.4S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR128.4S = NEON_add(Rn_VPR128.4S, Rm_VPR128.4S, 4:1); Rd_VPR128.4S = NEON_add(Rn_VPR128.4S, Rm_VPR128.4S, 4:1);
@endif @endif
} }
@@ -682,10 +682,10 @@ is b_3131=0 & q=0 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_2121=1 & Rm_VPR64.2S
simd_address_at(tmp3, Rd_VPR64.2S, 1, 4, 8); simd_address_at(tmp3, Rd_VPR64.2S, 1, 4, 8);
* [register]:4 tmp3 = (* [register]:4 tmp1) + (* [register]:4 tmp2); * [register]:4 tmp3 = (* [register]:4 tmp1) + (* [register]:4 tmp2);
zext_zd(Zd); # zero upper 24 bytes of Zd zext_zd(Zd); # zero upper 24 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmpd:8 = SIMD_INT_ADD(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); local tmpd:8 = SIMD_INT_ADD(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
Zd = zext(tmpd); # assigning to Rd_VPR64.2S Zd = zext(tmpd); # assigning to Rd_VPR64.2S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR64.2S = NEON_add(Rn_VPR64.2S, Rm_VPR64.2S, 4:1); Rd_VPR64.2S = NEON_add(Rn_VPR64.2S, Rm_VPR64.2S, 4:1);
@endif @endif
} }
@@ -1658,7 +1658,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x
local tmp10:4 = tmp7 + tmp9; local tmp10:4 = tmp7 + tmp9;
Rd_FPR32 = tmp5 + tmp10; Rd_FPR32 = tmp5 + tmp10;
zext_zs(Zd); # zero upper 28 bytes of Zd zext_zs(Zd); # zero upper 28 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmp1:4 = SIMD_PIECE(Rn_VPR128.4S, 0:1); local tmp1:4 = SIMD_PIECE(Rn_VPR128.4S, 0:1);
local tmp2:4 = SIMD_PIECE(Rn_VPR128.4S, 1:1); local tmp2:4 = SIMD_PIECE(Rn_VPR128.4S, 1:1);
local tmp3:4 = tmp1 + tmp2; local tmp3:4 = tmp1 + tmp2;
@@ -1667,7 +1667,7 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xe & advSIMD3.size=2 & b_1721=0x18 & b_1216=0x
local tmp6:4 = tmp4 + tmp5; local tmp6:4 = tmp4 + tmp5;
local tmpd:4 = tmp3 + tmp6; local tmpd:4 = tmp3 + tmp6;
Zd = zext(tmpd); # assigning to Rd_FPR32 Zd = zext(tmpd); # assigning to Rd_FPR32
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_FPR32 = NEON_addv(Rn_VPR128.4S, 4:1); Rd_FPR32 = NEON_addv(Rn_VPR128.4S, 4:1);
@endif @endif
} }
@@ -4291,11 +4291,11 @@ is b_3131=0 & Q=1 & b_29=0 & b_2428=0xe & b_2123=0 & b_16=1 & b_1515=0 & imm4=0x
simd_address_at(tmp3, Rd_VPR128.16B, 15, 1, 16); simd_address_at(tmp3, Rd_VPR128.16B, 15, 1, 16);
* [register]:1 tmp3 = tmp2; * [register]:1 tmp3 = tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmp1:1 = SIMD_PIECE(Rn_GPR32, 0:1); local tmp1:1 = SIMD_PIECE(Rn_GPR32, 0:1);
local tmpd:16 = SIMD_COPY(Rd_VPR128.16B, tmp1); local tmpd:16 = SIMD_COPY(Rd_VPR128.16B, tmp1);
Zd = zext(tmpd); # assigning to Rd_VPR128.16B Zd = zext(tmpd); # assigning to Rd_VPR128.16B
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR128.16B = NEON_dup(Rd_VPR128.16B, Rn_GPR32, 1:1); Rd_VPR128.16B = NEON_dup(Rd_VPR128.16B, Rn_GPR32, 1:1);
@endif @endif
} }
@@ -19165,10 +19165,10 @@ is b_3131=0 & q=1 & b_29=0 & b_2428=0xe & b_2123=0 & Rd_VPR128.S.imm_neon_uimm2
simd_address_at(tmp1, Rd_VPR128, imm_neon_uimm2:4, 4, 16); simd_address_at(tmp1, Rd_VPR128, imm_neon_uimm2:4, 4, 16);
* [register]:4 tmp1 = Rn_GPR32; * [register]:4 tmp1 = Rn_GPR32;
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_COPY(Rd_VPR128, Rn_GPR32, imm_neon_uimm2:1); local tmpd:16 = SIMD_COPY(Rd_VPR128, Rn_GPR32, imm_neon_uimm2:1);
Zd = zext(tmpd); # assigning to Rd_VPR128 Zd = zext(tmpd); # assigning to Rd_VPR128
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR128 = NEON_mov(Rd_VPR128, Rn_GPR32, imm_neon_uimm2:1, 2:1); Rd_VPR128 = NEON_mov(Rd_VPR128, Rn_GPR32, imm_neon_uimm2:1, 2:1);
@endif @endif
} }
@@ -19232,11 +19232,11 @@ is b_3131=0 & Q=0 & b_29=0 & b_2428=0xe & b_2123=0 & Rn_VPR128.S.imm_neon_uimm2
local tmp2:4 = * [register]:4 tmp1; local tmp2:4 = * [register]:4 tmp1;
Rd_GPR32 = tmp2; Rd_GPR32 = tmp2;
zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64 zext_rs(Rd_GPR64); # zero upper 28 bytes of Rd_GPR64
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmp1:4 = SIMD_PIECE(Rn_VPR128, imm_neon_uimm2:1); local tmp1:4 = SIMD_PIECE(Rn_VPR128, imm_neon_uimm2:1);
local tmpd:4 = tmp1; local tmpd:4 = tmp1;
Rd_GPR64 = zext(tmpd); # assigning to Rd_GPR32 Rd_GPR64 = zext(tmpd); # assigning to Rd_GPR32
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
local tmp1:4 = SIMD_PIECE(Rn_VPR128, imm_neon_uimm2:1); local tmp1:4 = SIMD_PIECE(Rn_VPR128, imm_neon_uimm2:1);
Rd_GPR32 = NEON_mov(tmp1, 4:1); Rd_GPR32 = NEON_mov(tmp1, 4:1);
@endif @endif
@@ -19366,11 +19366,11 @@ is b_31=0 & b_30=1 & b_29=1 & b_1928=0b0111100000 & b_1215=0b1110 & b_1011=0b01
simd_address_at(tmp2, Rd_VPR128.2D, 1, 8, 16); simd_address_at(tmp2, Rd_VPR128.2D, 1, 8, 16);
* [register]:8 tmp2 = tmp1; * [register]:8 tmp2 = tmp1;
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmp1:8 = Imm_neon_uimm8Shift; local tmp1:8 = Imm_neon_uimm8Shift;
local tmpd:16 = SIMD_COPY(Rd_VPR128.2D, tmp1); local tmpd:16 = SIMD_COPY(Rd_VPR128.2D, tmp1);
Zd = zext(tmpd); # assigning to Rd_VPR128.2D Zd = zext(tmpd); # assigning to Rd_VPR128.2D
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR128.2D = NEON_movi(Imm_neon_uimm8Shift, 8:1); Rd_VPR128.2D = NEON_movi(Imm_neon_uimm8Shift, 8:1);
@endif @endif
} }
@@ -19468,10 +19468,10 @@ is b_31=0 & b_30=1 & b_29=0 & b_1928=0b0111100000 & b_15=0 & b_12=0 & b_1011=0b0
simd_address_at(tmp1, Rd_VPR128.4S, 3, 4, 16); simd_address_at(tmp1, Rd_VPR128.4S, 3, 4, 16);
* [register]:4 tmp1 = Imm_neon_uimm8Shift:4; * [register]:4 tmp1 = Imm_neon_uimm8Shift:4;
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmpd:16 = SIMD_COPY(Rd_VPR128.4S, Imm_neon_uimm8Shift:4); local tmpd:16 = SIMD_COPY(Rd_VPR128.4S, Imm_neon_uimm8Shift:4);
Zd = zext(tmpd); # assigning to Rd_VPR128.4S Zd = zext(tmpd); # assigning to Rd_VPR128.4S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
Rd_VPR128.4S = NEON_movi(Imm_neon_uimm8Shift, 4:1); Rd_VPR128.4S = NEON_movi(Imm_neon_uimm8Shift, 4:1);
@endif @endif
} }
@@ -19674,11 +19674,11 @@ is b_3131=0 & q=1 & u=0 & b_2428=0xf & advSIMD3.size=2 & Re_VPR128.S.vIndex & Re
simd_address_at(tmp4, Rd_VPR128.4S, 3, 4, 16); simd_address_at(tmp4, Rd_VPR128.4S, 3, 4, 16);
* [register]:4 tmp4 = (* [register]:4 tmp3) * tmp2; * [register]:4 tmp4 = (* [register]:4 tmp3) * tmp2;
zext_zq(Zd); # zero upper 16 bytes of Zd zext_zq(Zd); # zero upper 16 bytes of Zd
@elif defined(SEMANTIC_pcode) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pcode)
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
local tmpd:16 = SIMD_INT_MULT(Rn_VPR128.4S, tmp1); local tmpd:16 = SIMD_INT_MULT(Rn_VPR128.4S, tmp1);
Zd = zext(tmpd); # assigning to Rd_VPR128.4S Zd = zext(tmpd); # assigning to Rd_VPR128.4S
@elif defined(SEMANTIC_pseudo) && !defined(SEMANTIC_force) @elif defined(SEMANTIC_pseudo)
local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1); local tmp1:4 = SIMD_PIECE(Re_VPR128.S, vIndex:1);
Rd_VPR128.4S = NEON_mul(Rn_VPR128.4S, tmp1, 4:1); Rd_VPR128.4S = NEON_mul(Rn_VPR128.4S, tmp1, 4:1);
@endif @endif
Ghidra/Processors/Dalvik/data/languages/Dalvik.slaspec
+5 -5
View File
@@ -500,7 +500,7 @@ define pcodeop switchAssist;
# A: destination register (8 bits) # A: destination register (8 bits)
# B: arbitrary 32-bit constant # B: arbitrary 32-bit constant
:const registerA8,constant32 is inst0=0x14 ; registerA8 ; constant32 :"const" registerA8,constant32 is inst0=0x14 ; registerA8 ; constant32
{ {
registerA8 = constant32; registerA8 = constant32;
} }
@@ -808,11 +808,11 @@ define pcodeop switchAssist;
distance:4 = B_BITS_0_31_S * 2; distance:4 = B_BITS_0_31_S * 2;
ident:4 = *[ram] ( inst_start + distance ); ident:4 = *[ram] ( inst_start + distance );
size2:2 = *[ram] ( inst_start + distance + 2 ); size2:2 = *[ram] ( inst_start + distance + 2 );
size:4 = zext( size2 ); sze:4 = zext( size2 );
first_key:4 = *[ram] ( inst_start + distance + 2 + 2 ); first_key:4 = *[ram] ( inst_start + distance + 2 + 2 );
if ( registerA8 < first_key ) goto inst_next; if ( registerA8 < first_key ) goto inst_next;
if ( registerA8 >= ( first_key + size ) ) goto inst_next; if ( registerA8 >= ( first_key + sze ) ) goto inst_next;
targets:4 = ( inst_start + distance + 2 + 2 + 4 ); targets:4 = ( inst_start + distance + 2 + 2 + 4 );
delta:4 = ( registerA8 ) - ( first_key ); # which index into target delta:4 = ( registerA8 ) - ( first_key ); # which index into target
@@ -836,11 +836,11 @@ define pcodeop switchAssist;
distance:4 = B_BITS_0_31_S * 2; distance:4 = B_BITS_0_31_S * 2;
temp:4 = inst_start; temp:4 = inst_start;
size2:2 = *[ram] ( temp + 2 + distance); size2:2 = *[ram] ( temp + 2 + distance);
size:4 = zext( size2 ); sze:4 = zext( size2 );
defaultPos:4 = inst_next; defaultPos:4 = inst_next;
address:4 = switchAssist( registerA8, size, defaultPos, temp, distance ); address:4 = switchAssist( registerA8, sze, defaultPos, temp, distance );
goto [ address ]; goto [ address ];
} }
Ghidra/Processors/PA-RISC/data/languages/pa-risc.sinc
+115 -114
View File
File diff suppressed because it is too large Load Diff
Ghidra/Processors/PA-RISC/data/languages/pa-riscInstructions.sinc
+80 -80
View File
File diff suppressed because it is too large Load Diff
Ghidra/Processors/Z80/certification.manifest
+1 -1
View File
@@ -2,7 +2,7 @@
Module.manifest||GHIDRA||||END| Module.manifest||GHIDRA||||END|
build.gradle||GHIDRA||||END| build.gradle||GHIDRA||||END|
data/languages/z180.pspec||GHIDRA||||END| data/languages/z180.pspec||GHIDRA||||END|
data/languages/z180.slaspec||GHIDRA||reviewed||END| data/languages/z180.slaspec||GHIDRA||||END|
data/languages/z182.pspec||GHIDRA||||END| data/languages/z182.pspec||GHIDRA||||END|
data/languages/z80.cspec||GHIDRA||||END| data/languages/z80.cspec||GHIDRA||||END|
data/languages/z80.ldefs||GHIDRA||||END| data/languages/z80.ldefs||GHIDRA||||END|
Ghidra/Processors/Z80/data/languages/z180.slaspec
+1 -1
View File
@@ -1,3 +1,3 @@
@define Z180 @define Z180 ""
@include "z80.slaspec" @include "z80.slaspec"