diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
index 67e3a9fad3..7e60e72591 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
@@ -1069,7 +1069,7 @@ attach variables [ D A B C S TH RA RB RS RT regp]
 attach variables [ BFA BI_CR CRFD CRFS CR_A CR_B CR_D CR_X ]
 	[cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7] ;
 
-attach variables [ BI_CR_VLE ]
+attach variables [ BI_CR_VLE BF_VLE ]
 	[cr0 cr1 cr2 cr3 ] ;
 
 attach variables [ fD fB fA fC fS fT ]
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
index 5a86f6548b..b46fd4df2a 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
@@ -2573,23 +2573,21 @@ define pcodeop InstructionCacheBlockLockSetX;
 	D = inst_next + sext(OFF16SH);
 }
 
-:cmpeqb BF2,A,B			is $(NOTVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=224 & A & B & BF2 {
+:cmpeqb CRFD,A,B			is $(NOTVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=224 & A & B & CRFD {
 	tmpa:1 = A:1;
-	tmps:1 = (tmpa == B[0,8]) | (tmpa == B[8,8]) | (tmpa == B[16,8]) | (tmpa == B[24,8]);
+	CRFD = (tmpa == B[0,8]) | (tmpa == B[8,8]) | (tmpa == B[16,8]) | (tmpa == B[24,8]);
 @if REGISTER_SIZE == "8"
-	tmps = tmps | (tmpa == B[32,8]) | (tmpa == B[40,8]) | (tmpa == B[48,8]) | (tmpa == B[56,8]);
+	CRFD = CRFD | (tmpa == B[32,8]) | (tmpa == B[40,8]) | (tmpa == B[48,8]) | (tmpa == B[56,8]);
 @endif
-	tmpc:8 = zext(tmps);
-	crall = crall | (tmpc << ((BF2*8) + 2));	
 }
 
-:cmprb BF2,L2,A,B		is $(NOTVLE) & OP=31 & BIT_22=0 & BIT_0=0 & XOP_1_10=192 & A & B & BF2 & L2 {
+:cmprb CRFD,L2,A,B		is $(NOTVLE) & OP=31 & BIT_22=0 & BIT_0=0 & XOP_1_10=192 & A & B & CRFD & L2 {
 	tmpin:1 = A:1;
 	tmp1lo:1 = B[16,8];
 	tmp1hi:1 = B[24,8];
 	tmp2lo:1 = B[0,8];
 	tmp2hi:1 = B[8,8];
-	tmps:1 = ((tmpin >= tmp2lo) & (tmpin <= tmp2hi)) | (((tmpin >= tmp1lo) & (tmpin <= tmp1hi)) * L2:1);
+	CRFD = ((tmpin >= tmp2lo) & (tmpin <= tmp2hi)) | (((tmpin >= tmp1lo) & (tmpin <= tmp1hi)) * L2:1);
 }
 
 :cnttzw A,S				is OP=31 & S & A & BITS_11_15=0 & XOP_1_10=538 & Rc=0 {
@@ -2685,10 +2683,8 @@ define pcodeop InstructionCacheBlockLockSetX;
 	D = tmpp:8;
 }
 
-:mcrxrx BF2				is $(NOTVLE) & OP=31 & BITS_11_22=0 & BIT_0=0 & XOP_1_10=576 & BF2 {
-	tmp:1 = (xer_ov << 3) | (xer_ov32 << 2) | (xer_ca << 1) | (xer_ca32);
-	tmp2:8 = zext(tmp);
-	crall = crall | (tmp2 << (8*BF2:1));
+:mcrxrx CRFD			is $(NOTVLE) & OP=31 & BITS_11_22=0 & BIT_0=0 & XOP_1_10=576 & CRFD {
+	CRFD = (xer_ov << 3) | (xer_ov32 << 2) | (xer_ca << 1) | (xer_ca32);
 }
 
 :modsd D,A,B			is $(NOTVLE) & OP=31 & D & A & B & XOP_1_10=777 & BIT_0=0 {
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
index fa321fc2b2..f692d3b56c 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
@@ -551,11 +551,11 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 	cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);
 }
 
+
 :e_cmpi BF_VLE,A,SCALE			is $(ISVLE) & OP=6 & XOP_11_VLE=21 & BITS_23_25=0 & A & BF_VLE & SCALE {
 	tmpA:4 = A:4;
 	tmpB:4 = SCALE:4;
-	tmpC:8 = zext(((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1));
-	crall = crall | (tmpC << (BF_VLE*8));
+	BF_VLE = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);
 }
 
 :se_cmp RX_VLE,RY_VLE			is $(ISVLE) & OP6_VLE=3 & BITS_8_9=0 & RX_VLE & RY_VLE {
@@ -579,8 +579,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 :e_cmpli BF_VLE,A,SCALE			is $(ISVLE) & OP=6 & XOP_11_VLE=21 & BITS_23_25=1 & A & BF_VLE & SCALE {
 	tmpA:4 = A:4;
 	tmpB:4 = SCALE:4;
-	tmpC:8 = zext(((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1));
-	crall = crall | (tmpC << (BF_VLE*8));	
+	BF_VLE = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);
 }
 
 :se_cmpl RX_VLE,RY_VLE			is $(ISVLE) & OP6_VLE=3 & BITS_8_9=1 & RX_VLE & RY_VLE {
@@ -595,11 +594,10 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 	cr0 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);			
 }
 
-:e_cmph BF2,A,B					is $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=14 & A & B & BF2 {
+:e_cmph CRFD,A,B					is $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=14 & A & B & CRFD {
 	tmpA:2 = A:2;
 	tmpB:2 = B:2;
-	tmpC:8 = zext(((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1));		
-	crall = crall | (tmpC << (BF2*8));	
+	CRFD = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);			
 }
 
 :se_cmph RX_VLE,RY_VLE			is $(ISVLE) & OP6_VLE=3 & BITS_8_9=2 & RX_VLE & RY_VLE {
@@ -614,11 +612,11 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 	cr0 = ((tmpA s< tmpB) << 3) | ((tmpA s> tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);		
 }
 
-:e_cmphl BF2,A,B				is $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=46 & A & B & BF2 {
+:e_cmphl CRFD,A,B				is $(ISVLE) & OP=31 & BITS_21_22=0 & BIT_0=0 & XOP_1_10=46 & A & B & CRFD {
 	tmpA:2 = A:2;
 	tmpB:2 = B:2;
-	tmpC:8 = zext(((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1));		
-	crall = crall | (tmpC << (BF2*8));		
+	tmpC:1 = ((tmpA < tmpB) << 3) | ((tmpA > tmpB) << 2) | ((tmpA == tmpB) << 1) | (xer_so & 1);		
+	CRFD = tmpC;		
 }
 
 :se_cmphl RX_VLE,RY_VLE			is $(ISVLE) & OP6_VLE=3 & BITS_8_9=3 & RX_VLE & RY_VLE {