From 6208df2d50d716b4faf87d3a0c0603d45aac4cb3 Mon Sep 17 00:00:00 2001
From: ghidra1 <ghidra1@users.noreply.github.com>
Date: Tue, 13 Jan 2026 10:44:59 -0500
Subject: [PATCH] GP-1 Corrected RISCV import opinion file

---
 .../RISCV/data/languages/riscv.opinion          | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.opinion b/Ghidra/Processors/RISCV/data/languages/riscv.opinion
index 4f550dedbc..dee07a29d9 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.opinion
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.opinion
@@ -11,18 +11,11 @@
       <!-- EF_RISCV_ABI_QUAD          0x0006  -->
       <!-- EF_RISCV_RVE               0x0008  -->
       <!-- EF_RISCV_TSO               0x0010  -->
-      <constraint primary="243" secondary="0" processor="RISCV" endian="little" size="32" variant="RV32I"/>
-      <constraint primary="243" secondary="0" processor="RISCV" endian="little" size="64" variant="RV64I"/>
-      <constraint primary="243" secondary="1" processor="RISCV" endian="little" size="32" variant="RV32IMC"/>
-      <constraint primary="243" secondary="1" processor="RISCV" endian="little" size="64" variant="RV64IC"/>
-      <constraint primary="243" secondary="2" processor="RISCV" endian="little" size="32" variant="RV32IF"/>
-      <constraint primary="243" secondary="3" processor="RISCV" endian="little" size="32" variant="RV32GC"/> <!-- RV32IMAFC -->
-      <constraint primary="243" secondary="4" processor="RISCV" endian="little" size="32" variant="RV32G"/>
-      <constraint primary="243" secondary="4" processor="RISCV" endian="little" size="64" variant="RV64G"/>
-      <constraint primary="243" secondary="5" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
-      <constraint primary="243" secondary="5" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
-      <constraint primary="243" processor="RISCV" endian="little" size="32" variant="RV32GC"/>
-      <constraint primary="243" processor="RISCV" endian="little" size="64" variant="RV64GC"/>
+      
+      <constraint primary="243" processor="RISCV" endian="little" size="32"/> <!-- must choose between 'default' and 'AndeStar' variants -->
+      <constraint primary="243" processor="RISCV" endian="little" size="64" variant="default"/>
+      
     </constraint>
+    
   </constraint>
 </opinions>