diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
index d242f70dcd..ab3fbedb3c 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.ldefs
@@ -6,7 +6,7 @@
             endian="little"
             size="64"
             variant="RV64I"
-            version="1.2"
+            version="1.3"
             slafile="riscv.lp64d.sla"
             processorspec="RV64I.pspec"
             id="RISCV:LE:64:RV64I">
@@ -19,7 +19,7 @@
             endian="little"
             size="64"
             variant="RV64IC"
-            version="1.2"
+            version="1.3"
             slafile="riscv.lp64d.sla"
             processorspec="RV64IC.pspec"
             id="RISCV:LE:64:RV64IC">
@@ -32,7 +32,7 @@
             endian="little"
             size="64"
             variant="RV64G"
-            version="1.2"
+            version="1.3"
             slafile="riscv.lp64d.sla"
             processorspec="RV64G.pspec"
             id="RISCV:LE:64:RV64G">
@@ -45,7 +45,7 @@
             endian="little"
             size="64"
             variant="RV64GC"
-            version="1.2"
+            version="1.3"
             slafile="riscv.lp64d.sla"
             processorspec="RV64GC.pspec"
             id="RISCV:LE:64:RV64GC">
@@ -58,7 +58,7 @@
             endian="little"
             size="64"
             variant="default"
-            version="1.2"
+            version="1.3"
             slafile="riscv.lp64d.sla"
             processorspec="RV64GC.pspec"
             id="RISCV:LE:64:default">
@@ -71,7 +71,7 @@
             endian="little"
             size="32"
             variant="RV32I"
-            version="1.2"
+            version="1.3"
             slafile="riscv.ilp32d.sla"
             processorspec="RV32I.pspec"
             id="RISCV:LE:32:RV32I">
@@ -84,7 +84,7 @@
             endian="little"
             size="32"
             variant="RV32IC"
-            version="1.2"
+            version="1.3"
             slafile="riscv.ilp32d.sla"
             processorspec="RV32IC.pspec"
             id="RISCV:LE:32:RV32IC">
@@ -97,7 +97,7 @@
             endian="little"
             size="32"
             variant="RV32IMC"
-            version="1.2"
+            version="1.3"
             slafile="riscv.ilp32d.sla"
             processorspec="RV32IMC.pspec"
             id="RISCV:LE:32:RV32IMC">
@@ -110,7 +110,7 @@
             endian="little"
             size="32"
             variant="RV32G"
-            version="1.2"
+            version="1.3"
             slafile="riscv.ilp32d.sla"
             processorspec="RV32G.pspec"
             id="RISCV:LE:32:RV32G">
@@ -123,7 +123,7 @@
             endian="little"
             size="32"
             variant="RV32GC"
-            version="1.2"
+            version="1.3"
             slafile="riscv.ilp32d.sla"
             processorspec="RV32GC.pspec"
             id="RISCV:LE:32:RV32GC">
@@ -136,7 +136,7 @@
             endian="little"
             size="32"
             variant="default"
-            version="1.2"
+            version="1.3"
             slafile="riscv.ilp32d.sla"
             processorspec="RV32GC.pspec"
             id="RISCV:LE:32:default">
diff --git a/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc b/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
index c93efef488..0fbdfac2e1 100644
--- a/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
+++ b/Ghidra/Processors/RISCV/data/languages/riscv.rv32i.sinc
@@ -123,15 +123,15 @@
 }
 
 # jal d,a 0000006f 0000007f JSR (0, 0) 
-# call if RA set, destreg == RA
-:jal ra,immUJ is immUJ & ra & r0711=1 & op0001=0x3 & op0204=0x3 & op0506=0x3
+# call for rd = RA|T0 set to inst_next
+:jal rd,immUJ is immUJ & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x3 & op0506=0x3
 {
-	ra = inst_next;
+	rd = inst_next;
 	call immUJ;
 }
 
-# goto if RA not set, destreg != RA
-:jal rd,immUJ is immUJ & rd & op0001=0x3 & op0204=0x3 & op0506=0x3
+# goto for all other rd set to inst_next
+:jal rd,immUJ is immUJ & rd & r0711 & op0001=0x3 & op0204=0x3 & op0506=0x3
 {
 	rd = inst_next;
 	goto immUJ;
@@ -144,16 +144,16 @@
 }
 
 # jalr d,s,j 00000067 0000707f JSR (0, 0)
-# call if RA set, destreg == RA
-:jalr ra,rs1,immI is rs1 & immI & ra & r0711=1 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
+# call for rd = RA|T0 set to inst_next
+:jalr rd,rs1,immI is rs1 & immI & rd & (r0711=1 | r0711=5) & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
 {
 	local ea:$(XLEN) = (rs1 + immI) & ~1;
-	ra = inst_next;
+	rd = inst_next;
 	call [ea];
 }
 
-# goto if RA not set, destreg != RA
-:jalr rd,rs1,immI is rs1 & immI & rd & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
+# goto for all other rd set to inst_next
+:jalr rd,rs1,immI is rs1 & immI & rd & r0711 & op0001=0x3 & op0204=0x1 & op0506=0x3 & funct3=0x0
 {
 	local ea:$(XLEN) = (rs1 + immI) & ~1;
 	rd = inst_next;