diff --git a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
index 0f46b8f4ed..1820bedcff 100644
--- a/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
+++ b/Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
@@ -2396,7 +2396,7 @@ define pcodeop ExclusiveAccess;
 :ldrsb^ItCond^".w"  Rt1215,PcrelOffset12         is TMode=1 & ItCond & (op8=0xf9 & thc0506=0 & thc0404=1 & sop0003=15; Rt1215) & PcrelOffset12
 {
    build ItCond;
-   tmp:1 = *PcrelOffset12;
+   tmp:1 = PcrelOffset12:1;
    Rt1215 = sext(tmp);
 }
 
@@ -2437,7 +2437,7 @@ define pcodeop ExclusiveAccess;
 {
    build ItCond;
    build PcrelOffset12;
-   tmp:2 = *PcrelOffset12;
+   tmp:2 = PcrelOffset12:2;
    Rt1215 = sext(tmp);
 }