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AVR8: Improve operands for load/store instructions

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Currently, the operators for post-incremented or offset source operands
associated with various memory access instructions are separators
rather than components of the operand. As a result, inferred references
split the register and the operator when rendered in the listing, making
it easy to overlook the operator. For example:

lpm R0,Z=>DAT_code_000455+

This patch mimics logic already in place for the st and std
instructions, which include the post-increment operator or offset as
part of the operand. For example:

st X+=>DAT_mem_0100,R0
This commit is contained in:
Austin Roach
2019-04-04 21:51:04 -04:00
committed by ghidorahrex
parent ac66dab16b
commit 3bad6f753f
1 changed files with 22 additions and 20 deletions
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Ghidra/Processors/Atmel/data/languages/avr8.sinc
+22 -20
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@@ -747,7 +747,8 @@ define pcodeop break;
RdFull = val:1; RdFull = val:1;
} }
:elpm RdFull, Z^"+" is phase=1 & ophi7=0x48 & oplow4=0x7 & RdFull & Z { ElpmPlus: Z^"+" is Z {}
:elpm RdFull, ElpmPlus is phase=1 & ophi7=0x48 & oplow4=0x7 & RdFull & ElpmPlus {
ptr:3 = zext(Z) | (zext(RAMPZ) << 16); ptr:3 = zext(Z) | (zext(RAMPZ) << 16);
tmp:2 = *[code]:2 (ptr >> 1); tmp:2 = *[code]:2 (ptr >> 1);
val:2 = (tmp >> (8 * (Z & 0x1))); val:2 = (tmp >> (8 * (Z & 0x1)));
@@ -836,10 +837,9 @@ define pcodeop break;
} }
# ld Rd,Y+ ; ld Rd, X+; ld Rd, Z+ # ld Rd,Y+ ; ld Rd, X+; ld Rd, Z+
:ld RdFull,RstPtr"+" is phase=1 & ophi7=0x48 & oplow2=0x01 & RdFull & RstPtr { LdPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; }
tmp:2 = RstPtr; :ld RdFull,LdPlus is phase=1 & ophi7=0x48 & oplow2=0x01 & RdFull & LdPlus {
RdFull = *[mem]:1 tmp; RdFull = *[mem]:1 LdPlus;
RstPtr = RstPtr + 0x01;
} }
# ld Rd,-Y ; ld Rd, -X; ld Rd, -Z # ld Rd,-Y ; ld Rd, -X; ld Rd, -Z
@@ -852,9 +852,9 @@ LdPredec: "-"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; }
# ldd Rd,Y+q # ldd Rd,Y+q
# ldd Rd,Z+q # ldd Rd,Z+q
:ldd RdFull,Rstq"+"q6 is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=0 & Rstq & RdFull & q6 { LddYq: Rstq^"+"^q6 is Rstq & q6 { local ptr = Rstq + zext(q6); export ptr; }
local ptr = Rstq + zext(q6); :ldd RdFull,LddYq is phase=1 & ophi2=0x2 & opbit12=0 & opbit9=0 & LddYq & RdFull {
RdFull = *[mem]:1 ptr; RdFull = *[mem]:1 LddYq;
} }
# Rd,K # Rd,K
@@ -903,12 +903,13 @@ LdPredec: "-"^RstPtr is RstPtr { RstPtr = RstPtr - 0x01; export RstPtr; }
RdFull = val:1; RdFull = val:1;
} }
# lpm Rd,Z+ # lpm Rd,Z+
:lpm RdFull,Z"+" is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & Z & opbit0=1 { LpmPlus: Z^"+" is Z {}
ptr:$(PCBYTESIZE) = zext(Z); :lpm RdFull,LpmPlus is phase=1 & ophi7=0x48 & op1to3=0x2 & RdFull & LpmPlus & opbit0=1 {
tmp:$(PCBYTESIZE) = *[code]:$(PCBYTESIZE) (ptr >> 1); ptr:3 = zext(Z);
val:$(PCBYTESIZE) = (tmp >> (8 * (Z & 0x1))); tmp:2 = *[code]:2 (ptr >> 1);
RdFull = val:1; val:2 = (tmp >> (Z & 0x1));
Z = Z + 1; RdFull = val:1;
Z = Z + 1;
} }
# lsl - just an assembly mnemonic for add # lsl - just an assembly mnemonic for add
:lsr RdFull is phase=1 & ophi7=0x4a & oplow4=0x6 & RdFull { :lsr RdFull is phase=1 & ophi7=0x4a & oplow4=0x6 & RdFull {
@@ -1086,11 +1087,13 @@ define pcodeop store_program_mem; # make this stand out.
*[code]:$(PCBYTESIZE) ptr = R1R0; *[code]:$(PCBYTESIZE) ptr = R1R0;
store_program_mem(); store_program_mem();
} }
:spm Z^"+" is phase=1 & ophi16=0x95f8 & Z {
ptr:$(PCBYTESIZE) = zext(Z) << 1; SpmPlus: Z^"+" is Z {}
*[code]:$(PCBYTESIZE) ptr = R1R0; :spm SpmPlus is phase=1 & ophi16=0x95f8 & SpmPlus {
Z = Z + 1; ptr:3 = zext(Z) << 1;
store_program_mem(); *[code]:2 ptr = R1R0;
Z = Z + 1;
store_program_mem();
} }
# For stores, see the ld code (just flip bit 9) # For stores, see the ld code (just flip bit 9)
:st X, RdFull is phase=1 & ophi7=0x49 & oplow4=0xc & X & RdFull { :st X, RdFull is phase=1 & ophi7=0x49 & oplow4=0xc & X & RdFull {
@@ -1105,7 +1108,6 @@ define pcodeop store_program_mem; # make this stand out.
# st Rd,Y+ ; st Rd, X+; st Rd, Z+ # st Rd,Y+ ; st Rd, X+; st Rd, Z+
StPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; } StPlus: RstPtr^"+" is RstPtr { tmp:2 = RstPtr; RstPtr = RstPtr + 0x01; export tmp; }
:st StPlus, RdFull is phase=1 & ophi7=0x49 & oplow2=0x01 & RdFull & StPlus { :st StPlus, RdFull is phase=1 & ophi7=0x49 & oplow2=0x01 & RdFull & StPlus {
*[mem]:1 StPlus = RdFull; *[mem]:1 StPlus = RdFull;
} }