Mirrors_Framework/ghidra
1
0
Fork 0
mirror of https://github.com/NationalSecurityAgency/ghidra.git synced 2026-06-02 00:47:04 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

GP-5334: Corrected operand count for m68k addressing modes

Browse Source
This commit is contained in:
ghidorahrex
2025-02-03 17:36:04 +00:00
parent 46d97d9579
commit 27b06c83a6
1 changed files with 416 additions and 374 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Ghidra/Processors/68000/data/languages/68000.sinc
+134 -92
View File
@@ -101,6 +101,7 @@ define token instr (16)
op5 = (5,5) op5 = (5,5)
op7 = (7,7) op7 = (7,7)
op8 = (8,8) op8 = (8,8)
op10 = (10,10)
op11 = (11,11) op11 = (11,11)
quick = (9,11) quick = (9,11)
op811 = (8,11) op811 = (8,11)
@@ -258,6 +259,7 @@ define token bdisp32 (32) bd32 = (0,31) signed;
define token odisp16 (16) od16 = (0,15) signed; define token odisp16 (16) od16 = (0,15) signed;
define token odisp32 (32) od32 = (0,31) signed; define token odisp32 (32) od32 = (0,31) signed;
define token fldparm (16) define token fldparm (16)
fldpar=(0,15)
flddo=(11,11) flddo=(11,11)
fldoffdat=(6,10) fldoffdat=(6,10)
fldoffreg=(6,8) fldoffreg=(6,8)
@@ -588,6 +590,12 @@ f_wd: fldwdreg is flddw=1 & fldwdreg { export fldwdreg; }
rreg: regxdn is da=0 & regxdn { export regxdn; } rreg: regxdn is da=0 & regxdn { export regxdn; }
rreg: regxan is da=1 & regxan { export regxan; } rreg: regxan is da=1 & regxan { export regxan; }
regPlus: (regan)+ is regan { export regan; }
regxPlus: (regxan)+ is regxan { export regxan; }
reg9Plus: (reg9an)+ is reg9an { export reg9an; }
regParen: (regan) is regan { export regan; }
d32l: (d32)".l" is d32 { export *[const]:4 d32; }
# Condition codes # Condition codes
cc: "t" is op811=0 { export 1:1; } cc: "t" is op811=0 { export 1:1; }
@@ -1043,7 +1051,8 @@ with : extGUARD=1 {
local source = regdn; mask:4 = 1 << (const8 & 31); ZF = (source & mask) == 0; regdn = source & (~mask); local source = regdn; mask:4 = 1 << (const8 & 31); ZF = (source & mask) == 0; regdn = source & (~mask);
} }
:bfchg e2l{f_off:f_wd} is opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { bfOffWd: {f_off:f_wd} is f_off & f_wd { }
:bfchg e2l^bfOffWd is opbig=0xea & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
tmp:4 = e2l; tmp:4 = e2l;
getbitfield(tmp, f_off, f_wd); getbitfield(tmp, f_off, f_wd);
@@ -1053,7 +1062,7 @@ with : extGUARD=1 {
e2l = (tmp & ~mask) | (~(tmp & mask) & mask); e2l = (tmp & ~mask) | (~(tmp & mask) & mask);
} }
:bfclr e2l{f_off:f_wd} is opbig=0xec & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bfclr e2l^bfOffWd is opbig=0xec & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
tmp:4 = e2l; tmp:4 = e2l;
getbitfield(tmp, f_off, f_wd); getbitfield(tmp, f_off, f_wd);
@@ -1063,7 +1072,7 @@ with : extGUARD=1 {
e2l = tmp & ~mask; e2l = tmp & ~mask;
} }
:bfexts e2l{f_off:f_wd},f_reg is opbig=0xeb & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bfexts e2l^bfOffWd,f_reg is opbig=0xeb & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
tmp:4 = e2l; tmp:4 = e2l;
tmp = tmp << f_off; tmp = tmp << f_off;
@@ -1073,7 +1082,7 @@ with : extGUARD=1 {
resbitflags(tmp2, f_wd-1); resbitflags(tmp2, f_wd-1);
} }
:bfextu e2l{f_off:f_wd},f_reg is opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bfextu e2l^bfOffWd,f_reg is opbig=0xe9 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
tmp:4 = e2l; tmp:4 = e2l;
getbitfield(tmp, f_off, f_wd); getbitfield(tmp, f_off, f_wd);
@@ -1081,7 +1090,7 @@ with : extGUARD=1 {
resbitflags(tmp, f_wd-1); resbitflags(tmp, f_wd-1);
} }
:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l :bfffo e2l^bfOffWd,f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg & flddo=0 & fldoffdat=0 & flddw=0 & fldwddat=0; e2l
[ savmod2=savmod1; regtsan=regtfan; ] { [ savmod2=savmod1; regtsan=regtfan; ] {
# "Find First One in Bit Field" pronounced "boo-foe" # "Find First One in Bit Field" pronounced "boo-foe"
# Set the destination f_reg with the position of the first 1 bit in the source e2l. # Set the destination f_reg with the position of the first 1 bit in the source e2l.
@@ -1096,7 +1105,7 @@ with : extGUARD=1 {
f_reg = zext(tmp != 0) * lzcount(tmp); f_reg = zext(tmp != 0) * lzcount(tmp);
} }
:bfffo e2l{f_off:f_wd},f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg ; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bfffo e2l^bfOffWd,f_reg is opbig=0xed & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg ; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
local tmp:4 = e2l; local tmp:4 = e2l;
tmp = (tmp << f_off) >> (32 - f_wd); tmp = (tmp << f_off) >> (32 - f_wd);
tmp = (tmp << (32 - f_wd)); tmp = (tmp << (32 - f_wd));
@@ -1109,7 +1118,7 @@ with : extGUARD=1 {
} }
:bfins f_reg,e2l{f_off:f_wd} is opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bfins f_reg,e2l^bfOffWd is opbig=0xef & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd & f_reg; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
mask:4 = 0; mask:4 = 0;
bitmask(mask, f_wd); bitmask(mask, f_wd);
@@ -1119,7 +1128,7 @@ with : extGUARD=1 {
e2l = (e2l & ~mask) | (tmp << (32 - f_off - f_wd)); e2l = (e2l & ~mask) | (tmp << (32 - f_off - f_wd));
} }
:bfset e2l{f_off:f_wd} is opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bfset e2l^bfOffWd is opbig=0xee & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
tmp:4 = e2l; tmp:4 = e2l;
getbitfield(tmp, f_off, f_wd); getbitfield(tmp, f_off, f_wd);
@@ -1129,7 +1138,7 @@ with : extGUARD=1 {
e2l = e2l & ~mask; e2l = e2l & ~mask;
} }
:bftst e2l{f_off:f_wd} is opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :bftst e2l^bfOffWd is opbig=0xe8 & op67=3 & $(DAT_DIR_CTL_ADDR_MODES); bfOffWd & f_off & f_wd; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
logflags(); logflags();
tmp:4 = e2l; tmp:4 = e2l;
getbitfield(tmp, f_off, f_wd); getbitfield(tmp, f_off, f_wd);
@@ -1220,6 +1229,7 @@ define pcodeop callm;
ZF = 0; ZF = 0;
NF = 1; NF = 1;
} }
:cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2) is op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 { :cas2.l regdc:regdc2,regdu:regdu2,(regda):(regda2) is op015=0x0efc; regda & ext_911=0 & regdu & ext_35=0 & regdc; regda2 & ext2_911=0 & regdu2 & ext2_35=0 & regdc2 {
if(regdc!=regda) goto <ne>; if(regdc!=regda) goto <ne>;
if(regdc2!=regda2) goto <ne>; if(regdc2!=regda2) goto <ne>;
@@ -1247,6 +1257,7 @@ define pcodeop callm;
ZF = 1; ZF = 1;
NF = 0; NF = 0;
} }
:cas.w regdcw,regduw,e2w is opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w [ savmod2=savmod1; regtsan=regtfan; ] { :cas.w regdcw,regduw,e2w is opbig=0x0c & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regduw & ext_35=0 & regdcw; e2w [ savmod2=savmod1; regtsan=regtfan; ] {
local tmp = e2w; local tmp = e2w;
if(tmp==regdcw) goto <eq>; if(tmp==regdcw) goto <eq>;
@@ -1259,6 +1270,7 @@ define pcodeop callm;
ZF = 1; ZF = 1;
NF = 0; NF = 0;
} }
:cas.l regdc,regdu,e2l is opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l [ savmod2=savmod1; regtsan=regtfan; ] { :cas.l regdc,regdu,e2l is opbig=0x0e & op67=3 & $(MEM_ALTER_ADDR_MODES); regda=0 & ext_911=0 & regdu & ext_35=0 & regdc; e2l [ savmod2=savmod1; regtsan=regtfan; ] {
local tmp = e2l; local tmp = e2l;
if(tmp==regdc) goto <eq>; if(tmp==regdc) goto <eq>;
@@ -1417,11 +1429,11 @@ cachetype: "both" is op67=3 { export 3:4; }
:cmpi.w const16,e2w is opbig=12 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { o2:2=e2w; subflags(o2,const16); local tmp =o2-const16; resflags(tmp);} :cmpi.w const16,e2w is opbig=12 & op67=1 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const16; e2w [ savmod2=savmod1; regtsan=regtfan; ] { o2:2=e2w; subflags(o2,const16); local tmp =o2-const16; resflags(tmp);}
:cmpi.l const32,e2l is opbig=12 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { o2:4=e2l; subflags(o2,const32); local tmp =o2-const32; resflags(tmp);} :cmpi.l const32,e2l is opbig=12 & op67=2 & savmod1 & regtfan & $(DAT_ALTER_ADDR_MODES); const32; e2l [ savmod2=savmod1; regtsan=regtfan; ] { o2:4=e2l; subflags(o2,const32); local tmp =o2-const32; resflags(tmp);}
:cmpm.b (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=0 & op5=0 & op34=1 & regan { local tmp1=*:1 regan; regan=regan+1; local tmp2=*:1 reg9an; reg9an=reg9an+1; :cmpm.b regPlus,reg9Plus is op=11 & reg9Plus & op8=1 & op67=0 & op5=0 & op34=1 & regPlus { local tmp1=*:1 regPlus; regPlus=regPlus+1; local tmp2=*:1 reg9Plus; reg9Plus=reg9Plus+1;
subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
:cmpm.w (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=1 & op5=0 & op34=1 & regan { local tmp1=*:2 regan; regan=regan+2; local tmp2=*:2 reg9an; reg9an=reg9an+2; :cmpm.w regPlus,reg9Plus is op=11 & reg9Plus & op8=1 & op67=1 & op5=0 & op34=1 & regPlus { local tmp1=*:2 regPlus; regPlus=regPlus+2; local tmp2=*:2 reg9Plus; reg9Plus=reg9Plus+2;
subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
:cmpm.l (regan)+,(reg9an)+ is op=11 & reg9an & op8=1 & op67=2 & op5=0 & op34=1 & regan { local tmp1=*:4 regan; regan=regan+4; local tmp2=*:4 reg9an; reg9an=reg9an+4; :cmpm.l regPlus,reg9Plus is op=11 & reg9Plus & op8=1 & op67=2 & op5=0 & op34=1 & regPlus { local tmp1=*:4 regPlus; regPlus=regPlus+4; local tmp2=*:4 reg9Plus; reg9Plus=reg9Plus+4;
subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); } subflags(tmp2,tmp1); local tmp =tmp2-tmp1; resflags(tmp); }
# cpBcc # need to know specific copressors use copcc1 # cpBcc # need to know specific copressors use copcc1
# cpDBcc # use copcc2 # cpDBcc # use copcc2
@@ -1429,7 +1441,8 @@ cachetype: "both" is op67=3 { export 3:4; }
# cpScc # use copcc2 # cpScc # use copcc2
# cpTRAPcc # use copcc2 # cpTRAPcc # use copcc2
:db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16 { :db^cc regdnw,addr16 is op=5 & cc & op67=3 & op5=0 & op34=1 & regdnw; addr16
{
if (cc) goto inst_next; if (cc) goto inst_next;
regdnw=regdnw-1; regdnw=regdnw-1;
if (regdnw!=-1) goto addr16; if (regdnw!=-1) goto addr16;
@@ -1445,14 +1458,16 @@ cachetype: "both" is op67=3 { export 3:4; }
reg9dn = (rem << 16) | (div & 0xffff); reg9dn = (rem << 16) | (div & 0xffff);
} }
:divu.w eaw,reg9dn is (op=8 & reg9dn & op68=3)... & eaw { :divu.w eaw,reg9dn is (op=8 & reg9dn & op68=3)... & eaw
{
local denom = zext(eaw); local denom = zext(eaw);
local divis = reg9dn; local divis = reg9dn;
local div = divis / denom; local div = divis / denom;
local rem = divis % denom; local rem = divis % denom;
CF=0; CF=0;
resflags(div); resflags(div);
reg9dn = (rem << 16) | (div & 0xffff); } reg9dn = (rem << 16) | (div & 0xffff);
}
#remyes: "s" is regdq & (regdr=regdq) & divsgn=1 { } #remyes: "s" is regdq & (regdr=regdq) & divsgn=1 { }
remyes: "sl" is divsgn=1 { } remyes: "sl" is divsgn=1 { }
@@ -1541,24 +1556,27 @@ subdiv: regdr:regdq is regdq & regdr & divsz=1 & divsgn=1 {
# jump addresses derived from effective address calculation # jump addresses derived from effective address calculation
addrpc16: reloc is d16 [ reloc = inst_start+2+d16; ] { export *[ram]:4 reloc; } addrpc16: reloc is d16 [ reloc = inst_start+2+d16; ] { export *[ram]:4 reloc; }
addrd16: d16 is d16 { export *[ram]:4 d16; } addrd16: d16".w" is d16 { export *[ram]:4 d16; }
addrd32: d32 is d32 { export *[ram]:4 d32; } addrd32: d32".l" is d32 { export *[ram]:4 d32; }
addrReg: (regan) is regan { export regan; }
addrRegD16: (d16,regan) is regan; d16 {local tmp = regan + d16; export *[ram]:4 tmp; }
addrextw: (extw) is extw { export extw; }
:jmp (regan) is opbig=0x4e & op67=3 & mode=2 & regan { goto [regan]; } :jmp addrReg is opbig=0x4e & op67=3 & mode=2 & addrReg { goto [addrReg]; }
:jmp (d16,regan) is opbig=0x4e & op67=3 & mode=5 & regan; d16 { local tmp = regan + d16; goto [tmp]; } :jmp addrRegD16 is (opbig=0x4e & op67=3 & mode=5) ... & addrRegD16 { goto [addrRegD16]; }
:jmp (extw) is opbig=0x4e & op67=3 & mode=6 & regan; extw [ pcmode=0; regtfan=regan; ] { build extw; goto [extw]; } :jmp addrextw is opbig=0x4e & op67=3 & mode=6 & regan; addrextw [ pcmode=0; regtfan=regan; ] { goto [addrextw]; }
:jmp addrpc16 is opbig=0x4e & op67=3 & mode=7 & regan=2; addrpc16 { goto addrpc16; } :jmp addrpc16 is opbig=0x4e & op67=3 & mode=7 & regan=2; addrpc16 { goto addrpc16; }
:jmp (extw) is opbig=0x4e & op67=3 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; goto [extw]; } :jmp addrextw is opbig=0x4e & op67=3 & mode=7 & regan=3; addrextw [ pcmode=1; ] { goto [addrextw]; }
:jmp addrd16".w" is opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16 { goto addrd16; } :jmp addrd16 is opbig=0x4e & op67=3 & mode=7 & regan=0; addrd16 { goto addrd16; }
:jmp addrd32".l" is opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32 { goto addrd32; } :jmp addrd32 is opbig=0x4e & op67=3 & mode=7 & regan=1; addrd32 { goto addrd32; }
:jsr (regan) is opbig=0x4e & op67=2 & mode=2 & regan { SP=SP-4; *:4 SP = inst_next; call [regan]; } :jsr addrReg is opbig=0x4e & op67=2 & mode=2 & addrReg { SP=SP-4; *:4 SP = inst_next; call [addrReg]; }
:jsr (d16,regan) is opbig=0x4e & op67=2 & mode=5 & regan; d16 { SP=SP-4; *:4 SP = inst_next; local tmp = regan + d16; call [tmp]; } :jsr addrRegD16 is (opbig=0x4e & op67=2 & mode=5) ... & addrRegD16 { SP=SP-4; *:4 SP = inst_next; call [addrRegD16]; }
:jsr (extw) is opbig=0x4e & op67=2 & mode=6 & regan; extw [ pcmode=0; regtfan=regan;] { build extw; SP=SP-4; *:4 SP=inst_next; call [extw];} :jsr addrextw is opbig=0x4e & op67=2 & mode=6 & regan; addrextw [ pcmode=0; regtfan=regan;] { build addrextw; SP=SP-4; *:4 SP=inst_next; call [addrextw];}
:jsr addrpc16 is opbig=0x4e & op67=2 & mode=7 & regan=2; addrpc16 { SP=SP-4; *:4 SP = inst_next; call addrpc16; } :jsr addrpc16 is opbig=0x4e & op67=2 & mode=7 & regan=2; addrpc16 { SP=SP-4; *:4 SP = inst_next; call addrpc16; }
:jsr (extw) is opbig=0x4e & op67=2 & mode=7 & regan=3; extw [ pcmode=1; ] { build extw; SP=SP-4; *:4 SP = inst_next; call [extw]; } :jsr addrextw is opbig=0x4e & op67=2 & mode=7 & regan=3; addrextw [ pcmode=1; ] { build addrextw; SP=SP-4; *:4 SP = inst_next; call [addrextw]; }
:jsr addrd16".w" is opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16 { SP=SP-4; *:4 SP = inst_next; call addrd16; } :jsr addrd16 is opbig=0x4e & op67=2 & mode=7 & regan=0; addrd16 { SP=SP-4; *:4 SP = inst_next; call addrd16; }
:jsr addrd32".l" is opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32 { SP=SP-4; *:4 SP = inst_next; call addrd32; } :jsr addrd32 is opbig=0x4e & op67=2 & mode=7 & regan=1; addrd32 { SP=SP-4; *:4 SP = inst_next; call addrd32; }
:lea eaptr,reg9an is (op=4 & reg9an & op68=7)... & eaptr { reg9an = eaptr; } :lea eaptr,reg9an is (op=4 & reg9an & op68=7)... & eaptr { reg9an = eaptr; }
@@ -1615,30 +1633,60 @@ macro shiftCXFlags(cntreg) {
@ifdef MC68040 @ifdef MC68040
:move16 (regan)+,(regxan)+ is opbig=0xf6 & op37=4 & regan; regxan & da=1 {local src=regan&0xfffffff0; local dst=regxan&0xfffffff0; regan=regan+16; regxan=regxan+16; macro move16(src, dst)
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; {
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } *:4 dst= *:4 src;
:move16 (regan)+,(d32)".l" is opbig=0xf6 & op37=0 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; regan=regan+16; src=src+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; dst=dst+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } *:4 dst= *:4 src;
:move16 (d32)".l",(regan)+ is opbig=0xf6 & op37=1 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; regan=regan+16; src=src+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; dst=dst+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } *:4 dst= *:4 src;
:move16 (regan),(d32)".l" is opbig=0xf6 & op37=2 & regan; d32 { local src=regan&0xfffffff0; dst:4=d32&0xfffffff0; src=src+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; dst=dst+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } *:4 dst= *:4 src;
:move16 (d32)".l",(regan) is opbig=0xf6 & op37=3 & regan; d32 { local dst=regan&0xfffffff0; src:4=d32&0xfffffff0; }
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4;
*:4 dst= *:4 src; src=src+4; dst=dst+4; *:4 dst= *:4 src;src=src+4;dst=dst+4; } :move16 regPlus,regxPlus is opbig=0xf6 & op37=4 & regan & regPlus; regxan & regxPlus & da=1 {
local src=regan&0xfffffff0;
local dst=regxan&0xfffffff0;
regan=regan+16;
regxan=regxan+16;
move16(src, dst);
}
:move16 regPlus,d32l is opbig=0xf6 & op37=0 & regan & regPlus; d32 & d32l {
local src=regan&0xfffffff0;
local dst:4=d32&0xfffffff0;
regan=regan+16;
move16(src, dst);
}
:move16 d32l,regPlus is opbig=0xf6 & op37=1 & regan & regPlus; d32 & d32l {
local dst=regan&0xfffffff0;
local src:4=d32&0xfffffff0;
regan=regan+16;
move16(src, dst);
}
:move16 regParen,d32l is opbig=0xf6 & op37=2 & regan & regParen; d32 & d32l {
local src=regan&0xfffffff0;
local dst:4=d32&0xfffffff0;
move16(src, dst);
}
:move16 d32l,regParen is opbig=0xf6 & op37=3 & regan & regParen; d32 & d32l {
local dst=regan&0xfffffff0;
local src:4=d32&0xfffffff0;
move16(src, dst);
}
@endif # MC68040 @endif # MC68040
@ifdef COLDFIRE @ifdef COLDFIRE
:mvs.b: eab, reg9dn is (op=0x7 & op68=4 & reg9dn )... &eab { reg9dn = sext(eab); } :mvs.b: eab, reg9dn is (op=0x7 & op68=4 & reg9dn )... & eab { reg9dn = sext(eab); }
:mvs.w: eaw, reg9dn is (op=0x7 & op68=5 & reg9dn )... &eaw { reg9dn = sext(eaw); } :mvs.w: eaw, reg9dn is (op=0x7 & op68=5 & reg9dn )... & eaw { reg9dn = sext(eaw); }
:mvz.b: eab, reg9dn is (op=0x7 & op68=6 & reg9dn )... &eab { reg9dn = zext(eab); } :mvz.b: eab, reg9dn is (op=0x7 & op68=6 & reg9dn )... & eab { reg9dn = zext(eab); }
:mvz.w: eaw, reg9dn is (op=0x7 & op68=7 & reg9dn )... &eaw { reg9dn = zext(eaw); } :mvz.w: eaw, reg9dn is (op=0x7 & op68=7 & reg9dn )... & eaw { reg9dn = zext(eaw); }
:mov3q "#"^d911, eal is (op=0xa & op68=5 & d911 ) ... &eal { eal = d911; }
:mov3q "#"^d911, eal is (op=0xa & op68=5 & d911 ) ... & eal { eal = d911; }
:sats.l regdn is opbig=0x4c & op37=0x10 & regdn { if (VF == 0) goto inst_next; regdn = (zext(regdn == 0 ) * 0x80000000) + (zext(regdn != 0) * 0x7fffffff); VF=0; CF=0; } :sats.l regdn is opbig=0x4c & op37=0x10 & regdn { if (VF == 0) goto inst_next; regdn = (zext(regdn == 0 ) * 0x80000000) + (zext(regdn != 0) * 0x7fffffff); VF=0; CF=0; }
@@ -1863,44 +1911,36 @@ m2rfl0: { m2rfl1" "SP} is SP & mvm15=1 & m2rfl1 { SP = *movemptr; movemptr = mov
m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { } m2rfl0: { m2rfl1} is mvm15=0 & m2rfl1 { }
movemOp: (regan) is mode=2 & regan { export regan; }
movemOp: (regan)+ is mode=3 & regan { export regan; }
movemOp: -(regan) is mode=4 & regan { export regan; }
movemOp: (d16, regan) is mode=5 & regan; fldpar ; d16 { local tmp = regan + d16; export tmp; }
movemOp: (extw) is mode=6 & regan; fldpar ; extw [ pcmode=0; regtfan=regan; ] {build extw; export extw; }
movemOp: (d16)".w" is mode=7 & regan=0; fldpar; d16 { local tmp:4 = d16; export tmp; }
movemOp: (d32)".l" is mode=7 & regan=1; fldpar; d32 { local tmp:4 = d32; export tmp; }
movemOp: (d16,PC) is op10=1 & mode=7 & regan=2; fldpar; d16 & PC { local tmp = inst_start + 4 + d16:4; export tmp; }
movemOp: (extw) is op10=1 & mode=7 & regan=3; fldpar; extw [ pcmode=1; ] { build extw; export extw; }
:movem.w r2mfw0,(regan) is opbig=0x48 & op67=2 & mode=2 & regan; r2mfw0 { movemptr = regan; build r2mfw0; } movemWrt: is (mode=3 | mode=4) & regan { regan = movemptr; }
:movem.w r2mbw0,-(regan) is opbig=0x48 & op67=2 & mode=4 & regan; r2mbw0 { movemptr = regan; build r2mbw0; regan = movemptr; } movemWrt: is mode { }
:movem.w r2mfw0,(d16,regan) is opbig=0x48 & op67=2 & mode=5 & regan; r2mfw0; d16 { movemptr = regan+d16; build r2mfw0; }
:movem.w r2mfw0,(extw) is opbig=0x48 & op67=2 & mode=6 & regan; r2mfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfw0; }
:movem.w r2mfw0,(d16)".w" is opbig=0x48 & op67=2 & mode=7 & regan=0; r2mfw0; d16 { movemptr = d16; build r2mfw0; }
:movem.w r2mfw0,(d32)".l" is opbig=0x48 & op67=2 & mode=7 & regan=1; r2mfw0; d32 { movemptr = d32; build r2mfw0; }
:movem.l r2mfl0,(regan) is opbig=0x48 & op67=3 & mode=2 & regan; r2mfl0 { movemptr = regan; build r2mfl0; }
:movem.l r2mbl0,-(regan) is opbig=0x48 & op67=3 & mode=4 & regan; r2mbl0 { movemptr = regan; build r2mbl0; regan = movemptr; }
:movem.l r2mfl0,(d16,regan) is opbig=0x48 & op67=3 & mode=5 & regan; r2mfl0; d16 { movemptr = regan+d16; build r2mfl0; }
:movem.l r2mfl0,(extw) is opbig=0x48 & op67=3 & mode=6 & regan; r2mfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build r2mfl0; }
:movem.l r2mfl0,(d16)".w" is opbig=0x48 & op67=3 & mode=7 & regan=0; r2mfl0; d16 { movemptr = d16; build r2mfl0; }
:movem.l r2mfl0,(d32)".l" is opbig=0x48 & op67=3 & mode=7 & regan=1; r2mfl0; d32 { movemptr = d32; build r2mfl0; }
:movem.w (regan),m2rfw0 is opbig=0x4c & op67=2 & mode=2 & regan; m2rfw0 { movemptr = regan; build m2rfw0; } :movem.w r2mfw0, movemOp is (opbig=0x48 & op67=2; r2mfw0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mfw0; }
:movem.w (regan)+,m2rfw0 is opbig=0x4c & op67=2 & mode=3 & regan; m2rfw0 { movemptr = regan; build m2rfw0; regan = movemptr; } :movem.w r2mbw0, movemOp is (opbig=0x48 & op67=2 & mode=4 & movemWrt; r2mbw0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mbw0; build movemWrt; }
:movem.w (d16,regan),m2rfw0 is opbig=0x4c & op67=2 & mode=5 & regan; m2rfw0; d16 { movemptr = regan+d16; build m2rfw0; }
:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=6 & regan; m2rfw0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfw0; }
:movem.w (d16,PC),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=2; m2rfw0; d16 & PC { movemptr = inst_start+4+d16; build m2rfw0; }
:movem.w (extw),m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=3; m2rfw0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfw0; }
:movem.w (d16)".w",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=0; m2rfw0; d16 { movemptr = d16; build m2rfw0; }
:movem.w (d32)".l",m2rfw0 is opbig=0x4c & op67=2 & mode=7 & regan=1; m2rfw0; d32 { movemptr = d32; build m2rfw0; }
:movem.l (regan),m2rfl0 is opbig=0x4c & op67=3 & mode=2 & regan; m2rfl0 { movemptr = regan; build m2rfl0; }
:movem.l (regan)+,m2rfl0 is opbig=0x4c & op67=3 & mode=3 & regan; m2rfl0 { movemptr = regan; build m2rfl0; regan = movemptr; }
:movem.l (d16,regan),m2rfl0 is opbig=0x4c & op67=3 & mode=5 & regan; m2rfl0; d16 { movemptr = regan+d16; build m2rfl0; }
:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=6 & regan; m2rfl0; extw [ pcmode=0; regtfan=regan; ] { build extw; movemptr = extw; build m2rfl0; }
:movem.l (d16,PC),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=2; m2rfl0; d16 & PC { movemptr = inst_start+4+d16; build m2rfl0; }
:movem.l (extw),m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=3; m2rfl0; extw [ pcmode=1; ] { build extw; movemptr = extw; build m2rfl0; }
:movem.l (d16)".w",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=0; m2rfl0; d16 { movemptr = d16; build m2rfl0; }
:movem.l (d32)".l",m2rfl0 is opbig=0x4c & op67=3 & mode=7 & regan=1; m2rfl0; d32 { movemptr = d32; build m2rfl0; }
:movep.w (d16,regan),reg9dnw is op=0 & reg9dnw & op68=4 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); } :movem.l r2mfl0, movemOp is (opbig=0x48 & op67=3; r2mfl0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mfl0; }
:movep.l (d16,regan),reg9dn is op=0 & reg9dn & op68=5 & op35=1 & regan; d16 { src:4 = (regan + d16); ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); } :movem.l r2mbl0, movemOp is (opbig=0x48 & op67=3 & mode=4 & movemWrt; r2mbl0) ... & movemOp { build movemOp; movemptr = movemOp; build r2mbl0; build movemWrt; }
:movep.w reg9dnw,(d16,regan) is op=0 & reg9dnw & op68=6 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; }
:movep.l reg9dn,(d16,regan) is op=0 & reg9dn & op68=7 & op35=1 & regan; d16 { src:4 = (regan + d16); local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; } :movem.w movemOp, m2rfw0 is (opbig=0x4c & op67=2 & movemWrt; m2rfw0) ... & movemOp { build movemOp; movemptr = movemOp; build m2rfw0; build movemWrt; }
:movem.l movemOp, m2rfl0 is (opbig=0x4c & op67=3 & movemWrt; m2rfl0) ... & movemOp { build movemOp; movemptr = movemOp; build m2rfl0; build movemWrt; }
:moveq "#"^d8base,reg9dn is op=7 & reg9dn & op8=0 & d8base { reg9dn = d8base; resflags(reg9dn); logflags(); } epw: (d16, regan) is regan; d16 { local tmp = regan + d16; export tmp; }
:movep.w epw,reg9dnw is (op=0 & reg9dnw & op68=4 & op35=1) ... & epw { src:4 = epw; ho:1 = *:1 src; lo:1 = *:1(src+2); reg9dnw = (zext(ho) << 8) | zext(lo); }
:movep.l epw,reg9dn is (op=0 & reg9dn & op68=5 & op35=1) ... & epw { src:4 = epw; ho:1 = *:1 src; mu:1 = *:1(src+2); ml:1 = *(src+4); lo:1 = *:1(src+6); reg9dn = (zext(ho) << 24) | (zext(mu) << 16) | (zext(ml) << 8) | zext(lo); }
:movep.w reg9dnw,epw is (op=0 & reg9dnw & op68=6 & op35=1) ... & epw { src:4 = epw; local tmp = (reg9dnw >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dnw:1; }
:movep.l reg9dn,epw is (op=0 & reg9dn & op68=7 & op35=1)... & epw { src:4 = epw; local tmp = (reg9dn >> 24); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 16); *:1 src = tmp:1; src = src+2; tmp = (reg9dn >> 8); *:1 src = tmp:1; src = src+2; *:1 src = reg9dn:1; }
:moveq d8base,reg9dn is op=7 & reg9dn & op8=0 & d8base { reg9dn = d8base; resflags(reg9dn); logflags(); }
:moves.b rreg,e2b is opbig=0x0e & op67=0 & mode & regan; rreg & wl=1; e2b [ regtsan=regan; savmod2=mode; ] { e2b = rreg:1; } :moves.b rreg,e2b is opbig=0x0e & op67=0 & mode & regan; rreg & wl=1; e2b [ regtsan=regan; savmod2=mode; ] { e2b = rreg:1; }
:moves.w rreg,e2w is opbig=0x0e & op67=1 & mode & regan; rreg & wl=1; e2w [ regtsan=regan; savmod2=mode; ] { e2w = rreg:2; } :moves.w rreg,e2w is opbig=0x0e & op67=1 & mode & regan; rreg & wl=1; e2w [ regtsan=regan; savmod2=mode; ] { e2w = rreg:2; }
@@ -2035,8 +2075,8 @@ macro negResFlags(result) {
@ifdef MC68040 @ifdef MC68040
:pflushn "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=0 & regan unimpl :pflushn regPlus is opbig=0xf5 & op67=0 & op5=0 & op34=0 & regPlus unimpl
:pflush "("^regan^")" is opbig=0xf5 & op67=0 & op5=0 & op34=1 & regan unimpl :pflush regPlus is opbig=0xf5 & op67=0 & op5=0 & op34=1 & regPlus unimpl
:pflushan is opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0 unimpl :pflushan is opbig=0xf5 & op67=0 & op5=0 & op34=2 & regan=0 unimpl
:pflusha is opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0 unimpl :pflusha is opbig=0xf5 & op67=0 & op5=0 & op34=3 & regan=0 unimpl
@@ -2121,8 +2161,8 @@ ptestLevel: "#"^mregn is mregn { export *[const]:1 mregn; }
@ifdef MC68040 @ifdef MC68040
:ptestr "("^regan^")" is opbig=0xf5 & op67=1 & op35=5 & regan unimpl :ptestr regPlus is opbig=0xf5 & op67=1 & op35=5 & regPlus unimpl
:ptestw "("^regan^")" is opbig=0xf5 & op67=1 & op35=1 & regan unimpl :ptestw regPlus is opbig=0xf5 & op67=1 & op35=1 & regPlus unimpl
@endif # MC68040 @endif # MC68040
@@ -2362,7 +2402,6 @@ f_mem: e2x is ffmt=2; e2x { tmp:10 = float2float(e2x); export tmp; }
f_mem: e2x is ffmt=3; e2x { tmp:10 = float2float(e2x); export tmp; } f_mem: e2x is ffmt=3; e2x { tmp:10 = float2float(e2x); export tmp; }
f_mem: e2d is ffmt=5; e2d { tmp:10 = float2float(e2d); export tmp; } f_mem: e2d is ffmt=5; e2d { tmp:10 = float2float(e2d); export tmp; }
:fabs.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x18) ... & f_mem :fabs.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x18) ... & f_mem
[ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); } [ savmod2=savmod1; regtsan=regtfan; ] { fdst = abs(f_mem); }
@@ -2493,7 +2532,6 @@ fdivrnd: "d" is fdst & fopmode=0x64 { tmp:8 = float2float(fdst); fdst = float2f
[ savmod2=savmod1; regtsan=regtfan; ] { fdst = fmod(f_mem); } [ savmod2=savmod1; regtsan=regtfan; ] { fdst = fmod(f_mem); }
:fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 { fdst = fmod(fsrc); } :fmod fsrc, fdst is op=15 & $(FP_COP) & op68=0 & mode=0 & regan=0; frm=0 & f1515=0 & f1313=0 & fsrc & fdst & fopmode=0x21 { fdst = fmod(fsrc); }
:fmove.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x00) ... & f_mem :fmove.^fprec f_mem, fdst is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); (frm=1 & f1515=0 & f1313=0 & fdst & fprec & fopmode=0x00) ... & f_mem
[ savmod2=savmod1; regtsan=regtfan; ] { fdst = f_mem; resflags_fp(fdst); } [ savmod2=savmod1; regtsan=regtfan; ] { fdst = f_mem; resflags_fp(fdst); }
@@ -2536,11 +2574,14 @@ fmovernd: "d" is fdst & fopmode=0x44 { tmp:8 = float2fl
:fmove.^fprec fdst, e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d :fmove.^fprec fdst, e2d is op=15 & $(FP_COP) & op68=0 & $(MEM_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_D); e2d
[ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); } [ savmod2=savmod1; regtsan=regtfan; ] { e2d = float2float(fdst); resflags_fp(e2d); }
:fmove.p fdst, e2l {"#"fkfactor} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfactor & $(FPREC_P); e2l kfact: {"#"fkfactor} is fkfactor & $(FPREC_P) { local tmp:4 = fkfactor; export *[const]:4 tmp; }
[ savmod2=savmod1; regtsan=regtfan; ] { kfact:4 = fkfactor; e2l = kfactor(fdst, kfact); } kfact: {fkfacreg} is fkfacreg & $(FPREC_Pd) { export fkfacreg; }
:fmove.p fdst, e2l {fkfacreg} is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & fkfacreg & $(FPREC_Pd); e2l :fmove.p fdst, e2l kfact is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & kfact & $(FPREC_P); e2l
[ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, fkfacreg); } [ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, kfact); }
:fmove.p fdst, e2l kfact is op=15 & $(FP_COP) & op68=0 & $(DAT_ALTER_ADDR_MODES); frm=1 & f1315=3 & fdst & kfact & $(FPREC_Pd); e2l
[ savmod2=savmod1; regtsan=regtfan; ] { e2l = kfactor(fdst, kfact); }
#Special case for FMOVEM.L and must occur before it within this file #Special case for FMOVEM.L and must occur before it within this file
:fmove.l e2l, FPCR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=0 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPCR = e2l; } :fmove.l e2l, FPCR is op=15 & $(FP_COP) & $(DAT_ALTER_ADDR_MODES) & op68=0 & FPCR; f1415=2 & fdr=0 & f1012=4 & f0009=0; e2l [ savmod2=savmod1; regtsan=regtfan; ] { FPCR = e2l; }
@@ -3019,6 +3060,7 @@ moveaccreg2: ACC3 is ACC3 & op01=3 { export ACC3; }
accreg = accreg - tmp; accreg = accreg - tmp;
accw = accw + tmp; accw = accw + tmp;
} }
:msaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ... :msaac.l reg03y, reg9an^scalefactor, accreg, accw is (op=10 & reg9an & reg03y & op6=1 & op8=0 & op45=0 ; fbit=1 & wl=1 & scalefactor & accw & odsize=1) ... & accreg ...
{ {
local tmp = reg03y * reg9an; local tmp = reg03y * reg9an;