diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
index f3d4a42f78..fa321fc2b2 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
@@ -541,7 +541,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 }
 
 :se_btsti RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {
-	tmp:$(REGISTER_SIZE) = (RX_VLE >> OIM5_VLE) & 0x1;
+	tmp:$(REGISTER_SIZE) = (RX_VLE >> (0x1F - OIM5_VLE)) & 0x1;
 	cr0flags(tmp);
 }
 
@@ -709,13 +709,13 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 }
 
 :se_bclri RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {
-	tmp:$(REGISTER_SIZE) = 1 << OIM5_VLE;
+	tmp:$(REGISTER_SIZE) =  0x80000000 >> OIM5_VLE;
 	tmp = ~tmp;
 	RX_VLE = RX_VLE & tmp;
 }
 
 :se_bgeni RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {
-	RX_VLE = 1 << OIM5_VLE;
+	RX_VLE = 0x80000000 >> OIM5_VLE;
 }
 
 :se_bmaski RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=11 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {
@@ -725,7 +725,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 }
 
 :se_bseti RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {
-	tmp:$(REGISTER_SIZE) = 1 << OIM5_VLE;
+	tmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE;
 	RX_VLE = RX_VLE | tmp;	
 }
 
diff --git a/Ghidra/Processors/x86/data/languages/rdrand.sinc b/Ghidra/Processors/x86/data/languages/rdrand.sinc
index ceaf72d55d..8432b8f0fa 100644
--- a/Ghidra/Processors/x86/data/languages/rdrand.sinc
+++ b/Ghidra/Processors/x86/data/languages/rdrand.sinc
@@ -1,6 +1,6 @@
 define pcodeop rdrand;
 define pcodeop rdrandIsValid;
-:RDRAND r16     is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; r16 & reg_opcode=6 { r16 = rdrand(); CF=rdrandIsValid(); }
-:RDRAND r32     is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; r32 & reg_opcode=6 { r32 = rdrand(); CF=rdrandIsValid(); }
-:RDRAND r64     is vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; r64 & reg_opcode=6 { r64 = rdrand(); CF=rdrandIsValid(); }
+:RDRAND rm16     is vexMode=0 & opsize=0 & byte=0x0f; byte=0xC7; (rm16 & reg_opcode=6 ...) { rm16 = rdrand(); CF=rdrandIsValid(); }
+:RDRAND rm32     is vexMode=0 & opsize=1 & byte=0x0f; byte=0xC7; (rm32 & reg_opcode=6 ...) { rm32 = rdrand(); CF=rdrandIsValid(); }
+:RDRAND rm64     is vexMode=0 & opsize=2 & $(REX_W) & byte=0x0f; byte=0xC7; (rm64 & reg_opcode=6 ...) { rm64 = rdrand(); CF=rdrandIsValid(); }