mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-05-24 03:09:36 +08:00
Merge remote-tracking branch 'origin/GT-3523_emteere_PR-1430_Aleckaj_master'
This commit is contained in:
emteere
@@ -0,0 +1,7 @@
|
||||
apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
|
||||
apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
|
||||
apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
|
||||
apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
|
||||
apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
|
||||
apply plugin: 'eclipse'
|
||||
eclipse.project.name = 'Processors v850'
|
||||
@@ -0,0 +1,22 @@
|
||||
##VERSION: 2.0
|
||||
Module.manifest||GHIDRA||||END|
|
||||
build.gradle||GHIDRA||||END|
|
||||
data/languages/Helpers/Conditions.sinc||GHIDRA||||END|
|
||||
data/languages/Helpers/Extras.sinc||GHIDRA||||END|
|
||||
data/languages/Helpers/Macros.sinc||GHIDRA||||END|
|
||||
data/languages/Helpers/Register.sinc||GHIDRA||||END|
|
||||
data/languages/Helpers/Tokens.sinc||GHIDRA||||END|
|
||||
data/languages/Helpers/Variables.sinc||GHIDRA||||END|
|
||||
data/languages/Instructions/Arithmetic.sinc||GHIDRA||||END|
|
||||
data/languages/Instructions/Float.sinc||GHIDRA||||END|
|
||||
data/languages/Instructions/Load_Store.sinc||GHIDRA||||END|
|
||||
data/languages/Instructions/Logic.sinc||GHIDRA||||END|
|
||||
data/languages/Instructions/Special.sinc||GHIDRA||||END|
|
||||
data/languages/V850.cspec||GHIDRA||||END|
|
||||
data/languages/V850.ldefs||GHIDRA||||END|
|
||||
data/languages/V850.opinion||GHIDRA||||END|
|
||||
data/languages/V850.pspec||GHIDRA||||END|
|
||||
data/languages/V850.slaspec||GHIDRA||||END|
|
||||
data/manuals/v850.idx||GHIDRA||||END|
|
||||
data/patterns/V850_patterns.xml||GHIDRA||||END|
|
||||
data/patterns/patternconstraints.xml||GHIDRA||||END|
|
||||
@@ -0,0 +1,38 @@
|
||||
#####################################################
|
||||
##### Conditions #####
|
||||
#####################################################
|
||||
|
||||
|
||||
c0003: "v" is op0003=0x0 { tmp:1 = ($(OV)) == 1; export tmp; }
|
||||
c0003: "nv" is op0003=0x8 { tmp:1 = ($(OV)) == 0; export tmp; }
|
||||
c0003: "c" is op0003=0x1 { tmp:1 = ($(CY)) == 1; export tmp; }
|
||||
c0003: "nc" is op0003=0x9 { tmp:1 = ($(CY)) == 0; export tmp; }
|
||||
c0003: "e" is op0003=0x2 { tmp:1 = ($(Z)) == 1; export tmp; }
|
||||
c0003: "ne" is op0003=0xA { tmp:1 = ($(Z)) == 0; export tmp; }
|
||||
c0003: "nh" is op0003=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; }
|
||||
c0003: "h" is op0003=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; }
|
||||
c0003: "n" is op0003=0x4 { tmp:1 = ($(S)) == 1; export tmp; }
|
||||
c0003: "p" is op0003=0xC { tmp:1 = ($(S)) == 0; export tmp; }
|
||||
c0003: "t" is op0003=0x5 { tmp:1 = 1; export tmp; }
|
||||
c0003: "sa" is op0003=0xD { tmp:1 = ($(SAT)) == 1; export tmp; }
|
||||
c0003: "lt" is op0003=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; }
|
||||
c0003: "ge" is op0003=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; }
|
||||
c0003: "le" is op0003=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }
|
||||
c0003: "gt" is op0003=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }
|
||||
|
||||
c1720: "v" is op1720=0x0 { tmp:1 = ($(OV)) == 1; export tmp; }
|
||||
c1720: "nv" is op1720=0x8 { tmp:1 = ($(OV)) == 0; export tmp; }
|
||||
c1720: "c" is op1720=0x1 { tmp:1 = ($(CY)) == 1; export tmp; }
|
||||
c1720: "nc" is op1720=0x9 { tmp:1 = ($(CY)) == 0; export tmp; }
|
||||
c1720: "e" is op1720=0x2 { tmp:1 = ($(Z)) == 1; export tmp; }
|
||||
c1720: "ne" is op1720=0xA { tmp:1 = ($(Z)) == 0; export tmp; }
|
||||
c1720: "nh" is op1720=0x3 { tmp:1 = ($(CY) || $(Z)) == 1; export tmp; }
|
||||
c1720: "h" is op1720=0xB { tmp:1 = ($(CY) || $(Z)) == 0; export tmp; }
|
||||
c1720: "n" is op1720=0x4 { tmp:1 = ($(S)) == 1; export tmp; }
|
||||
c1720: "p" is op1720=0xC { tmp:1 = ($(S)) == 0; export tmp; }
|
||||
c1720: "t" is op1720=0x5 { tmp:1 = 1; export tmp; }
|
||||
c1720: "sa" is op1720=0xD { tmp:1 = ($(SAT)) == 1; export tmp; }
|
||||
c1720: "lt" is op1720=0x6 { tmp:1 = ($(S) ^^ $(OV)) == 1; export tmp; }
|
||||
c1720: "ge" is op1720=0xE { tmp:1 = ($(S) ^^ $(OV)) == 0; export tmp; }
|
||||
c1720: "le" is op1720=0x7 { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 1; export tmp; }
|
||||
c1720: "gt" is op1720=0xF { tmp:1 = ($(S) ^^ $(OV) || $(Z)) == 0; export tmp; }
|
||||
@@ -0,0 +1,125 @@
|
||||
#####################################################
|
||||
##### Extras #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# read r0 always return zero
|
||||
R0004: _R0004 is _R0004 & _R0004=0 { local x:4=0; export x; }
|
||||
R0004: _R0004 is _R0004 { export _R0004; }
|
||||
|
||||
R1115: _R1115 is _R1115 & _R1115=0 { local x:4=0; export x; }
|
||||
R1115: _R1115 is _R1115 { export _R1115; }
|
||||
|
||||
R2731: _R2731 is _R2731 & _R2731=0 { local x:4=0; export x; }
|
||||
R2731: _R2731 is _R2731 { export _R2731; }
|
||||
|
||||
|
||||
adr9: res is op0406 & s1115
|
||||
[ res = ((s1115 << 4) | (op0406 << 1)) + inst_start; ]
|
||||
{
|
||||
export *:4 res;
|
||||
}
|
||||
|
||||
adr22: res is s0005; op1631 & op1616=0
|
||||
[ res = ((s0005 << 16) | op1631) + inst_start; ]
|
||||
{
|
||||
export *:4 res;
|
||||
}
|
||||
|
||||
adr32: res is op1631 & op1616=0; op3247
|
||||
[ res = ((op3247 << 16) | op1631) + inst_start; ]
|
||||
{
|
||||
export *:4 res;
|
||||
}
|
||||
|
||||
reg4: op0_1720 is op2323=0 & op0_1720 { export op0_1720; }
|
||||
reg4: op1_1720 is op2323=1 & op1_1720 { export op1_1720; }
|
||||
|
||||
|
||||
|
||||
##### Prep/Disp Loop #####
|
||||
|
||||
PrepList20: r20 is prep27=1 & r20 { push(r20); }
|
||||
PrepList20: is prep27=0 { }
|
||||
|
||||
PrepList21: r21 is prep26=1 & prep27=0 & r21 { push(r21); }
|
||||
PrepList21: PrepList20,r21 is prep26=1 & PrepList20 & r21 { push(r21); }
|
||||
PrepList21: PrepList20 is prep26=0 & PrepList20 { }
|
||||
|
||||
PrepList22: r22 is prep25=1 & prep2627=0 & r22 { push(r22); }
|
||||
PrepList22: PrepList21,r22 is prep25=1 & PrepList21 & r22 { push(r22); }
|
||||
PrepList22: PrepList21 is prep25=0 & PrepList21 { }
|
||||
|
||||
PrepList23: r23 is prep24=1 & prep2527=0 & r23 { push(r23); }
|
||||
PrepList23: PrepList22,r23 is prep24=1 & PrepList22 & r23 { push(r23); }
|
||||
PrepList23: PrepList22 is prep24=0 & PrepList22 { }
|
||||
|
||||
PrepList24: r24 is prep31=1 & prep2427=0 & r24 { push(r24); }
|
||||
PrepList24: PrepList23,r24 is prep31=1 & PrepList23 & r24 { push(r24); }
|
||||
PrepList24: PrepList23 is prep31=0 & PrepList23 { }
|
||||
|
||||
PrepList25: r25 is prep30=1 & prep2427=0 & prep31=0 & r25 { push(r25); }
|
||||
PrepList25: PrepList24,r25 is prep30=1 & PrepList24 & r25 { push(r25); }
|
||||
PrepList25: PrepList24 is prep30=0 & PrepList24 { }
|
||||
|
||||
PrepList26: r26 is prep29=1 & prep2427=0 & prep3031=0 & r26 { push(r26); }
|
||||
PrepList26: PrepList25,r26 is prep29=1 & PrepList25 & r26 { push(r26); }
|
||||
PrepList26: PrepList25 is prep29=0 & PrepList25 { }
|
||||
|
||||
PrepList27: r27 is prep28=1 & prep2427=0 & prep2931=0 & r27 { push(r27); }
|
||||
PrepList27: PrepList26,r27 is prep28=1 & PrepList26 & r27 { push(r27); }
|
||||
PrepList27: PrepList26 is prep28=0 & PrepList26 { }
|
||||
|
||||
PrepList28: r28 is prep23=1 & prep2431=0 & r28 { push(r28); }
|
||||
PrepList28: PrepList27,r28 is prep23=1 & PrepList27 & r28 { push(r28); }
|
||||
PrepList28: PrepList27 is prep23=0 & PrepList27 { }
|
||||
|
||||
PrepList29: r29 is prep22=1 & prep2431=0 & prep23=0 & r29 { push(r29); }
|
||||
PrepList29: PrepList28,r29 is prep22=1 & PrepList28 & r29 { push(r29); }
|
||||
PrepList29: PrepList28 is prep22=0 & PrepList28 { }
|
||||
|
||||
PrepList30: ep is prep00=1 & prep2431=0 & prep2223=0 & ep { push(ep); }
|
||||
PrepList30: PrepList29,ep is prep00=1 & PrepList29 & ep { push(ep); }
|
||||
PrepList30: PrepList29 is prep00=0 & PrepList29 { }
|
||||
|
||||
PrepList: { lp } is prep21=1 & prep2431=0 & prep2223=0 & prep00=0 & lp { push(lp); }
|
||||
PrepList: { PrepList30,lp } is prep21=1 & PrepList30 & lp { push(lp); }
|
||||
PrepList: { PrepList30 } is prep21=0 & PrepList30 { }
|
||||
|
||||
|
||||
|
||||
DispList31: lp is prep21=1 & lp { pop(lp); }
|
||||
DispList31: is prep21=0 { }
|
||||
|
||||
DispList30: ep,DispList31 is DispList31 & prep00=1 & ep { pop(ep); }
|
||||
DispList30: DispList31 is DispList31 & prep00=0 { }
|
||||
|
||||
DispList29: r29,DispList30 is DispList30 & prep22=1 & r29 { pop(r29); }
|
||||
DispList29: DispList30 is DispList30 & prep22=0 { }
|
||||
|
||||
DispList28: r28,DispList29 is DispList29 & prep23=1 & r28 { pop(r28); }
|
||||
DispList28: DispList29 is DispList29 & prep23=0 { }
|
||||
|
||||
DispList27: r27,DispList28 is DispList28 & prep28=1 & r27 { pop(r27); }
|
||||
DispList27: DispList28 is DispList28 & prep28=0 { }
|
||||
|
||||
DispList26: r26,DispList27 is DispList27 & prep29=1 & r26 { pop(r26); }
|
||||
DispList26: DispList27 is DispList27 & prep29=0 { }
|
||||
|
||||
DispList25: r25,DispList26 is DispList26 & prep30=1 & r25 { pop(r25); }
|
||||
DispList25: DispList26 is DispList26 & prep30=0 { }
|
||||
|
||||
DispList24: r24,DispList25 is DispList25 & prep31=1 & r24 { pop(r24); }
|
||||
DispList24: DispList25 is DispList25 & prep31=0 { }
|
||||
|
||||
DispList23: r23,DispList24 is DispList24 & prep24=1 & r23 { pop(r23); }
|
||||
DispList23: DispList24 is DispList24 & prep24=0 { }
|
||||
|
||||
DispList22: r22,DispList23 is DispList23 & prep25=1 & r22 { pop(r22); }
|
||||
DispList22: DispList23 is DispList23 & prep25=0 { }
|
||||
|
||||
DispList21: r21,DispList22 is DispList22 & prep26=1 & r21 { pop(r21); }
|
||||
DispList21: DispList22 is DispList22 & prep26=0 { }
|
||||
|
||||
DispList: { r20,DispList21 } is DispList21 & prep27=1 & r20 { pop(r20); }
|
||||
DispList: { DispList21 } is DispList21 & prep27=0 { }
|
||||
@@ -0,0 +1,252 @@
|
||||
#####################################################
|
||||
##### Macros #####
|
||||
#####################################################
|
||||
|
||||
|
||||
##### CARRY-Flag #####
|
||||
|
||||
macro set_CY_pos(var1, var2)
|
||||
{
|
||||
$(CY) = carry(var1, var2);
|
||||
}
|
||||
|
||||
macro set_CY_pos2(var1, var2, var3)
|
||||
{
|
||||
local var12 = var1 + var2;
|
||||
$(CY) = carry(var1, var2) || carry(var12, var3);
|
||||
}
|
||||
|
||||
macro set_CY_neg(var1, var2)
|
||||
{
|
||||
$(CY) = var1 < var2;
|
||||
}
|
||||
|
||||
macro set_CY_neg2(var1, var2, var3)
|
||||
{
|
||||
local var23 = var2 + var3;
|
||||
$(CY) = (var1 < var23);
|
||||
}
|
||||
|
||||
|
||||
|
||||
##### Overflow-Flag #####
|
||||
|
||||
macro set_OV_pos(var1, var2)
|
||||
{
|
||||
$(OV) = scarry(var1, var2);
|
||||
}
|
||||
|
||||
macro set_OV_pos2(var1, var2, var3)
|
||||
{
|
||||
local var12 = var1 + var2;
|
||||
$(OV) = scarry(var1, var2) || scarry(var12, var3);
|
||||
}
|
||||
|
||||
macro set_OV_neg(var1, var2)
|
||||
{
|
||||
local A:4 = var1;
|
||||
local B:4 = var2;
|
||||
local R = A - B;
|
||||
|
||||
local A1 = A[31,1];
|
||||
local B1 = B[31,1];
|
||||
local R1 = R[31,1];
|
||||
|
||||
$(OV) = (A1 != B1) && (B1 == R1);
|
||||
|
||||
#OV = 1 if:
|
||||
#pos - neg = neg
|
||||
#neg - pos = pos
|
||||
}
|
||||
|
||||
macro set_OV_neg2(var1, var2, var3)
|
||||
{
|
||||
local A:4 = var1;
|
||||
local B:4 = var2;
|
||||
local C:4 = var3;
|
||||
local R = A - B - C;
|
||||
|
||||
local A1 = A[31,1];
|
||||
local B1 = B[31,1];
|
||||
local R1 = R[31,1];
|
||||
|
||||
$(OV) = (A1 != B1) && (B1 == R1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
##### S/Z-Flags #####
|
||||
|
||||
macro set_S(flag)
|
||||
{
|
||||
$(S) = flag s< 0;
|
||||
}
|
||||
|
||||
macro set_Z(var)
|
||||
{
|
||||
$(Z) = var == 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
##### General-Flag-Macros #####
|
||||
|
||||
macro set_general_flags_pos(var1, var2)
|
||||
{
|
||||
local res = var1 + var2;
|
||||
set_CY_pos(var1, var2);
|
||||
set_OV_pos(var1, var2);
|
||||
set_S(res);
|
||||
set_Z(res);
|
||||
}
|
||||
|
||||
macro set_general_flags_neg(var1, var2)
|
||||
{
|
||||
local res = var1 - var2;
|
||||
set_CY_neg(var1, var2);
|
||||
set_OV_neg(var1, var2);
|
||||
set_S(res);
|
||||
set_Z(res);
|
||||
}
|
||||
|
||||
macro set_OV0_S_Z(var)
|
||||
{
|
||||
$(OV) = 0;
|
||||
set_S(var);
|
||||
set_Z(var);
|
||||
}
|
||||
|
||||
|
||||
|
||||
##### General-Macros #####
|
||||
|
||||
macro either_or(res, cond, true, false) # if condition is != 0
|
||||
{
|
||||
res = (true * zext(cond != 0)) + (false * zext(cond == 0));
|
||||
}
|
||||
|
||||
macro either_or1(res, cond, true, false) # if condition is == 1
|
||||
{
|
||||
res = (true * zext(cond == 1)) + (false * zext(cond != 1));
|
||||
}
|
||||
|
||||
macro shift_right_logic(res, var, shift_)
|
||||
{
|
||||
local shift = shift_ & 0x1f;
|
||||
local mask = (zext(shift != 0) * var) & (1 << (shift - 1));
|
||||
res = var >> shift;
|
||||
set_OV0_S_Z(res);
|
||||
$(CY) = ((mask != 0) && (shift != 0));
|
||||
}
|
||||
|
||||
macro shift_right_arith(res, var, shift_)
|
||||
{
|
||||
local shift = shift_ & 0x1f;
|
||||
local mask = (zext(shift != 0) * var) & (1 << (shift - 1));
|
||||
res = var s>> shift;
|
||||
set_OV0_S_Z(res);
|
||||
$(CY) = ((mask != 0) && (shift != 0));
|
||||
}
|
||||
|
||||
macro shift_left_logic(res, var, shift_)
|
||||
{
|
||||
local shift = shift_ & 0x1f;
|
||||
local mask = (zext(shift != 0) * var) & (1 << (32 - shift));
|
||||
res = var << shift;
|
||||
set_OV0_S_Z(res);
|
||||
$(CY) = ((mask != 0) && (shift != 0));
|
||||
}
|
||||
|
||||
|
||||
|
||||
##### Prep/Disp Macros #####
|
||||
|
||||
macro push(reg)
|
||||
{
|
||||
sp = sp - 4;
|
||||
*:4 sp = reg;
|
||||
}
|
||||
|
||||
macro pop(reg)
|
||||
{
|
||||
reg = *:4 sp;
|
||||
sp = sp + 4;
|
||||
}
|
||||
|
||||
|
||||
|
||||
##### Search Macros #####
|
||||
|
||||
macro SearchRight(res, var, char)
|
||||
{
|
||||
local var_:4 = var;
|
||||
res = 0;
|
||||
|
||||
<loop>
|
||||
if ((var_ & 0x1) == char)
|
||||
goto <end>;
|
||||
|
||||
var_ = var_ >> 1;
|
||||
res = res + 1;
|
||||
|
||||
if (res < 32)
|
||||
goto <loop>;
|
||||
|
||||
res = 0;
|
||||
|
||||
<end>
|
||||
}
|
||||
|
||||
macro SearchLeft(res, var, char)
|
||||
{
|
||||
local var_:4 = var;
|
||||
res = 0;
|
||||
|
||||
<loop>
|
||||
if ((var_ >> 31) == char)
|
||||
goto <end>;
|
||||
|
||||
var_ = var_ << 1;
|
||||
res = res + 1;
|
||||
|
||||
if (res < 32)
|
||||
goto <loop>;
|
||||
|
||||
res = 0;
|
||||
|
||||
<end>
|
||||
}
|
||||
|
||||
# macro saturate(var)
|
||||
# {
|
||||
# if (var s> 0x7FFFFFFF)
|
||||
# goto <pos_sat>;
|
||||
|
||||
# if (var s< -0x80000000)
|
||||
# goto <neg_sat>;
|
||||
|
||||
# goto <end>;
|
||||
|
||||
# <pos_sat>
|
||||
# var = 0x7FFFFFFF;
|
||||
# goto <end>;
|
||||
|
||||
# <neg_sat>
|
||||
# var = -0x80000000;
|
||||
# goto <end>;
|
||||
|
||||
# <end>
|
||||
# }
|
||||
|
||||
|
||||
##### Float-Macros #####
|
||||
|
||||
macro compare_float(res, fcond, reg1, reg2)
|
||||
{
|
||||
local un = ((fcond & 1) == 1) & (nan(reg2) || nan(reg1));
|
||||
local eq = ((fcond & 2) == 2) & (!(nan(reg2) || nan(reg1))) & (reg2 f== reg1);
|
||||
local le = ((fcond & 4) == 4) & (!(nan(reg2) || nan(reg1))) & (reg2 f< reg1);
|
||||
#local ex = (fcond & 8) & ((nan(reg2) || nan(reg1)));
|
||||
|
||||
res = zext(un|eq|le);
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
#####################################################
|
||||
##### Register #####
|
||||
#####################################################
|
||||
|
||||
|
||||
##### General-purpose registers (r0 to r31) #####
|
||||
|
||||
define register offset=0x0 size=0x4 # offset = 0 because it's the start
|
||||
[
|
||||
r0 r1 r2 sp gp tp r6 r7 r8 r9
|
||||
r10 r11 r12 r13 r14 r15 r16 r17 r18 r19
|
||||
r20 r21 r22 r23 r24 r25 r26 r27 r28 r29
|
||||
ep lp
|
||||
];
|
||||
|
||||
|
||||
|
||||
##### Control/Special registers #####
|
||||
|
||||
define register offset=0x80 size=0x4 # offset = 0x80(128) = PreOffset+PreRegister*Size = 0+32*4 = 128
|
||||
[
|
||||
EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC
|
||||
FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW
|
||||
CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR
|
||||
DBWR BSEL
|
||||
];
|
||||
|
||||
define register offset=0x0 size=0x8
|
||||
[
|
||||
r0r1 r2sp r4r5 r6r7 r8r9
|
||||
r10r11 r12r13 r14r15 r16r17 r18r19
|
||||
r20r21 r22r23 r24r25 r26r27 r28r29
|
||||
_
|
||||
];
|
||||
|
||||
define register offset=0x100 size=0x4 [ PC ]; # offset = 0x100(256) = PreOffset+PreRegister*Size = 128+32*4 = 256
|
||||
@@ -0,0 +1,105 @@
|
||||
#####################################################
|
||||
##### Tokens #####
|
||||
#####################################################
|
||||
|
||||
|
||||
define token instr(16)
|
||||
op0000 = (0,0)
|
||||
op0003 = (0,3)
|
||||
op0004 = (0,4)
|
||||
_R0004 = (0,4)
|
||||
SR0004 = (0,4)
|
||||
R0004x2 = (0,4)
|
||||
s0004 = (0,4) signed
|
||||
s0005 = (0,5) signed
|
||||
op0005 = (0,5)
|
||||
op0006 = (0,6)
|
||||
op0010 = (0,10)
|
||||
op0015 = (0,15)
|
||||
op0106 = (1,6)
|
||||
op0406 = (4,6)
|
||||
op0410 = (4,10)
|
||||
op0505 = (5,5)
|
||||
op0510 = (5,10)
|
||||
op0515 = (5,15)
|
||||
op0610 = (6,10)
|
||||
op0615 = (6,15)
|
||||
op0710 = (7,10)
|
||||
op1113 = (11,13)
|
||||
op1114 = (11,14)
|
||||
op1115 = (11,15)
|
||||
_R1115 = (11,15)
|
||||
SR1115 = (11,15)
|
||||
R1115x2 = (11,15)
|
||||
s1115 = (11,15) signed
|
||||
op1415 = (14,15)
|
||||
op1515 = (15,15)
|
||||
;
|
||||
|
||||
define token instr2(16)
|
||||
op1616 = (0,0)
|
||||
op1617 = (0,1)
|
||||
op1619 = (0,3)
|
||||
op1620 = (0,4)
|
||||
R1620 = (0,4)
|
||||
R1620x2 = (0,4)
|
||||
op1626 = (0,10)
|
||||
op1631 = (0,15)
|
||||
s1631 = (0,15) signed
|
||||
fcbit1719 = (1,3)
|
||||
op1720 = (1,4)
|
||||
op0_1720 = (1,4)
|
||||
op1_1720 = (1,4)
|
||||
s1731 = (1,15) signed
|
||||
op1821 = (2,5)
|
||||
s1821 = (2,5) signed
|
||||
op2020 = (4,4)
|
||||
op2026 = (4,10)
|
||||
op2122 = (5,6)
|
||||
op2126 = (5,10)
|
||||
op2226 = (6,10)
|
||||
op2323 = (7,7)
|
||||
op2426 = (8,10)
|
||||
op2729 = (11,13)
|
||||
fcond2730 = (11,14)
|
||||
op2731 = (11,15)
|
||||
_R2731 = (11,15)
|
||||
R2731x2 = (11,15)
|
||||
op3031 = (14,15)
|
||||
op3131 = (15,15)
|
||||
;
|
||||
|
||||
define token instr3(16)
|
||||
op3247 = (0,15)
|
||||
s3247 = (0,15) signed
|
||||
;
|
||||
|
||||
define token instr4(16)
|
||||
op4863 = (0,15)
|
||||
;
|
||||
|
||||
# used in PREPARE/DISPOSE instructions
|
||||
define token prep(32)
|
||||
prep00 = (0,0)
|
||||
prep0105 = (1,5)
|
||||
prep0615 = (6,15)
|
||||
prep1620 = (16,20)
|
||||
prep21 = (21,21)
|
||||
prep22 = (22,22)
|
||||
prep2223 = (22,31)
|
||||
prep23 = (23,23)
|
||||
prep24 = (24,24)
|
||||
prep2431 = (24,31)
|
||||
prep25 = (25,25)
|
||||
prep26 = (26,26)
|
||||
prep27 = (27,27)
|
||||
prep28 = (28,28)
|
||||
prep29 = (29,29)
|
||||
prep2931 = (29,31)
|
||||
prep3031 = (30,31)
|
||||
prep2427 = (24,27)
|
||||
prep2527 = (25,27)
|
||||
prep2627 = (26,27)
|
||||
prep30 = (30,30)
|
||||
prep31 = (31,31)
|
||||
;
|
||||
@@ -0,0 +1,49 @@
|
||||
#####################################################
|
||||
##### Variables #####
|
||||
#####################################################
|
||||
|
||||
|
||||
attach variables [ _R0004 _R1115 _R2731 R1620 prep1620]
|
||||
[
|
||||
r0 r1 r2 sp gp tp r6 r7 r8 r9
|
||||
r10 r11 r12 r13 r14 r15 r16 r17 r18 r19
|
||||
r20 r21 r22 r23 r24 r25 r26 r27 r28 r29
|
||||
ep lp
|
||||
];
|
||||
|
||||
attach variables [ R0004x2 R1115x2 R1620x2 R2731x2 ]
|
||||
[
|
||||
r0r1 _ r2sp _ r4r5 _ r6r7 _ r8r9 _
|
||||
r10r11 _ r12r13 _ r14r15 _ r16r17 _ r18r19 _
|
||||
r20r21 _ r22r23 _ r24r25 _ r26r27 _ r28r29 _
|
||||
_ _
|
||||
];
|
||||
|
||||
attach variables [ SR0004 SR1115 ]
|
||||
[
|
||||
EIPC EIPSW FEPC FEPSW ECR PSW FPSR FPEPC FPST FPCC
|
||||
FPCFG SCCFG SCBP EIIC FEIC DBIC CTPC CTPSW DBPC DBPSW
|
||||
CTBP DIR DBG22 DBG23 DBG24 DBG25 DBG26 DBG27 EIWR FEWR
|
||||
DBWR BSEL
|
||||
];
|
||||
|
||||
|
||||
attach variables [op0_1720] [r0 r2 gp r6 r8 r10 r12 r14 r16 r18 r20 r22 r24 r26 r28 ep];
|
||||
attach variables [op1_1720] [r1 sp tp r7 r9 r11 r13 r15 r17 r19 r21 r23 r25 r27 r29 lp];
|
||||
|
||||
|
||||
attach names [fcond2730]
|
||||
["f" "un" "eq" "ueq" "olt" "ult" "ole" "ule" "sd" "ngle" "seq" "ngl" "lt" "nge" "le" "ngt"];
|
||||
|
||||
|
||||
@define NP "PSW[7,1]"
|
||||
@define EP "PSW[6,1]"
|
||||
@define ID "PSW[5,1]"
|
||||
@define SAT "PSW[4,1]"
|
||||
@define CY "PSW[3,1]"
|
||||
@define OV "PSW[2,1]"
|
||||
@define S "PSW[1,1]"
|
||||
@define Z "PSW[0,1]"
|
||||
|
||||
@define EICC "ECR[0,16]"
|
||||
@define FECC "ECR[16,16]"
|
||||
@@ -0,0 +1,336 @@
|
||||
# (3) Multiply instructions
|
||||
# (4) Multiply-accumulate instructions
|
||||
# (5) Arithmetic instructions
|
||||
# (7) Saturated operation instructions
|
||||
# (11) Divide instructions
|
||||
# (12) High-speed divide instructions
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Multiply #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# MUL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100000
|
||||
:mul R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x220 & R2731
|
||||
{
|
||||
local res:8 = sext(R1115) * sext(R0004);
|
||||
R1115 = res:4;
|
||||
R2731 = res[32,32];
|
||||
}
|
||||
|
||||
# MUL imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII00
|
||||
:mul imm9, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2226=0x9 & op1617=0x0 & s1821 & R2731
|
||||
[ imm9 = (s1821 << 5) | s0004; ]
|
||||
{
|
||||
local res:8 = sext(R1115) * imm9;
|
||||
R1115 = res:4;
|
||||
R2731 = res[32,32];
|
||||
}
|
||||
|
||||
# MULH reg1, reg2 - rrrrr000111RRRRR
|
||||
:mulh R0004, R1115 is op0510=0x07 & R0004 & R1115 & op1115!=0
|
||||
{
|
||||
R1115 = sext(R1115:2) * sext(R0004:2);
|
||||
}
|
||||
|
||||
# MULH imm5, reg2 - rrrrr010111iiiii
|
||||
:mulh s0004, R1115 is op0510=0x17 & s0004 & R1115
|
||||
{
|
||||
R1115 = sext(R1115:2) * s0004;
|
||||
}
|
||||
|
||||
# MULHI imm16, reg1, reg2 - rrrrr110111RRRRR|iiiiiiiiiiiiiiii
|
||||
:mulhi s1631, R0004, R1115 is op0510=0x37 & R1115 & R0004; s1631
|
||||
{
|
||||
R1115 = R0004 * s1631;
|
||||
}
|
||||
|
||||
# MULU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01000100010
|
||||
:mulu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x222 & R2731
|
||||
{
|
||||
local res:8 = zext(R1115) * zext(R0004);
|
||||
R1115 = res:4;
|
||||
R2731 = res[32,32];
|
||||
}
|
||||
|
||||
# MULU imm9, reg2, reg3 - rrrrr111111iiiii|wwwww01001IIII10
|
||||
:mulu imm9, R1115, R2731 is op0510=0x3F & op0004 & R1115; op2226=0x9 & op1617=0x2 & op1821 & R2731
|
||||
[ imm9 = (op1821 << 5) | op0004; ]
|
||||
{
|
||||
local res:8 = zext(R1115) * imm9;
|
||||
R1115 = res:4;
|
||||
R2731 = res[32,32];
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### MultiplyAccumulate #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# MAC reg1, reg2, reg3, reg4 - rrrrr111111RRRRR wwww0011110mmmm0
|
||||
:mac R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1E & op1616=0 & R1620x2 & R2731x2
|
||||
{
|
||||
R1620x2 = sext(R1115) * sext(R0004) + R2731x2;
|
||||
}
|
||||
|
||||
# MACU reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwww0011111mmmm0
|
||||
:macu R0004, R1115, R2731x2, R1620x2 is op0510=0x3F & R0004 & R1115; op2126=0x1F & op1616=0 & R1620x2 & R2731x2
|
||||
{
|
||||
R1620x2 = zext(R1115) * zext(R0004) + R2731x2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Arithmetic #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# ADD reg1, reg2 - rrrrr001110RRRRR
|
||||
:add R0004, R1115 is op0510=0x0E & R0004 & R1115
|
||||
{
|
||||
set_general_flags_pos(R0004, R1115);
|
||||
R1115 = R1115 + R0004;
|
||||
}
|
||||
|
||||
# ADD imm5, reg2 - rrrrr010010iiiii
|
||||
:add s0004, R1115 is op0510=0x12 & s0004 & R1115
|
||||
{
|
||||
set_general_flags_pos(s0004, R1115);
|
||||
R1115 = R1115 + s0004;
|
||||
}
|
||||
|
||||
# ADDI imm16, reg1, reg2 - rrrrr110000RRRRR|iiiiiiiiiiiiiiii
|
||||
:addi s1631, R0004, R1115 is op0510=0x30 & R1115 & R0004; s1631
|
||||
{
|
||||
set_general_flags_pos(R0004, s1631);
|
||||
R1115 = R0004 + s1631;
|
||||
}
|
||||
|
||||
# CMP reg1, reg2 - rrrrr001111RRRRR
|
||||
:cmp R0004, R1115 is op0510=0x0F & R0004 & R1115
|
||||
{
|
||||
set_general_flags_neg(R1115, R0004);
|
||||
}
|
||||
|
||||
# CMP imm5, reg2 - rrrrr010011iiiii
|
||||
:cmp s0004, R1115 is op0510=0x13 & s0004 & R1115
|
||||
{
|
||||
set_general_flags_neg(R1115, s0004);
|
||||
}
|
||||
|
||||
# MOV reg1, reg2 - rrrrr000000RRRRR
|
||||
:mov R0004, R1115 is op0510=0x00 & R0004 & R1115
|
||||
{
|
||||
R1115 = R0004;
|
||||
}
|
||||
|
||||
# MOV imm5, reg2 - rrrrr010000iiiii
|
||||
:mov s0004, R1115 is op0510=0x10 & s0004 & R1115 & op1115!=0
|
||||
{
|
||||
R1115 = s0004;
|
||||
}
|
||||
|
||||
# MOV imm32, reg1 - 00000110001RRRRR|iiiiiiiiiiiiiiii|IIIIIIIIIIIIIIII
|
||||
:mov imm32, R0004 is op0515=0x031 & R0004; op1631; op3247
|
||||
[ imm32 = (op3247 << 16) | op1631; ]
|
||||
{
|
||||
R0004 = imm32;
|
||||
}
|
||||
|
||||
# MOVEA imm16, reg1, reg2 - rrrrr110001RRRRR|iiiiiiiiiiiiiiii
|
||||
:movea s1631, R0004, R1115 is op0510=0x31 & op1115!=0 & R0004 & R1115; s1631
|
||||
{
|
||||
R1115 = R0004 + s1631;
|
||||
}
|
||||
|
||||
# MOVHI imm16, reg1, reg2 - rrrrr110010RRRRR|iiiiiiiiiiiiiiii
|
||||
:movhi s1631, R0004, R1115 is op0510=0x32 & op1115!=0 & R0004 & R1115; s1631
|
||||
{
|
||||
R1115 = R0004 + (s1631 << 16);
|
||||
}
|
||||
|
||||
# SUB reg1, reg2 - rrrrr001101RRRRR
|
||||
:sub R0004, R1115 is op0510=0x0D & R0004 & R1115
|
||||
{
|
||||
set_general_flags_neg(R1115, R0004);
|
||||
R1115 = R1115 - R0004;
|
||||
}
|
||||
|
||||
# SUBR reg1, reg2 - rrrrr001100RRRRR
|
||||
:subr R0004, R1115 is op0510=0x0C & R0004 & R1115
|
||||
{
|
||||
set_general_flags_neg(R0004, R1115);
|
||||
R1115 = R0004 - R1115;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Saturated #####
|
||||
#####################################################
|
||||
|
||||
|
||||
define pcodeop __saturate;
|
||||
|
||||
# SATADD reg1, reg2 - rrrrr000110RRRRR
|
||||
:satadd R0004, R1115 is op0510=0x06 & R0004 & R1115 & op1115!=0
|
||||
{
|
||||
set_general_flags_pos(R1115, R0004);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R1115 = R1115 + R0004;
|
||||
__saturate(R1115);
|
||||
}
|
||||
|
||||
#SATADD imm5, reg2 - rrrrr010001iiiii
|
||||
:satadd s0004, R1115 is op0510=0x11 & s0004 & R1115 & op1115!=0
|
||||
{
|
||||
set_general_flags_pos(R1115, s0004);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R1115 = R1115 + s0004;
|
||||
__saturate(R1115);
|
||||
}
|
||||
|
||||
# SATADD reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110111010
|
||||
:satadd R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x3BA & R2731
|
||||
{
|
||||
set_general_flags_pos(R1115, R0004);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R2731 = R1115 + R0004;
|
||||
__saturate(R2731);
|
||||
}
|
||||
|
||||
# SATSUB reg1, reg2 - rrrrr000101RRRRR
|
||||
:satsub R0004, R1115 is op0510=0x05 & R0004 & R1115 & op1115!=0
|
||||
{
|
||||
set_general_flags_neg(R1115, R0004);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R1115 = R1115 - R0004;
|
||||
__saturate(R1115);
|
||||
}
|
||||
|
||||
# SATSUB reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01110011010
|
||||
:satsub R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x39A & R2731
|
||||
{
|
||||
set_general_flags_neg(R1115, R0004);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R2731 = R1115 - R0004;
|
||||
__saturate(R2731);
|
||||
}
|
||||
|
||||
# SATSUBI imm16, reg1, reg2
|
||||
:satsubi s1631, R0004, R1115 is op0510=0x33 & op1115!=0 & R0004 & R1115; s1631
|
||||
{
|
||||
set_general_flags_neg(R0004, s1631);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R1115 = R0004 - s1631;
|
||||
__saturate(R1115);
|
||||
}
|
||||
|
||||
# SATSUBR reg1, reg2
|
||||
:satsubr R0004, R1115 is op0510=0x04 & R0004 & R1115 & op1115!=0
|
||||
{
|
||||
set_general_flags_neg(R0004, R1115);
|
||||
$(SAT) = $(SAT) || $(OV);
|
||||
R1115 = R0004 - R1115;
|
||||
__saturate(R1115);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Divide #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# DIV reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000000
|
||||
:div R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C0 & R2731
|
||||
{
|
||||
local quot:4 = R1115 s/ R0004;
|
||||
local mod:4 = R1115 s% R0004;
|
||||
$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
R1115 = quot;
|
||||
R2731 = mod;
|
||||
}
|
||||
|
||||
# DIVH reg1, reg2 - rrrrr000010RRRRR
|
||||
:divh R0004, R1115 is op0510=0x02 & R0004 & R1115
|
||||
{
|
||||
$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);
|
||||
R1115 = R1115 / R0004;
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
}
|
||||
|
||||
# DIVH reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000000
|
||||
:divh R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x280 & R2731
|
||||
{
|
||||
local quot:4 = R1115 s/ sext(R0004:2);
|
||||
local mod:4 = R1115 s% sext(R0004:2);
|
||||
$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
R1115 = quot;
|
||||
R2731 = mod;
|
||||
}
|
||||
|
||||
# DIVHU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01010000010
|
||||
:divhu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x282 & R2731
|
||||
{
|
||||
local quot:4 = R1115 / sext(R0004:2);
|
||||
local mod:4 = R1115 % sext(R0004:2);
|
||||
$(OV) = (R0004 == 0);
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
R1115 = quot;
|
||||
R2731 = mod;
|
||||
}
|
||||
|
||||
# DIVU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011000010
|
||||
:divu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2C2 & R2731
|
||||
{
|
||||
local quot:4 = R1115 / R0004;
|
||||
local mod:4 = R1115 % R0004;
|
||||
$(OV) = (R0004 == 0);
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
R1115 = quot;
|
||||
R2731 = mod;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### HighSpeedDivide #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# DIVQ reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111100
|
||||
:divq R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FC & R2731
|
||||
{
|
||||
local quot:4 = R1115 s/ R0004;
|
||||
local mod:4 = R1115 s% R0004;
|
||||
$(OV) = ((R1115 == 0x80000000 && R0004 == 0xFFFFFFFF) || R0004 == 0x0);
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
R2731 = mod;
|
||||
R1115 = quot;
|
||||
}
|
||||
|
||||
# DIVQU reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww01011111110
|
||||
:divqu R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x2FE & R2731
|
||||
{
|
||||
local quot:4 = R1115 / R0004;
|
||||
local mod:4 = R1115 % R0004;
|
||||
$(OV) = (R0004 == 0);
|
||||
set_Z(R1115);
|
||||
set_S(R1115);
|
||||
R2731 = mod;
|
||||
R1115 = quot;
|
||||
}
|
||||
@@ -0,0 +1,474 @@
|
||||
#####################################################
|
||||
##### Float #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# ABSF.D reg2, reg3 - rrrr011111100000|wwww010001011000
|
||||
:absf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11000
|
||||
{
|
||||
R2731x2 = abs(R1115x2);
|
||||
}
|
||||
|
||||
# ABSF.S reg2, reg3 - rrrrr11111100000|wwwww10001001000
|
||||
:absf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01000
|
||||
{
|
||||
R2731 = abs(R1115);
|
||||
}
|
||||
|
||||
# ADDF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110000
|
||||
:addf.d R0004x2, R1115x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2 ; R2731x2 & op2126=0b100011 & op1620=0b10000
|
||||
{
|
||||
R2731x2 = R1115x2 f+ R0004x2;
|
||||
}
|
||||
|
||||
# ADDF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100000
|
||||
:addf.s R0004, R1115, R2731 is R1115 & op0510=0x3F & R0004 ; R2731 & op2126=0b100011 & op1620=0b00000
|
||||
{
|
||||
R2731 = R1115 f+ R0004;
|
||||
}
|
||||
|
||||
# CEILF.DL reg2, reg3 - rrrr011111100010|wwww010001010100
|
||||
:ceilf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
local var:8 = ceil(float2float(R1115x2));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# CEILF.DUL reg2, reg3 - rrrr011111110010|wwww010001010100
|
||||
:ceilf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
local var:8 = ceil(float2float(R1115x2));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# CEILF.DUW reg2, reg3 - rrrrr11111110010|wwwww10001010000
|
||||
:ceilf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(ceil(R1115x2));
|
||||
}
|
||||
|
||||
# CEILF.DW reg2, reg3 - rrrrr11111100010|wwwww10001010000
|
||||
:ceilf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(ceil(R1115x2));
|
||||
}
|
||||
|
||||
# CEILF.SL reg2, reg3 - rrrrr11111100010|wwww010001000100
|
||||
:ceilf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
local var:8 = ceil(float2float(R1115));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# CEILF.SUL reg2, reg3 - rrrrr11111110010|wwwww10001000100
|
||||
:ceilf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10010; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
local var:8 = ceil(float2float(R1115));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# CEILF.SUW reg2, reg3 - rrrrr11111110010|wwwww10001000000
|
||||
:ceilf.sul R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10010; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(ceil(R1115));
|
||||
}
|
||||
|
||||
# CEILF.SW reg2, reg3 - rrrrr11111100010|wwwww10001000000
|
||||
:ceilf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(ceil(R1115));
|
||||
}
|
||||
|
||||
# CMOVF.D fcbit, reg1, reg2, reg3 - rrrr0111111RRRR0|wwww01000001fff0
|
||||
:cmovf.d fcbit1719, R1115x2, R0004x2, R2731x2 is R1115x2 & op0510=0x3F & R0004x2; R2731x2 & op2126=0b100000 & op2020=1 & fcbit1719 & op1616=0
|
||||
{
|
||||
#CC0 = Bit 24
|
||||
local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1;
|
||||
either_or1(R2731x2, bit, R0004x2, R1115x2);
|
||||
}
|
||||
|
||||
# CMOVF.S fcbit, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww1000000fff0
|
||||
:cmovf.s fcbit1719, R1115, R0004, R2731 is R1115 & op0510=0x3F & R0004; R2731 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0
|
||||
{
|
||||
local bit = (FPSR >> (fcbit1719 + 24:1)) & 0x1;
|
||||
either_or1(R2731, bit, R0004, R1115);
|
||||
}
|
||||
|
||||
# CMPF.D fcond, reg2, reg1, fcbit - rrrr0111111RRRRR|0FFFF1000011fff0
|
||||
:cmpf.d fcond2730, R1115x2, R0004x2, fcbit1719 is R1115x2 & op0510=0x3F & R0004x2; op3131=0 & fcond2730 & op2126=0b100001 & op2020=1 & fcbit1719 & op1616=0
|
||||
{
|
||||
#0 = Unordered
|
||||
#1 = Equal to
|
||||
#2 = Less than
|
||||
#3 = Exeption
|
||||
#bits = ex le eq un
|
||||
|
||||
local bit:4 = 0;
|
||||
compare_float(bit, fcond2730:1, R0004x2, R1115x2);
|
||||
|
||||
local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit
|
||||
local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register
|
||||
FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position
|
||||
}
|
||||
|
||||
# CMPF.S fcond, reg2, reg1, fcbit - rrrrr111111RRRRR|0FFFF1000010fff0
|
||||
:cmpf.s fcond2730, R1115, R0004, fcbit1719 is R1115 & op0510=0x3F & R0004; op3131=0 & fcond2730 & op2126=0b100001 & op2020=0 & fcbit1719 & op1616=0
|
||||
{
|
||||
local bit:4 = 0;
|
||||
compare_float(bit, fcond2730:1, R0004, R1115);
|
||||
|
||||
local pos:4 = bit << (fcbit1719 + 24); #find position of the calculated bit
|
||||
local mask:4 = 1 << (fcbit1719 + 24); #create mask to clean old bit in FPSR register
|
||||
FPSR = (FPSR & ~mask) | pos; #set the new bit at the right position
|
||||
}
|
||||
|
||||
# CVTF.DL reg2, reg3 - rrrr011111100100|wwww010001010100
|
||||
:cvtf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
R2731x2 = int2float(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.DS reg2, reg3 - rrrr011111100011|wwww010001010010
|
||||
:cvtf.ds R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10010
|
||||
{
|
||||
R2731 = float2float(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.DUL reg2, reg3 - rrrr011111110100|wwww010001010100
|
||||
:cvtf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
R2731x2 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.DUW reg2, reg3 - rrrrr11111110100|wwwww10001010000
|
||||
:cvtf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.DW reg2, reg3 - rrrrr11111100100|wwwww10001010000
|
||||
:cvtf.sw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.LD reg2, reg3 - rrrr011111100001|wwww010001010010
|
||||
:cvtf.ls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10010
|
||||
{
|
||||
R2731x2 = int2float(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.LS reg2, reg3 - rrrr011111100001|wwwww10001000010
|
||||
:cvtf.ls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00010
|
||||
{
|
||||
R2731 = int2float(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.SD reg2, reg3 - rrrrr11111100010|wwww010001010010
|
||||
:cvtf.sd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b10010
|
||||
{
|
||||
R2731x2 = float2float(R1115);
|
||||
}
|
||||
|
||||
# CVTF.SL reg2, reg3 - rrrrr11111100100|wwwww10001000100
|
||||
:cvtf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00100; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
R2731x2 = trunc(R1115);
|
||||
}
|
||||
|
||||
# CVTF.SUL reg2, reg3 - rrrrr11111110100|wwwww10001000100
|
||||
:cvtf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10100; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
R2731x2 = trunc(R1115);
|
||||
}
|
||||
|
||||
# CVTF.SUW reg2, reg3 - rrrrr11111110100|wwwww10001000000
|
||||
:cvtf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10100; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(R1115);
|
||||
}
|
||||
|
||||
# CVTF.SW reg2, reg3 - rrrrr11111100100|wwwww10001000000
|
||||
:cvtf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00100; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(R1115);
|
||||
}
|
||||
|
||||
# CVTF.ULD reg2, reg3 - rrrr011111100001|wwww010001010010
|
||||
:cvtf.uls R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10010
|
||||
{
|
||||
R2731x2 = int2float(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.ULS reg2, reg3 - rrrr011111110001|wwwww10001000010
|
||||
:cvtf.uls R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00010
|
||||
{
|
||||
R2731 = int2float(R1115x2);
|
||||
}
|
||||
|
||||
# CVTF.UWD reg2, reg3 - rrrrr11111110000|wwwww10001010010
|
||||
:cvtf.uwd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10000; R2731x2 & op2126=0b100010 & op1620=0b10010
|
||||
{
|
||||
R2731x2 = int2float(R1115);
|
||||
}
|
||||
|
||||
# CVTF.UWS reg2, reg3 - rrrrr11111110000|wwwww10001000010
|
||||
:cvtf.uws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10000; R2731 & op2126=0b100010 & op1620=0b00010
|
||||
{
|
||||
R2731 = int2float(R1115);
|
||||
}
|
||||
|
||||
# CVTF.WD reg2, reg3 - rrrrr11111100000|wwwww10001010010
|
||||
:cvtf.wd R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b10010
|
||||
{
|
||||
R2731x2 = int2float(R1115);
|
||||
}
|
||||
|
||||
# CVTF.WS reg2, reg3 - rrrrr11111100000|wwwww10001000010
|
||||
:cvtf.ws R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b00010
|
||||
{
|
||||
R2731 = int2float(R1115);
|
||||
}
|
||||
|
||||
# DIVF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111110
|
||||
:divf.s R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11110
|
||||
{
|
||||
R2731x2 = R1115x2 f/ R0004x2;
|
||||
}
|
||||
|
||||
# DIVF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101110
|
||||
:divf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01110
|
||||
{
|
||||
R2731 = R1115 f/ R0004;
|
||||
}
|
||||
|
||||
# FLOORF.DL reg2, reg3 - rrrr011111100011|wwww010001010100
|
||||
:floorf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
local var:8 = floor(float2float(R1115x2));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# FLOORF.DUL reg2, reg3 - rrrr011111110011|wwww010001010100
|
||||
:floorf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
local var:8 = floor(float2float(R1115x2));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# FLOORF.DUW reg2, reg3 - rrrrr11111110011|wwwww10001010000
|
||||
:floorf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(floor(R1115x2));
|
||||
}
|
||||
|
||||
# FLOORF.DW reg2, reg3 - rrrrr11111100011|wwwww10001010000
|
||||
:floorf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(floor(R1115x2));
|
||||
}
|
||||
|
||||
# FLOORF.SL reg2, reg3 - rrrrr11111100011|wwww010001000100
|
||||
:floorf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00011; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
local var:8 = floor(float2float(R1115));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# FLOORF.SUL reg2, reg3 - rrrrr11111110011|wwwww10001000100
|
||||
:floorf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10011; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
local var:8 = floor(float2float(R1115));
|
||||
R2731x2 = trunc(var);
|
||||
}
|
||||
|
||||
# FLOORF.SUW reg2, reg3 - rrrrr11111110011|wwwww10001000000
|
||||
:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10011; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(floor(R1115));
|
||||
}
|
||||
|
||||
# FLOORF.SW reg2, reg3 - rrrrr11111100011|wwwww10001000000
|
||||
:floorf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00011; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(floor(R1115));
|
||||
}
|
||||
|
||||
# MADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W00WWWW0
|
||||
:maddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b00 & op1616=0 & reg4
|
||||
{
|
||||
reg4 = (R1115 f* R0004) f+ R2731;
|
||||
}
|
||||
|
||||
# MAXF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111000
|
||||
:maxf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11000
|
||||
{
|
||||
local bigger:1 = R1115x2 f> R0004x2;
|
||||
either_or(R2731x2, bigger, R1115x2, R0004x2);
|
||||
}
|
||||
|
||||
# MAXF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001101000
|
||||
:maxf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01000
|
||||
{
|
||||
local bigger:1 = R1115 f> R0004;
|
||||
either_or(R2731, bigger, R1115, R0004);
|
||||
}
|
||||
|
||||
# MINF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001111010
|
||||
:minf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b11010
|
||||
{
|
||||
local bigger:1 = R1115x2 f< R0004x2;
|
||||
either_or(R2731x2, bigger, R1115x2, R0004x2);
|
||||
}
|
||||
|
||||
# MINF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001101010
|
||||
:minf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b01010
|
||||
{
|
||||
local bigger:1 = R1115 f< R0004;
|
||||
either_or(R2731, bigger, R1115, R0004);
|
||||
}
|
||||
|
||||
# MSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W01WWWW0
|
||||
:msubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b01 & op1616=0 & reg4
|
||||
{
|
||||
reg4 = (R1115 f* R0004) f- R2731;
|
||||
}
|
||||
|
||||
# MULF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110100
|
||||
:mulf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10100
|
||||
{
|
||||
R2731x2 = R1115x2 f* R0004x2;
|
||||
}
|
||||
|
||||
# MULF.S reg1, reg2, reg3 - rrrr0111111RRRRR|wwwww10001100100
|
||||
:mulf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00100
|
||||
{
|
||||
R2731 = R1115 f* R0004;
|
||||
}
|
||||
|
||||
# NEGF.D reg2, reg3 - rrrr011111100001|wwww010001011000
|
||||
:negf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11000
|
||||
{
|
||||
R2731x2 = f- R1115x2;
|
||||
}
|
||||
|
||||
# NEGF.S reg2, reg3 - rrrrr11111100001|wwwww10001001000
|
||||
:negf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01000
|
||||
{
|
||||
R2731 = f- R1115;
|
||||
}
|
||||
|
||||
# NMADDF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W10WWWW0
|
||||
:nmaddf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b10 & op1616=0 & reg4
|
||||
{
|
||||
reg4 = f-((R1115 f* R0004) f+ R2731);
|
||||
}
|
||||
|
||||
# NMSUBF.S reg1, reg2, reg3, reg4 - rrrrr111111RRRRR|wwwww101W11WWWW0
|
||||
:nmsubf.s R0004, R1115, R2731, reg4 is R0004 & op0510=0x3F & R1115; R2731 & op2426=0b101 & op2122=0b11 & op1616=0 & reg4
|
||||
{
|
||||
reg4 = f-((R1115 f* R0004) f- R2731);
|
||||
}
|
||||
|
||||
# RECIPF.D reg2, reg3 - rrrr011111100001|wwww010001011110
|
||||
:recipf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b11110
|
||||
{
|
||||
R2731x2 = 1 f/ R1115x2;
|
||||
}
|
||||
|
||||
# RECIPF.S reg2, reg3 - rrrrr11111100001|wwwww10001001110
|
||||
:recipf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b01110
|
||||
{
|
||||
R2731 = 1 f/ R1115;
|
||||
}
|
||||
|
||||
# RSQRTF.D reg2, reg3 - rrrr011111100010|wwwww10001011110
|
||||
:rsqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00010; R2731x2 & op2126=0b100010 & op1620=0b11110
|
||||
{
|
||||
R2731x2 = 1 f/ sqrt(R1115x2);
|
||||
}
|
||||
|
||||
# RSQRTF.S reg2, reg3 - rrrrr11111100010|wwwww10001001110
|
||||
:rsqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00010; R2731 & op2126=0b100010 & op1620=0b01110
|
||||
{
|
||||
R2731 = 1 f/ sqrt(R1115);
|
||||
}
|
||||
|
||||
# SQRTF.D reg2, reg3 - rrrr011111100000|wwww010001011110
|
||||
:sqrtf.d R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00000; R2731x2 & op2126=0b100010 & op1620=0b11110
|
||||
{
|
||||
R2731x2 = sqrt(R1115x2);
|
||||
}
|
||||
|
||||
# SQRTF.S reg2, reg3 - rrrrr11111100000|wwwww10001001110
|
||||
:sqrtf.s R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00000; R2731 & op2126=0b100010 & op1620=0b01110
|
||||
{
|
||||
R2731 = sqrt(R1115);
|
||||
}
|
||||
|
||||
# SUBF.D reg1, reg2, reg3 - rrrr0111111RRRR0|wwww010001110010
|
||||
:subf.d R0004x2, R1115x2, R2731x2 is R0004x2 & op0510=0x3F & R1115x2; R2731x2 & op2126=0b100011 & op1620=0b10010
|
||||
{
|
||||
R2731x2 = R1115x2 f- R0004x2;
|
||||
}
|
||||
|
||||
# SUBF.S reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww10001100010
|
||||
:subf.s R0004, R1115, R2731 is R0004 & op0510=0x3F & R1115; R2731 & op2126=0b100011 & op1620=0b00010
|
||||
{
|
||||
R2731 = R1115 f- R0004;
|
||||
}
|
||||
|
||||
# TRFSR fcbit - 0000011111100000|000001000000fff0
|
||||
:trfsr fcbit1719 is op1115=0 & op0510=0x3F & op0004=0; op2731=0 & op2126=0b100000 & op2020=0 & fcbit1719 & op1616=0
|
||||
{
|
||||
local var:4 = FPSR & (1 << (fcbit1719 + 24));
|
||||
$(Z) = (var != 0);
|
||||
}
|
||||
|
||||
# TRNCF.DL reg2, reg3 - rrrr011111100001|wwww010001010100
|
||||
:trncf.dl R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
R2731x2 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# TRNCF.DUL reg2, reg3 - rrrr011111110001|wwww010001010100
|
||||
:trncf.dul R1115x2, R2731x2 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b10100
|
||||
{
|
||||
R2731x2 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# TRNCF.DUW reg2, reg3 - rrrrr11111110001|wwwww10001010000
|
||||
:trncf.duw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# TRNCF.DW reg2, reg3 - rrrrr11111100001|wwwww10001010000
|
||||
:trncf.dw R1115x2, R2731 is R1115x2 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b10000
|
||||
{
|
||||
R2731 = trunc(R1115x2);
|
||||
}
|
||||
|
||||
# TRNCF.SL reg2, reg3 - rrrrr11111100001|wwww010001000100
|
||||
:trncf.sl R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b00001; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
R2731x2 = trunc(R1115);
|
||||
}
|
||||
|
||||
# TRNCF.SUL reg2, reg3 - rrrrr11111110001|wwww010001000100
|
||||
:trncf.sul R1115, R2731x2 is R1115 & op0510=0x3F & op0004=0b10001; R2731x2 & op2126=0b100010 & op1620=0b00100
|
||||
{
|
||||
R2731x2 = trunc(R1115);
|
||||
}
|
||||
|
||||
# TRNCF.SUW reg2, reg3 - rrrrr11111110001|wwwww10001000000
|
||||
:trncf.suw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b10001; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(R1115);
|
||||
}
|
||||
|
||||
# TRNCF.SW reg2, reg3 - rrrrr11111100001|wwwww10001000000
|
||||
:trncf.sw R1115, R2731 is R1115 & op0510=0x3F & op0004=0b00001; R2731 & op2126=0b100010 & op1620=0b00000
|
||||
{
|
||||
R2731 = trunc(R1115);
|
||||
}
|
||||
@@ -0,0 +1,368 @@
|
||||
# (1) Load instructions
|
||||
# (2) Store instructions
|
||||
# (9) Data manipulation instructions
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Load #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# LD.B disp16[reg1], reg2 - rrrrr111000RRRRR|dddddddddddddddd
|
||||
:ld.b s1631[R0004], R1115 is op0510=0x38 & R0004 & R1115; s1631
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
R1115 = sext(*:1 adr);
|
||||
}
|
||||
|
||||
# LD.B disp23[reg1], reg3 - rrrrr111100RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD
|
||||
:ld.b disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2026 & op1619=0x5; s3247
|
||||
[ disp23 = (s3247 << 7) | op2026; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
R2731 = sext(*:1 adr);
|
||||
}
|
||||
|
||||
# LD.BU disp16[reg1], reg2 - rrrrr11110bRRRRR|ddddddddddddddd1
|
||||
:ld.bu disp16[R0004], R1115 is op0610=0x1E & R0004 & R1115 & op0505; op1616=0x1 & s1731
|
||||
[ disp16 = (s1731 << 1) | op0505; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp16;
|
||||
R1115 = zext(*:1 adr);
|
||||
}
|
||||
|
||||
# LD.BU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwddddddd0101|DDDDDDDDDDDDDDDD
|
||||
:ld.bu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x5; s3247
|
||||
[ disp23 = (s3247 << 7) | op2026; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
R2731 = zext(*:1 adr);
|
||||
}
|
||||
|
||||
# LD.H disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd0
|
||||
:ld.h s1631[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1631 & op1616=0x0
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
R1115 = sext(*:2 adr);
|
||||
}
|
||||
|
||||
# LD.H disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD
|
||||
:ld.h disp23[R0004], R2731 is op0515=0x3C & R0004; R2731 & op2126 & op1620=0x7; s3247
|
||||
[ disp23 = (s3247 << 7) | (op2126 << 1); ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
R2731 = sext(*:2 adr);
|
||||
}
|
||||
|
||||
# LD.HU disp16[reg1], reg2 - rrrrr111111RRRRR|ddddddddddddddd1
|
||||
:ld.hu disp16[R0004], R1115 is op0510=0x3F & R0004 & R1115; op1616=0x1 & s1731
|
||||
[ disp16 = s1731 << 1; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp16;
|
||||
R1115 = zext(*:2 adr);
|
||||
}
|
||||
|
||||
# LD.HU disp23[reg1], reg3 - 00000111101RRRRR|wwwwwdddddd00111|DDDDDDDDDDDDDDDD
|
||||
:ld.hu disp23[R0004], R2731 is op0515=0x3D & R0004; R2731 & op2026 & op1619=0x7; s3247
|
||||
[ disp23 = (s3247 << 7) | op2026; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
R2731 = zext(*:2 adr);
|
||||
}
|
||||
|
||||
# LD.W disp16[reg1], reg2 - rrrrr111001RRRRR|ddddddddddddddd1
|
||||
:ld.w disp16[R0004], R1115 is op0510=0x39 & R0004 & R1115; s1731 & op1616=0x1
|
||||
[ disp16 = s1731 * 2; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp16;
|
||||
R1115 = *:4 adr;
|
||||
}
|
||||
|
||||
# LD.W disp23[reg1], reg3 - 00000111100RRRRR|wwwwwdddddd01001|DDDDDDDDDDDDDDDD
|
||||
:ld.w disp23[R0004], R2731 is op0515=0x03C & R0004; R2731 & op2126 & op1620=0x9; s3247
|
||||
[ disp23 = (s3247 << 7) | (op2126 << 1); ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
R2731 = *:4 adr;
|
||||
}
|
||||
|
||||
# SLD.B disp7[ep], reg2 - rrrrr0110ddddddd
|
||||
:sld.b op0006[ep], R1115 is op0710=0x06 & op0006 & R1115 & ep
|
||||
{
|
||||
local adr:4 = ep + op0006;
|
||||
R1115 = sext(*:1 adr);
|
||||
}
|
||||
|
||||
# SLD.BU disp4[ep], reg2 - rrrrr0000110dddd
|
||||
:sld.bu op0003[ep], R1115 is op0410=0x06 & R1115 & op0003 & ep
|
||||
{
|
||||
local adr:4 = ep + op0003;
|
||||
R1115 = zext(*:1 adr);
|
||||
}
|
||||
|
||||
# SLD.H disp8[ep], reg2 - rrrrr1000ddddddd
|
||||
:sld.h disp8[ep], R1115 is op0710=0x08 & op0006 & R1115 & ep
|
||||
[ disp8 = op0006 * 2; ]
|
||||
{
|
||||
local adr:4 = ep + disp8;
|
||||
R1115 = sext(*:2 adr);
|
||||
}
|
||||
|
||||
# SLD.HU disp5[ep], reg2 - rrrrr0000111dddd
|
||||
:sld.hu disp5[ep], R1115 is op0410=0x07 & R1115 & op0003 & ep
|
||||
[ disp5 = op0003 * 2; ]
|
||||
{
|
||||
local adr:4 = ep + disp5;
|
||||
R1115 = zext(*:2 adr);
|
||||
}
|
||||
|
||||
# SLD.W disp8[ep], reg2 - rrrrr1010dddddd0
|
||||
:sld.w disp8[ep], R1115 is op0710=0x0A & op0000=0x0 & op0106 & R1115 & ep
|
||||
[ disp8 = op0106 * 4; ]
|
||||
{
|
||||
local adr:4 = ep + disp8;
|
||||
R1115 = *:4 adr;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Store #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# SST.B reg2, disp7[ep] - rrrrr0111ddddddd
|
||||
:sst.b R1115, op0006[ep] is op0710=0x07 & op0006 & R1115 & ep
|
||||
{
|
||||
local adr:4 = ep + op0006;
|
||||
local tmp:4 = R1115;
|
||||
*:1 adr = tmp:1;
|
||||
}
|
||||
|
||||
# SST.H reg2, disp8[ep] - rrrrr1001ddddddd
|
||||
:sst.h R1115, disp8[ep] is op0710=0x09 & op0006 & R1115 & ep
|
||||
[ disp8 = op0006 * 2; ]
|
||||
{
|
||||
local adr:4 = ep + disp8;
|
||||
local tmp:4 = R1115;
|
||||
*:2 adr = tmp:2;
|
||||
}
|
||||
|
||||
# SST.W reg2, disp8[ep] - rrrrr1010dddddd1
|
||||
:sst.w R1115, disp8[ep] is op0710=0x0A & op0000=0x1 & op0106 & R1115 & ep
|
||||
[ disp8 = op0106 * 4; ]
|
||||
{
|
||||
local adr:4 = ep + disp8;
|
||||
local tmp:4 = R1115;
|
||||
*:4 adr = tmp;
|
||||
}
|
||||
|
||||
# ST.B reg2, disp16[reg1] - rrrrr111010RRRRR|dddddddddddddddd
|
||||
:st.b R1115, s1631[R0004] is op0510=0x3A & R0004 & R1115; s1631
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
local tmp:4 = R1115;
|
||||
*:1 adr = tmp:1;
|
||||
}
|
||||
|
||||
# ST.B reg3, disp23[reg1] - 00000111100RRRRR|dddddddddddddddd
|
||||
:st.b R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2026 & op1619=0xD; s3247
|
||||
[ disp23 = (s3247 << 7) | op2026; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
local tmp:4 = R2731;
|
||||
*:1 adr = tmp:1;
|
||||
}
|
||||
|
||||
# ST.H reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd0
|
||||
:st.h R1115, s1631[R0004] is op0510=0x3B & R0004 & R1115; s1631 & op1616=0x0
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
local tmp:4 = R1115;
|
||||
*:2 adr = tmp:2;
|
||||
}
|
||||
|
||||
# ST.H reg3, disp23[reg1] - 00000111101RRRRR|wwwwwdddddd01101|DDDDDDDDDDDDDDDD
|
||||
:st.h R2731, disp23[R0004] is op0515=0x3D & R0004; R2731 & op2126 & op1620=0xD; s3247
|
||||
[ disp23 = (s3247 << 7) | (op2126 << 1); ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
local tmp:4 = R2731;
|
||||
*:2 adr = tmp:2;
|
||||
}
|
||||
|
||||
# ST.W reg2, disp16[reg1] - rrrrr111011RRRRR|ddddddddddddddd1
|
||||
:st.w R1115, disp16[R0004] is op0510=0x3B & R0004 & R1115; s1731 & op1616=0x1
|
||||
[ disp16 = s1731 * 2; ]
|
||||
{
|
||||
local adr:4 = R0004 + disp16;
|
||||
local tmp:4 = R1115;
|
||||
*:4 adr = tmp;
|
||||
}
|
||||
|
||||
# ST.W reg3, disp23[reg1] - 00000111100RRRRR|wwwwwdddddd01111|DDDDDDDDDDDDDDDD
|
||||
:st.w R2731, disp23[R0004] is op0515=0x3C & R0004; R2731 & op2126 & op1620=0xF; s3247
|
||||
[ disp23 = (s3247 << 7) | (op2126 << 1); ]
|
||||
{
|
||||
local adr:4 = R0004 + disp23;
|
||||
local tmp:4 = R2731;
|
||||
*:2 adr = tmp:2;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### DataManipulation #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# BSH reg2, reg3 - rrrrr11111100000|wwwww01101000010
|
||||
:bsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x342 & R2731
|
||||
{
|
||||
local x1 = R1115[0,8];
|
||||
local x2 = R1115[8,8];
|
||||
local x3 = R1115[16,8];
|
||||
local x4 = R1115[24,8];
|
||||
R2731 = zext(x3 << 24) | zext(x4 << 16) | zext(x1 << 8) | zext(x2);
|
||||
set_S(R2731);
|
||||
$(OV) = 0;
|
||||
$(Z) = (x1 == 0) && (x2 == 0);
|
||||
$(CY) = (x1 == 0) || (x2 == 0);
|
||||
}
|
||||
|
||||
# BSW reg2, reg3 - rrrrr11111100000|wwwww01101000000
|
||||
:bsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x340 & R2731
|
||||
{
|
||||
local x1 = R1115[0,8];
|
||||
local x2 = R1115[8,8];
|
||||
local x3 = R1115[16,8];
|
||||
local x4 = R1115[24,8];
|
||||
R2731 = zext(x1 << 24) | zext(x2 << 16) | zext(x3 << 8) | zext(x4);
|
||||
set_OV0_S_Z(R2731);
|
||||
$(CY) = (x1 == 0) || (x2 == 0) || (x3 == 0) || (x4 == 0);
|
||||
}
|
||||
|
||||
# CMOV cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011001cccc0
|
||||
:cmov^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x19 & op1616=0 & c1720 & R2731
|
||||
{
|
||||
local result:4 = zext(c1720);
|
||||
R2731 = R0004 * zext(result != 0) + R1115 * zext(result == 0);
|
||||
}
|
||||
|
||||
# CMOV cccc, imm5, reg2, reg3 - rrrrr111111iiiii|wwwww011000cccc0
|
||||
:cmov^c1720 s0004, R1115, R2731 is op0510=0x3F & s0004 & R1115; op2126=0x18 & op1616=0 & c1720 & R2731
|
||||
{
|
||||
local result:4 = zext(c1720);
|
||||
R2731 = s0004 * zext(result != 0) + R1115 * zext(result == 0);
|
||||
}
|
||||
|
||||
# HSH reg2, reg3 - rrrrr11111100000|wwwww01101000110
|
||||
:hsh R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x346 & R2731
|
||||
{
|
||||
R2731 = R1115;
|
||||
set_S(R2731);
|
||||
$(OV) = 0;
|
||||
$(Z) = (R2731:2 == 0);
|
||||
$(CY) = $(Z);
|
||||
}
|
||||
|
||||
# HSW reg2, reg3 - rrrrr11111100000|wwwww01101000100
|
||||
:hsw R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x344 & R2731
|
||||
{
|
||||
local x1 = R1115:2;
|
||||
local x2 = R1115[16,16];
|
||||
R2731 = zext(x1 << 16) | zext(x2);
|
||||
set_OV0_S_Z(R2731);
|
||||
$(CY) = (x1 == 0) || (x2 == 0);
|
||||
}
|
||||
|
||||
# SAR reg1, reg2 - rrrrr111111RRRRR|0000000010100000
|
||||
:sar R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xA0
|
||||
{
|
||||
shift_right_arith(R1115, R1115, R0004);
|
||||
}
|
||||
|
||||
# SAR imm5, reg2 - rrrrr010101iiiii
|
||||
:sar op0004, R1115 is op0510=0x15 & op0004 & R1115
|
||||
{
|
||||
shift_right_arith(R1115, R1115, op0004:5);
|
||||
}
|
||||
|
||||
# SAR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010100010
|
||||
:sar R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xA2 & R2731
|
||||
{
|
||||
shift_right_arith(R2731, R1115, R0004);
|
||||
}
|
||||
|
||||
# SASF cccc, reg2 - rrrrr1111110cccc|0000001000000000
|
||||
:sasf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0200
|
||||
{
|
||||
R1115 = (R1115 << 1) | zext(c0003);
|
||||
}
|
||||
|
||||
# SETF cond, reg2 - rrrrr1111110cccc|0000000000000000
|
||||
:setf^c0003 R1115 is op0410=0x7E & c0003 & R1115; op1631=0x0
|
||||
{
|
||||
R1115 = zext(c0003);
|
||||
}
|
||||
|
||||
# SHL reg1, reg2 - rrrrr111111RRRRR|0000000011000000
|
||||
:shl R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0xC0
|
||||
{
|
||||
shift_left_logic(R1115, R1115, R0004);
|
||||
}
|
||||
|
||||
# SHL imm5, reg2 - rrrrr010110iiiii
|
||||
:shl op0004, R1115 is op0510=0x16 & op0004 & R1115
|
||||
{
|
||||
shift_left_logic(R1115, R1115, op0004:5);
|
||||
}
|
||||
|
||||
# SHL reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00011000010
|
||||
:shl R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xC2 & R2731
|
||||
{
|
||||
shift_left_logic(R2731, R1115, R0004);
|
||||
}
|
||||
|
||||
# SHR reg1, reg2 - rrrrr111111RRRRR|0000000010000000
|
||||
:shr R0004, R1115 is op0510=0x3F & R0004 & R1115; op1631=0x80
|
||||
{
|
||||
shift_right_logic(R1115, R1115, R0004);
|
||||
}
|
||||
|
||||
# SHR imm5, reg2 - rrrrr010100iiiii
|
||||
:shr op0004, R1115 is op0510=0x14 & op0004 & R1115
|
||||
{
|
||||
shift_right_logic(R1115, R1115, op0004:5);
|
||||
}
|
||||
|
||||
# SHR reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww00010000010
|
||||
:shr R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0x82 & R2731
|
||||
{
|
||||
shift_right_logic(R2731, R1115, R0004);
|
||||
}
|
||||
|
||||
# SXB reg1 - 00000000101RRRRR
|
||||
:sxb R0004 is op0515=0x05 & R0004
|
||||
{
|
||||
R0004 = sext(R0004:1);
|
||||
}
|
||||
|
||||
# SXH reg1 - 00000000111RRRRR
|
||||
:sxh R0004 is op0515=0x07 & R0004
|
||||
{
|
||||
R0004 = sext(R0004:2);
|
||||
}
|
||||
|
||||
# ZXB reg1 - 00000000100RRRRR
|
||||
:zxb R0004 is op0515=0x004 & R0004
|
||||
{
|
||||
R0004 = zext(R0004:1);
|
||||
}
|
||||
|
||||
# ZXH reg1 - 00000000110RRRRR
|
||||
:zxh R0004 is op0515=0x006 & R0004
|
||||
{
|
||||
R0004 = zext(R0004:2);
|
||||
}
|
||||
@@ -0,0 +1,167 @@
|
||||
# (6) Conditional arithmetic instructions
|
||||
# (8) Logical instructions
|
||||
# (14) Bit manipulation instructions
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Conditional #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# ADF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011101cccc0
|
||||
:adf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1D & op1616=0 & c1720 & R2731
|
||||
{
|
||||
local cond = zext(c1720);
|
||||
set_OV_pos2(R1115, R0004, cond);
|
||||
set_CY_pos2(R1115, R0004, cond);
|
||||
R2731 = R1115 + R0004 + cond;
|
||||
set_S(R2731);
|
||||
set_Z(R2731);
|
||||
}
|
||||
|
||||
# SBF cccc, reg1, reg2, reg3 - rrrrr111111RRRRR|wwwww011100cccc0
|
||||
:sbf^c1720 R0004, R1115, R2731 is op0510=0x3F & R0004 & R1115; op2126=0x1C & op1616=0 & c1720 & R2731
|
||||
{
|
||||
local cond = zext(c1720);
|
||||
set_OV_neg2(R1115, R0004, cond);
|
||||
set_CY_neg2(R1115, R0004, cond);
|
||||
R2731 = R1115 - R0004 - cond;
|
||||
set_S(R2731);
|
||||
set_Z(R2731);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Logic #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# AND reg1, reg2 - rrrrr001010RRRRR
|
||||
:and R0004, R1115 is op0510=0x0A & R0004 & R1115
|
||||
{
|
||||
R1115 = R1115 & R0004;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
# ANDI imm16, reg1, reg2 - rrrrr110110RRRRR|iiiiiiiiiiiiiiii
|
||||
:andi op1631, R0004, R1115 is op0510=0x36 & R1115 & R0004; op1631
|
||||
{
|
||||
R1115 = R0004 & op1631;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
# NOT reg1, reg2 - rrrrr000001RRRRR
|
||||
:not R0004, R1115 is op0510=0x01 & R0004 & R1115
|
||||
{
|
||||
R1115 = ~R0004;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
# OR reg1, reg2 - rrrrr001000RRRRR
|
||||
:or R0004, R1115 is op0510=0x08 & R0004 & R1115
|
||||
{
|
||||
R1115 = R1115 | R0004;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
# ORI imm16, reg1, reg2 - rrrrr110100RRRRR|iiiiiiiiiiiiiiii
|
||||
:ori op1631, R0004, R1115 is op0510=0x34 & R1115 & R0004; op1631
|
||||
{
|
||||
R1115 = R0004 | op1631;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
# TST reg1, reg2 - rrrrr001011RRRRR
|
||||
:tst R0004, R1115 is op0510=0x0B & R0004 & R1115
|
||||
{
|
||||
set_OV0_S_Z(R1115 & R0004);
|
||||
}
|
||||
|
||||
# XOR reg1, reg2 - rrrrr001001RRRRR
|
||||
:xor R0004, R1115 is op0510=0x09 & R0004 & R1115
|
||||
{
|
||||
R1115 = R1115 ^ R0004;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
# XORI imm16, reg1, reg2 - rrrrr110101RRRRR|iiiiiiiiiiiiiiii
|
||||
:xori op1631, R0004, R1115 is op0510=0x35 & R1115 & R0004; op1631
|
||||
{
|
||||
R1115 = R0004 ^ op1631;
|
||||
set_OV0_S_Z(R1115);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### BitManipulation #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# CLR1 bit#3, disp16[reg1] - 10bbb111110RRRRR|dddddddddddddddd
|
||||
:clr1 op1113, s1631[R0004] is op0510=0x3E & op1415=2 & op1113 & R0004; s1631
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
local tkn = *:1 adr;
|
||||
*:1 adr = tkn & ~(1 << op1113);
|
||||
set_Z(tkn & (1 << op1113));
|
||||
}
|
||||
|
||||
# CLR1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100100
|
||||
:clr1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE4
|
||||
{
|
||||
local tkn = *:1 R0004;
|
||||
*:1 R0004 = tkn & ~(1 << R1115);
|
||||
set_Z(tkn & (1 << R1115));
|
||||
}
|
||||
|
||||
# NOT1 bit#3, disp16[reg1] - 01bbb111110RRRRR|dddddddddddddddd
|
||||
:not1 op1113, s1631[R0004] is op0510=0x3E & op1415=1 & op1113 & R0004; s1631
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
local tkn = *:1 adr;
|
||||
*:1 adr = tkn ^ (1 << op1113);
|
||||
set_Z(tkn & (1 << op1113));
|
||||
}
|
||||
|
||||
# NOT1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100010
|
||||
:not1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE2
|
||||
{
|
||||
local tkn = *:1 R0004;
|
||||
*:1 R0004 = tkn ^ (1 << R1115);
|
||||
set_Z(tkn & (1 << R1115));
|
||||
}
|
||||
|
||||
# SET1 bit#3, disp16[reg1] - 00bbb111110RRRRR|dddddddddddddddd
|
||||
:set1 op1113, s1631[R0004] is op0510=0x3E & op1415=0 & op1113 & R0004; s1631
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
local tkn = *:1 adr;
|
||||
*:1 adr = tkn | (1 << op1113);
|
||||
set_Z(tkn & (1 << op1113));
|
||||
}
|
||||
|
||||
# SET1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100000
|
||||
:set1 R1115, [R0004] is op0510=0x3F & R0004 & R1115; op1631=0xE0
|
||||
{
|
||||
local tkn = *:1 R0004;
|
||||
*:1 R0004 = tkn | (1 << R1115);
|
||||
set_Z(tkn & (1 << R1115));
|
||||
}
|
||||
|
||||
# TST1 bit#3, disp16[reg1] - 11bbb111110RRRRR|dddddddddddddddd
|
||||
:tst1 op1113, s1631[R0004] is op0510=0x3E & op1415=3 & op1113 & R0004; s1631
|
||||
{
|
||||
local adr:4 = R0004 + s1631;
|
||||
local tkn = *:1 adr;
|
||||
set_Z(tkn & (1 << op1113));
|
||||
}
|
||||
|
||||
# TST1 reg2, [reg1] - rrrrr111111RRRRR|0000000011100110
|
||||
:tst1 R0004, [R1115] is op0510=0x3F & R0004 & R1115; op1631=0xE6
|
||||
{
|
||||
local tkn = *:1 R0004;
|
||||
set_Z(tkn & (1 << R1115));
|
||||
}
|
||||
@@ -0,0 +1,378 @@
|
||||
# (10) Bit search instructions
|
||||
# (13) Branch instructions
|
||||
# (15) Special instructions
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### BitSearch #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# SCH0L reg2, reg3 - rrrrr11111100000|wwwww01101100100
|
||||
:sch0l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x364 & R2731
|
||||
{
|
||||
SearchLeft(R2731, R1115, 0);
|
||||
$(CY) = (R1115 != 0xFFFFFFFF); # zero bit found
|
||||
$(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found
|
||||
}
|
||||
|
||||
# SCH0R reg2, reg3 - rrrrr11111100000|wwwww01101100000
|
||||
:sch0r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x360 & R2731
|
||||
{
|
||||
SearchRight(R2731, R1115, 0);
|
||||
$(CY) = (R1115 != 0xFFFFFFFF); # zero bit found
|
||||
$(Z) = (R1115 == 0xFFFFFFFF); # zero bit not found
|
||||
}
|
||||
|
||||
# SCH1L reg2, reg3 - rrrrr11111100000|wwwww01101100110
|
||||
:sch1l R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x366 & R2731
|
||||
{
|
||||
SearchLeft(R2731, R1115, 1);
|
||||
$(CY) = (R1115 != 0x0); # one bit found
|
||||
$(Z) = (R1115 == 0x0); # one bit not found
|
||||
}
|
||||
|
||||
# SCH1R reg2, reg3
|
||||
:sch1r R1115, R2731 is op0010=0x7E0 & R1115; op1626=0x362 & R2731
|
||||
{
|
||||
SearchRight(R2731, R1115, 1);
|
||||
$(CY) = (R1115 != 0x0); # one bit found
|
||||
$(Z) = (R1115 == 0x0); # one bit not found
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Branch #####
|
||||
#####################################################
|
||||
|
||||
|
||||
#Bcond adr9 - ddddd1011dddcccc
|
||||
:b^c0003 adr9 is op0710=0xB & c0003 & adr9
|
||||
{
|
||||
if (c0003)
|
||||
goto adr9;
|
||||
}
|
||||
:br adr9 is op0710=0xB & op0003=0x5 & adr9
|
||||
{
|
||||
goto adr9;
|
||||
}
|
||||
|
||||
# JARL disp22, reg2 - rrrrr11110dddddd|ddddddddddddddd0
|
||||
:jarl adr22, R1115 is (op0610=0x1E & R1115) ... & adr22
|
||||
{
|
||||
R1115 = inst_next;
|
||||
PC = & adr22;
|
||||
call adr22;
|
||||
}
|
||||
|
||||
# JARL disp32, reg1 - 00000010111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD
|
||||
:jarl adr32, R0004 is op0515=0x017 & R0004; adr32
|
||||
{
|
||||
R0004 = inst_next;
|
||||
PC = & adr32;
|
||||
call adr32;
|
||||
}
|
||||
|
||||
# JMP [reg1] - 00000000011RRRRR
|
||||
:jmp [R0004] is op0515=0x03 & R0004 & op0004=0x1F
|
||||
{
|
||||
PC = R0004;
|
||||
return [R0004];
|
||||
}
|
||||
:jmp [R0004] is op0515=0x03 & R0004 & op0004!=0x1F
|
||||
{
|
||||
PC = R0004;
|
||||
call [R0004];
|
||||
}
|
||||
|
||||
# JMP disp32[reg1] - 00000110111RRRRR|ddddddddddddddd0|DDDDDDDDDDDDDDDD
|
||||
:jmp adr32[R0004] is op0515=0x037 & R0004; adr32
|
||||
{
|
||||
local adr = adr32 + R0004;
|
||||
goto [adr];
|
||||
}
|
||||
|
||||
# JR disp22 - 00000111110ddddd|ddddddddddddddd0
|
||||
:jr adr22 is op0615=0x1E ... & adr22
|
||||
{
|
||||
PC = & adr22;
|
||||
goto adr22;
|
||||
}
|
||||
|
||||
# JR disp32 - 0000001011100000|ddddddddddddddd0|DDDDDDDDDDDDDDDD
|
||||
:jr adr32 is op0015=0x2E0; adr32
|
||||
{
|
||||
PC = & adr32;
|
||||
goto adr32;
|
||||
}
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Special #####
|
||||
#####################################################
|
||||
|
||||
|
||||
# CALLT imm6 - 0000001000iiiiii
|
||||
:callt op0005 is op0615=0x8 & op0005
|
||||
{
|
||||
CTPC = inst_next;
|
||||
CTPSW = PSW;
|
||||
local adr:4 = CTBP + (op0005 << 1);
|
||||
PC = CTBP + zext(*:2 adr);
|
||||
call [PC];
|
||||
}
|
||||
|
||||
# CAXI [reg1], reg2, reg3 - rrrrr111111RRRRR|wwwww00011101110
|
||||
:caxi [R0004], R1115, R2731 is op0510=0x3F & R0004 & R1115; op1626=0xEE & R2731
|
||||
{
|
||||
local tkn = *:4 (R0004 & ~(0x3));
|
||||
local result = R1115 - tkn;
|
||||
*:4 R0004 = tkn * zext(result != 0) + R2731 * zext(result == 0);
|
||||
R2731 = tkn;
|
||||
set_general_flags_neg(R1115, tkn);
|
||||
}
|
||||
|
||||
# CTRET - 0000011111100000|0000000101000100
|
||||
:ctret is op0515=0x3F; op1631=0x144
|
||||
{
|
||||
PC = CTPC;
|
||||
PSW = CTPSW;
|
||||
return [PC];
|
||||
}
|
||||
|
||||
# DI - 0000011111100000|0000000101100000
|
||||
define pcodeop __disable_irq;
|
||||
:di is op0015=0x7E0; op1631=0x160
|
||||
{
|
||||
$(ID) = 1;
|
||||
__disable_irq();
|
||||
}
|
||||
|
||||
# DISPOSE imm5, list12 - 0000011001iiiiiL|LLLLLLLLLLL00000
|
||||
:dispose prep0105, DispList is prep0615=0x19 & prep1620=0x0 & prep0105 & DispList
|
||||
{
|
||||
sp = sp + (prep0105 << 2);
|
||||
build DispList;
|
||||
}
|
||||
|
||||
# DISPOSE imm5, list12, [reg1] - 0000011001iiiiiL|LLLLLLLLLLLRRRRR
|
||||
:dispose prep0105, DispList, [prep1620] is prep0615=0x19 & prep1620 & prep0105 & DispList
|
||||
{
|
||||
sp = sp + (prep0105 << 2);
|
||||
build DispList;
|
||||
PC = prep1620;
|
||||
return [PC];
|
||||
}
|
||||
|
||||
# EI - 1000011111100000|0000000101100000
|
||||
define pcodeop __enable_irq;
|
||||
:ei is op0015=0x87E0; op1631=0x160
|
||||
{
|
||||
$(ID) = 0;
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
# EIRET - 0000011111100000|0000000101001000
|
||||
:eiret is op0515=0x3F; op1631=0x148
|
||||
{
|
||||
PC = EIPC;
|
||||
PSW = EIPSW;
|
||||
return [PC];
|
||||
}
|
||||
|
||||
# FERET - 0000011111100000|0000000101001010
|
||||
:feret is op0515=0x3F; op1631=0x14A
|
||||
{
|
||||
PC = FEPC;
|
||||
PSW = FEPSW;
|
||||
return [PC];
|
||||
}
|
||||
|
||||
# FETRAP vector4 - 0vvvv00001000000
|
||||
:fetrap op1114 is op0010=0x40 & op1515=0 & op1114 & op1115!=0
|
||||
{
|
||||
FEPC = inst_next;
|
||||
FEPSW = PSW;
|
||||
$(FECC) = op1114 + 0x30; # exception code 0x30..0x3F
|
||||
FEIC = op1114 + 0x30; # exception code 0x30..0x3F
|
||||
$(EP) = 1;
|
||||
$(ID) = 1;
|
||||
$(NP) = 1;
|
||||
PC = 0x30;
|
||||
goto [PC];
|
||||
}
|
||||
|
||||
# HALT - 0000011111100000|0000000100100000
|
||||
define pcodeop __halt;
|
||||
:halt is op0015=0x7E0; op1631=0x120
|
||||
{
|
||||
__halt();
|
||||
}
|
||||
|
||||
# LDSR reg2, regID - rrrrr111111RRRRR|0000000000100000
|
||||
:ldsr R0004, SR1115 is op0510=0x3F & SR1115 & R0004; op1631=0x20
|
||||
{
|
||||
SR1115 = R0004;
|
||||
}
|
||||
|
||||
# NOP - 0000000000000000
|
||||
:nop is op0015=0x0
|
||||
{
|
||||
PC = inst_next;
|
||||
}
|
||||
|
||||
# PREPARE list12, imm5 - 0000011110iiiiiL|LLLLLLLLLLL00001
|
||||
:prepare PrepList, prep0105 is prep0615=0x1E & prep0105 & prep1620=0x1 & PrepList
|
||||
{
|
||||
build PrepList;
|
||||
sp = sp - (prep0105 << 2);
|
||||
}
|
||||
|
||||
# PREPARE list12, imm5, sp - 0000011110iiiiiL|LLLLLLLLLLL00011
|
||||
:prepare PrepList, prep0105, sp is prep0615=0x1E & prep0105 & prep1620=0x3 & PrepList & sp
|
||||
{
|
||||
build PrepList;
|
||||
sp = sp - (prep0105 << 2);
|
||||
ep = sp;
|
||||
}
|
||||
|
||||
# PREPARE list12, imm5, imm16 (low) - 0000011110iiiiiL|LLLLLLLLLLL01011|iiiiiiiiiiiiiiii
|
||||
:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0xB & PrepList; s3247
|
||||
{
|
||||
build PrepList;
|
||||
sp = sp - (prep0105 << 2);
|
||||
ep = s3247;
|
||||
}
|
||||
|
||||
# PREPARE list12, imm5, imm16 (high) - 0000011110iiiiiL|LLLLLLLLLLL10011|iiiiiiiiiiiiiiii
|
||||
:prepare PrepList, prep0105, s3247 is prep0615=0x1E & prep0105 & prep1620=0x13 & PrepList; s3247
|
||||
{
|
||||
build PrepList;
|
||||
sp = sp - (prep0105 << 2);
|
||||
ep = s3247 << 16;
|
||||
}
|
||||
|
||||
# PREPARE list12, imm5, imm32 - 0000011110iiiiiL|LLLLLLLLLLL11011|iiiiiiiiiiiiiiii|iiiiiiiiiiiiiiii
|
||||
:prepare PrepList, prep0105, imm32 is prep0615=0x1E & prep0105 & prep1620=0x1B & PrepList; op3247; op4863
|
||||
[ imm32 = (op4863 << 16) | op3247; ]
|
||||
{
|
||||
build PrepList;
|
||||
sp = sp - (prep0105 << 2);
|
||||
ep = imm32;
|
||||
}
|
||||
|
||||
# RETI - 0000011111100000|0000000101000000
|
||||
:reti is op0515=0x3F; op1631=0x140
|
||||
{
|
||||
if($(EP)!=1)
|
||||
goto <false>;
|
||||
|
||||
PC = EIPC;
|
||||
PSW = EIPSW;
|
||||
goto <end>;
|
||||
|
||||
<false>
|
||||
if($(NP)!=1)
|
||||
goto <false2>;
|
||||
|
||||
PC = FEPC;
|
||||
PSW = FEPSW;
|
||||
goto <end>;
|
||||
|
||||
<false2>
|
||||
PC = EIPC;
|
||||
PSW = EIPSW;
|
||||
|
||||
<end>
|
||||
return[PC];
|
||||
}
|
||||
|
||||
# RIE - 0000000001000000
|
||||
:rie is op0015=0x40
|
||||
{
|
||||
FEPC = PC;
|
||||
FEPSW = PSW;
|
||||
$(NP) = 1;
|
||||
$(EP) = 1;
|
||||
$(ID) = 1;
|
||||
PC = 0x30;
|
||||
goto [PC];
|
||||
}
|
||||
|
||||
# RIE imm5, imm4 - iiiii1111111IIII|0000000000000000
|
||||
:rie op1115, op0003 is op0410=0x7F & op1115 & op0003; op1631=0x0
|
||||
{
|
||||
FEPC = PC;
|
||||
FEPSW = PSW;
|
||||
$(NP) = 1;
|
||||
$(EP) = 1;
|
||||
$(ID) = 1;
|
||||
PC = 0x30;
|
||||
goto [PC];
|
||||
}
|
||||
|
||||
# STSR regID, reg2 - rrrrr111111RRRRR|0000000001000000
|
||||
:stsr SR0004, R1115 is op0510=0x3F & R1115 & SR0004; op1631=0x40
|
||||
{
|
||||
R1115 = SR0004;
|
||||
}
|
||||
|
||||
# SWITCH reg1 - 00000000010RRRRR
|
||||
:switch R0004 is op0515=0x2 & R0004
|
||||
{
|
||||
local adr:4 = inst_next + (R0004 << 1);
|
||||
PC = inst_next + (sext(*:2 adr) << 1);
|
||||
goto [PC];
|
||||
}
|
||||
|
||||
# SYNCE - 0000000000011101
|
||||
define pcodeop __synchronize;
|
||||
:synce is op0015=0x1D
|
||||
{
|
||||
__synchronize();
|
||||
}
|
||||
|
||||
# SYNCM - 0000000000011110
|
||||
:syncm is op0015=0x1E
|
||||
{
|
||||
__synchronize();
|
||||
}
|
||||
|
||||
# SYNCP - 0000000000011111
|
||||
:syncp is op0015=0x1F
|
||||
{
|
||||
__synchronize();
|
||||
}
|
||||
|
||||
# SYSCALL vector8 - 11010111111vvvvv|00VVV00101100000
|
||||
:syscall vector8 is op0515=0x6BF & op0004; op3031=0 & op2729 & op1626=0x160
|
||||
[ vector8 = (op2729 << 5) | op0004; ]
|
||||
{
|
||||
EIPC = inst_next;
|
||||
EIPSW = PSW;
|
||||
EIIC = vector8 + 0x8000; # exception code 0x8000..0x80FF
|
||||
$(EICC) = vector8 + 0x8000; # exception code 0x8000..0x80FF
|
||||
$(EP) = 1;
|
||||
$(ID) = 1;
|
||||
local adr:4;
|
||||
either_or(adr, (vector8 <= SCCFG), SCBP + (vector8 << 2), SCBP);
|
||||
PC = SCBP + (*:4 adr);
|
||||
call [PC];
|
||||
}
|
||||
|
||||
# TRAP imm5 - 00000111111vvvvv|0000000100000000
|
||||
:trap op0004 is op0515=0x3F & op0004; op1631=0x100
|
||||
{
|
||||
local vector5:4 = op0004;
|
||||
EIPC = inst_next;
|
||||
EIPSW = PSW;
|
||||
EIIC = vector5 + 0x40; # exception code 0x40..0x5F
|
||||
$(EICC) = vector5:2 + 0x40; # exception code 0x40..0x5F
|
||||
$(EP) = 1;
|
||||
$(ID) = 1;
|
||||
either_or(PC, (vector5 <= 15), 0x40, 0x50);
|
||||
call [PC];
|
||||
}
|
||||
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<compiler_spec>
|
||||
|
||||
<global>
|
||||
<range space="ram"/>
|
||||
</global>
|
||||
|
||||
<stackpointer register="sp" space="ram"/>
|
||||
|
||||
<default_proto>
|
||||
<prototype name="__stdcall" extrapop="0" stackshift="0">
|
||||
|
||||
<input>
|
||||
<pentry minsize="1" maxsize="4">
|
||||
<register name="r6"/>
|
||||
</pentry>
|
||||
|
||||
<pentry minsize="1" maxsize="4">
|
||||
<register name="r7"/>
|
||||
</pentry>
|
||||
|
||||
<pentry minsize="1" maxsize="4">
|
||||
<register name="r8"/>
|
||||
</pentry>
|
||||
|
||||
<pentry minsize="1" maxsize="4">
|
||||
<register name="r9"/>
|
||||
</pentry>
|
||||
|
||||
<pentry minsize="1" maxsize="500" align="4">
|
||||
<addr offset="0" space="stack"/>
|
||||
</pentry>
|
||||
</input>
|
||||
|
||||
<output>
|
||||
<pentry minsize="1" maxsize="4">
|
||||
<register name="r10"/>
|
||||
</pentry>
|
||||
|
||||
<pentry minsize="5" maxsize="8">
|
||||
<addr space="join" piece1="r10" piece2="r11"/>
|
||||
</pentry>
|
||||
</output>
|
||||
|
||||
<unaffected>
|
||||
<register name="r20"/>
|
||||
<register name="r21"/>
|
||||
<register name="r22"/>
|
||||
<register name="r23"/>
|
||||
<register name="r24"/>
|
||||
<register name="r25"/>
|
||||
<register name="r26"/>
|
||||
<register name="r27"/>
|
||||
<register name="r28"/>
|
||||
<register name="r29"/>
|
||||
<register name="ep"/>
|
||||
<register name="lp"/>
|
||||
</unaffected>
|
||||
|
||||
</prototype>
|
||||
</default_proto>
|
||||
|
||||
</compiler_spec>
|
||||
@@ -0,0 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<language_definitions>
|
||||
<language processor="V850"
|
||||
endian="little"
|
||||
size="32"
|
||||
variant="E1, E2, E2M"
|
||||
version="1.0"
|
||||
slafile="V850.sla"
|
||||
processorspec="V850.pspec"
|
||||
manualindexfile="../manuals/v850.idx"
|
||||
id="V850:LE:32:default">
|
||||
<description>Renesas V850 family</description>
|
||||
<compiler name="default" spec="V850.cspec" id="default"/>
|
||||
</language>
|
||||
</language_definitions>
|
||||
@@ -0,0 +1,6 @@
|
||||
<opinions>
|
||||
<constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
|
||||
<constraint primary="36" processor="V850" size="32" />
|
||||
<constraint primary="87" processor="V850" size="32" />
|
||||
</constraint>
|
||||
</opinions>
|
||||
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
|
||||
<processor_spec>
|
||||
|
||||
<programcounter register="PC"/>
|
||||
|
||||
<data_space space="ram"/>
|
||||
|
||||
<volatile outputop="write" inputop="read">
|
||||
<range space="ram" first="0x0" last="0x20"/>
|
||||
</volatile>
|
||||
|
||||
</processor_spec>
|
||||
@@ -0,0 +1,37 @@
|
||||
#####################################################
|
||||
##### #####
|
||||
##### V850E2M SLEIGH specification #####
|
||||
##### #####
|
||||
#####################################################
|
||||
|
||||
define endian = little;
|
||||
define alignment = 2;
|
||||
|
||||
# Size & default are required
|
||||
define space ram type=ram_space size=4 default;
|
||||
define space register type=register_space size=4;
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Helpers #####
|
||||
#####################################################
|
||||
|
||||
@include "Helpers/Register.sinc"
|
||||
@include "Helpers/Tokens.sinc"
|
||||
@include "Helpers/Variables.sinc"
|
||||
@include "Helpers/Conditions.sinc"
|
||||
@include "Helpers/Macros.sinc"
|
||||
@include "Helpers/Extras.sinc"
|
||||
|
||||
|
||||
|
||||
#####################################################
|
||||
##### Instructions #####
|
||||
#####################################################
|
||||
|
||||
@include "Instructions/Arithmetic.sinc"
|
||||
@include "Instructions/Float.sinc"
|
||||
@include "Instructions/Load_Store.sinc"
|
||||
@include "Instructions/Logic.sinc"
|
||||
@include "Instructions/Special.sinc"
|
||||
@@ -0,0 +1,174 @@
|
||||
@r01us0001ej0100_v850e2m.pdf [V850E2M User’s Manual: Architecture RENESAS MCU V850E2M Microprocessor Core]
|
||||
|
||||
ADD, 71
|
||||
ADDI, 72
|
||||
ADF, 73
|
||||
AND, 74
|
||||
ANDI, 75
|
||||
Bcond, 76
|
||||
BSH, 78
|
||||
BSW, 79
|
||||
CALLT, 80
|
||||
CAXI, 81
|
||||
CLR1, 82
|
||||
CMOV, 84
|
||||
CMP, 86
|
||||
CTRET, 87
|
||||
DI, 88
|
||||
DISPOSE, 89
|
||||
DIV, 91
|
||||
DIVH, 92
|
||||
DIVHU, 94
|
||||
DIVQ, 95
|
||||
DIVQU, 96
|
||||
DIVU, 97
|
||||
EI, 98
|
||||
EIRET, 99
|
||||
FERET, 100
|
||||
FETRAP, 101
|
||||
HALT, 102
|
||||
HSH, 103
|
||||
HSW, 104
|
||||
JARL, 105
|
||||
JMP, 107
|
||||
JR, 108
|
||||
LD.B, 109
|
||||
LD.BU, 110
|
||||
LD.H, 111
|
||||
LD.HU, 112
|
||||
LD.W, 113
|
||||
LDSR, 114
|
||||
MAC, 115
|
||||
MACU, 116
|
||||
MOV, 117
|
||||
MOVEA, 118
|
||||
MOVHI, 119
|
||||
MUL, 120
|
||||
MULH, 121
|
||||
MULHI, 122
|
||||
MULU, 123
|
||||
NOP, 124
|
||||
NOT, 125
|
||||
NOT1, 126
|
||||
OR, 128
|
||||
ORI, 129
|
||||
PREPARE, 130
|
||||
RETI, 132
|
||||
RIE, 134
|
||||
SAR, 135
|
||||
SASF, 137
|
||||
SATADD, 138
|
||||
SATSUB, 140
|
||||
SATSUBI, 141
|
||||
SATSUBR, 142
|
||||
SBF, 143
|
||||
SCH0L, 144
|
||||
SCH0R, 145
|
||||
SCH1L, 146
|
||||
SCH1R, 147
|
||||
SET1, 148
|
||||
SETF, 150
|
||||
SHL, 152
|
||||
SHR, 154
|
||||
SLD.B, 156
|
||||
SLD.BU, 157
|
||||
SLD.H, 158
|
||||
SLD.HU, 159
|
||||
SLD.W, 160
|
||||
SST.B, 161
|
||||
SST.H, 162
|
||||
SST.W, 163
|
||||
ST.B, 164
|
||||
ST.H, 165
|
||||
ST.W, 166
|
||||
STSR, 167
|
||||
SUB, 168
|
||||
SUBR, 169
|
||||
SWITCH, 170
|
||||
SXB, 171
|
||||
SXH, 172
|
||||
SYNCE, 173
|
||||
SYNCM, 174
|
||||
SYNCP, 175
|
||||
SYSCALL, 176
|
||||
TRAP, 178
|
||||
TST, 179
|
||||
TST1, 180
|
||||
XOR, 181
|
||||
XORI, 182
|
||||
ZXB, 183
|
||||
ZXH, 184
|
||||
|
||||
ABSF.D, 326
|
||||
ABSF.S, 327
|
||||
ADDF.D, 328
|
||||
ADDF.S, 329
|
||||
CEILF.DL, 330
|
||||
CEILF.DUL, 331
|
||||
CEILF.DUW, 332
|
||||
CEILF.DW, 333
|
||||
CEILF.SL, 334
|
||||
CEILF.SUL, 335
|
||||
CEILF.SUW, 336
|
||||
CEILF.SW, 337
|
||||
CMOVF.D, 338
|
||||
CMOVF.S, 339
|
||||
CMPF.D, 340
|
||||
CMPF.S, 343
|
||||
CVTF.DL, 346
|
||||
CVTF.DS, 347
|
||||
CVTF.DUL, 348
|
||||
CVTF.DUW, 349
|
||||
CVTF.DW, 350
|
||||
CVTF.LD, 351
|
||||
CVTF.LS, 352
|
||||
CVTF.SD, 353
|
||||
CVTF.SL, 354
|
||||
CVTF.SUL, 355
|
||||
CVTF.SUW, 356
|
||||
CVTF.SW, 357
|
||||
CVTF.ULD, 358
|
||||
CVTF.ULS, 359
|
||||
CVTF.UWD, 360
|
||||
CVTF.UWS, 361
|
||||
CVTF.WD, 362
|
||||
CVTF.WS, 363
|
||||
DIVF.D, 364
|
||||
DIVF.S, 365
|
||||
FLOORF.DL, 366
|
||||
FLOORF.DUL, 367
|
||||
FLOORF.DUW, 368
|
||||
FLOORF.DW, 369
|
||||
FLOORF.SL, 370
|
||||
FLOORF.SUL, 371
|
||||
FLOORF.SUW, 372
|
||||
FLOORF.SW, 373
|
||||
MADDF.S, 374
|
||||
MAXF.D, 376
|
||||
MAXF.S, 377
|
||||
MINF.D, 378
|
||||
MINF.S, 379
|
||||
MSUBF.S, 380
|
||||
MULF.D, 382
|
||||
MULF.S, 383
|
||||
NEGF.D, 384
|
||||
NEGF.S, 385
|
||||
NMADDF.S, 386
|
||||
NMSUBF.S, 388
|
||||
RECIPF.D, 390
|
||||
RECIPF.S, 391
|
||||
RSQRTF.D, 392
|
||||
RSQRTF.S, 393
|
||||
SQRTF.D, 394
|
||||
SQRTF.S, 395
|
||||
SUBF.D, 396
|
||||
SUBF.S, 397
|
||||
TRFSR, 398
|
||||
TRNCF.DL, 399
|
||||
TRNCF.DUL, 400
|
||||
TRNCF.DUW, 401
|
||||
TRNCF.DW, 402
|
||||
TRNCF.SL, 403
|
||||
TRNCF.SUL, 404
|
||||
TRNCF.SUW, 405
|
||||
TRNCF.SW, 406
|
||||
@@ -0,0 +1,37 @@
|
||||
<patternlist>
|
||||
<patternpairs totalbits="31" postbits="15">
|
||||
<!-- totalbits = total # of bits pre/post that must be a 0/1 not '.' -->
|
||||
<!-- postbits = number of bits that are 0/1 not '.' that must come from post pattern bits -->
|
||||
<prepatterns>
|
||||
<data>01111111 00000000</data> <!-- jmp [lp] -->
|
||||
</prepatterns>
|
||||
<postpatterns>
|
||||
<data>10...... 00000111 ...00001 ........</data> <!-- PREPARE list12, imm5 -->
|
||||
<data>10...... 00000111 ...00011 ........</data> <!-- PREPARE list12, imm5, sp -->
|
||||
<data>00000011 00011110 ........ ........</data> <!-- ADDI imm16, sp, sp -->
|
||||
<data>10...... 00000111 ...01011 ........ ........ ........</data> <!-- PREPARE list12, imm5, simm16 -->
|
||||
<data>10...... 00000111 ...10011 ........ ........ ........</data> <!-- PREPARE list12, imm5, imm16 -->
|
||||
<data>10...... 00000111 ...11011 ........ ........ ........ ........ ........</data> <!-- PREPARE list12, imm5, imm32 -->
|
||||
<codeboundary/>
|
||||
<possiblefuncstart/>
|
||||
</postpatterns>
|
||||
</patternpairs>
|
||||
<patternpairs totalbits="25" postbits="15">
|
||||
<prepatterns>
|
||||
<data>01...... 00000110 ........ ........</data> <!-- DISPOSE imm5, list12, [reg1] -->
|
||||
<data>11100000 00000111 01001010 00000001</data> <!-- FERET -->
|
||||
<data>11100000 00000111 01001000 00000001</data> <!-- EIRET -->
|
||||
<data>11100000 00000111 01000100 00000001</data> <!-- CTRET -->
|
||||
</prepatterns>
|
||||
<postpatterns>
|
||||
<data>10...... 00000111 ...00001 ........</data> <!-- PREPARE list12, imm5 -->
|
||||
<data>10...... 00000111 ...00011 ........</data> <!-- PREPARE list12, imm5, sp -->
|
||||
<data>00000011 00011110 ........ ........</data> <!-- ADDI imm16, sp, sp -->
|
||||
<data>10...... 00000111 ...11011 ........ ........ ........ ........ ........</data> <!-- PREPARE list12, imm5, imm32 -->
|
||||
<data>10...... 00000111 ...01011 ........ ........ ........</data> <!-- PREPARE list12, imm5, simm16 -->
|
||||
<data>10...... 00000111 ...10011 ........ ........ ........</data> <!-- PREPARE list12, imm5, imm16 -->
|
||||
<codeboundary/>
|
||||
<possiblefuncstart/>
|
||||
</postpatterns>
|
||||
</patternpairs>
|
||||
</patternlist>
|
||||
@@ -0,0 +1,5 @@
|
||||
<patternconstraints>
|
||||
<language id="V850:LE:32:default">
|
||||
<patternfile>V850_patterns.xml</patternfile>
|
||||
</language>
|
||||
</patternconstraints>
|
||||
Reference in New Issue
Block a user