diff --git a/Ghidra/Processors/PowerPC/certification.manifest b/Ghidra/Processors/PowerPC/certification.manifest
index c8d1018562..ad290208f0 100644
--- a/Ghidra/Processors/PowerPC/certification.manifest
+++ b/Ghidra/Processors/PowerPC/certification.manifest
@@ -23,6 +23,10 @@ data/languages/ppc_32_4xx_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_be.cspec||GHIDRA||||END|
data/languages/ppc_32_be.slaspec||GHIDRA||||END|
data/languages/ppc_32_be_Mac.cspec||GHIDRA||||END|
+data/languages/ppc_32_e500_be.cspec||GHIDRA||||END|
+data/languages/ppc_32_e500_be.slaspec||GHIDRA||||END|
+data/languages/ppc_32_e500_le.cspec||GHIDRA||||END|
+data/languages/ppc_32_e500_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_le.cspec||GHIDRA||||END|
data/languages/ppc_32_le.slaspec||GHIDRA||||END|
data/languages/ppc_32_mpc8270.pspec||GHIDRA||||END|
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
index a829a66c98..1d3dc8e043 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc.ldefs
@@ -158,7 +158,7 @@
-
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+ PowerQUICC-III e500 32-bit big-endian family
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+ PowerQUICC-III e500 32-bit little-endian family
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diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec
new file mode 100644
index 0000000000..5a9b490d75
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec
@@ -0,0 +1,29 @@
+# SLA specification file for IBM PowerPC e500 series core
+
+# NOTE: This language variant includes some registers and instructions not supported
+# by the actual processor (e.g., floating pointer registers and associated instructions).
+# The actual processor only supports a subset of the registers and instructions implemented.
+
+@define E500
+
+@define ENDIAN "big"
+
+# Although a 32-bit architecture, 64-bit general purpose registers are supported.
+# Language has been modeled using a 64-bit implementation with a 32-bit truncated
+# memory space (see ldefs).
+
+@define REGISTER_SIZE "8"
+@define BIT_64 "64"
+
+@define EATRUNC "ea"
+
+@define CTR_OFFSET "32"
+
+@define NoLegacyIntegerMultiplyAccumulate
+
+@include "ppc_common.sinc"
+@include "quicciii.sinc"
+@include "evx.sinc"
+@include "SPEF_SCR.sinc"
+@include "SPE_EFSD.sinc"
+@include "SPE_EFV.sinc"
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec
new file mode 100644
index 0000000000..616161e5a9
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.cspec
@@ -0,0 +1,79 @@
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diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec
new file mode 100644
index 0000000000..719c022459
--- /dev/null
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec
@@ -0,0 +1,29 @@
+# SLA specification file for IBM PowerPC e500 series core
+
+# NOTE: This language variant includes some registers and instructions not supported
+# by the actual processor (e.g., floating pointer registers and associated instructions).
+# The actual processor only supports a subset of the registers and instructions implemented.
+
+@define E500
+
+@define ENDIAN "little"
+
+# Although a 32-bit architecture, 64-bit general purpose registers are supported.
+# Language has been modeled using a 64-bit implementation with a 32-bit truncated
+# memory space (see ldefs).
+
+@define REGISTER_SIZE "8"
+@define BIT_64 "64"
+
+@define EATRUNC "ea"
+
+@define CTR_OFFSET "32"
+
+@define NoLegacyIntegerMultiplyAccumulate
+
+@include "ppc_common.sinc"
+@include "quicciii.sinc"
+@include "evx.sinc"
+@include "SPEF_SCR.sinc"
+@include "SPE_EFSD.sinc"
+@include "SPE_EFV.sinc"
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
index 0a2514114a..8498e4bdce 100644
--- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
+++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
@@ -18,6 +18,24 @@ define space register type=register_space size=4;
define register offset=0 size=$(REGISTER_SIZE) [
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 ];
+
+@ifdef E500
+# Define 4-byte general purpose sub-registers (LSB) to be used by E500 compiler specification
+# which must restrict parameter/return passing to low 4-bytes of the 8-byte general purpose registers.
+@if ENDIAN == "big"
+define register offset=0 size=4 [
+ _ _r0 _ _r1 _ _r2 _ _r3 _ _r4 _ _r5 _ _r6 _ _r7
+ _ _r8 _ _r9 _ _r10 _ _r11 _ _r12 _ _r13 _ _r14 _ _r15
+ _ _r16 _ _r17 _ _r18 _ _r19 _ _r20 _ _r21 _ _r22 _ _r23
+ _ _r24 _ _r25 _ _r26 _ _r27 _ _r28 _ _r29 _ _r30 _ _r31 ];
+@else
+define register offset=0 size=4 [
+ _r0 _ _r1 _ _r2 _ _r3 _ _r4 _ _r5 _ _r6 _ _r7 _
+ _r8 _ _r9 _ _r10 _ _r11 _ _r12 _ _r13 _ _r14 _ _r15 _
+ _r16 _ _r17 _ _r18 _ _r19 _ _r20 _ _r21 _ _r22 _ _r23 _
+ _r24 _ _r25 _ _r26 _ _r27 _ _r28 _ _r29 _ _r30 _ _r31 _ ];
+@endif
+@endif
# XER flags
define register offset=0x400 size=1 [ xer_so xer_ov xer_ov32 xer_ca xer_ca32 xer_count ];
@@ -1730,7 +1748,8 @@ macro loadRegisterPartial(reg, ea, sa) {
macro storeRegister(reg, ea) {
@ifdef BIT_64
- *:4(ea) = reg:4;
+ tmp:8 = reg; # workaround
+ *:4(ea) = tmp:4;
@else
*:4(ea) = reg;
@endif
@@ -1739,7 +1758,8 @@ macro storeRegister(reg, ea) {
macro storeReg(reg) {
@ifdef BIT_64
- *:4(tea) = reg:4;
+ tmp:8 = reg; # workaround
+ *:4(tea) = tmp:4;
@else
*:4(tea) = reg;
@endif
@@ -1748,7 +1768,8 @@ macro storeReg(reg) {
macro storeRegisterPartial(reg, ea, sa) {
@ifdef BIT_64
- *:4(ea) = reg:4;
+ tmp:8 = reg; # workaround
+ *:4(ea) = tmp:4;
@else
*:4(ea) = reg;
@endif