Robert Resch c5cc91f6f0 [micronova] Add FINAL_VALIDATE_SCHEMA to validate uart (#12350) ...

Co-authored-by: Jonathan Swoboda <154711427+swoboda1337@users.noreply.github.com>

2025-12-07 21:02:05 -05:00

..

common

[micronova] Add FINAL_VALIDATE_SCHEMA to validate uart (#12350)

2025-12-07 21:02:05 -05:00

build_components_base.bk72xx-ard.yaml

Group component tests to reduce CI time (#11134)

2025-10-12 07:21:45 +13:00

build_components_base.esp32-ard.yaml

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build_components_base.esp32-c3-ard.yaml

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build_components_base.esp32-c3-idf.yaml

[tests] Fix ESP32-C3 component test binary size by using larger partition table (#11319)

2025-10-17 20:20:00 +13:00

build_components_base.esp32-c5-idf.yaml

[psram] Add C5 support (#12215)

2025-11-30 23:27:10 -05:00

build_components_base.esp32-c6-idf.yaml

[esp32c6] Add test base file and platformio env (#8973)

2025-05-31 22:50:45 +12:00

build_components_base.esp32-idf.yaml

[ci] Merge components with different buses to reduce CI time (#11251)

2025-10-16 16:36:03 +13:00

build_components_base.esp32-p4-idf.yaml

[tests] Remove extra newline (#9213)

2025-06-26 11:21:19 +00:00

build_components_base.esp32-s2-ard.yaml

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build_components_base.esp32-s2-idf.yaml

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build_components_base.esp32-s3-ard.yaml

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build_components_base.esp32-s3-idf.yaml

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build_components_base.esp8266-ard.yaml

ESP8266: Complete testing mode memory patches with DRAM and Flash (#11427)

2025-10-21 15:26:49 +13:00

build_components_base.host.yaml

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build_components_base.ln882x-ard.yaml

Add support for LN882X Family (with LibreTiny) (#8954)

2025-06-30 16:20:36 +12:00

build_components_base.nrf52-adafruit.yaml

[nrf52, core] nrf52 core based on zephyr (#7049)

2025-07-16 13:00:21 +12:00

build_components_base.nrf52-mcumgr.yaml

[nrf52, core] nrf52 core based on zephyr (#7049)

2025-07-16 13:00:21 +12:00

build_components_base.nrf52-xiao-ble.yaml

[nrf52] add xiao_ble board (#10698)

2025-10-17 09:02:37 -04:00

build_components_base.rp2040-ard.yaml

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build_components_base.rtl87xx-ard.yaml

[mqtt] Enable support for the RTL87XX platform (#7697)

2025-12-01 23:06:47 +00:00

partitions_testing.csv

[ci] Merge components with different buses to reduce CI time (#11251)

2025-10-16 16:36:03 +13:00