diff --git a/Port/Cortex-M/port_cmx.h b/Port/Cortex-M/port_cmx.h
index bec35bb..1411c1b 100644
--- a/Port/Cortex-M/port_cmx.h
+++ b/Port/Cortex-M/port_cmx.h
@@ -3,8 +3,8 @@
  * @file     port_cmx.h
  * @brief    CMSIS Cortex-M Core Port File
  * @author   迟凯峰
- * @version  V2.2.3
- * @date     2026.01.20
+ * @version  V2.2.4
+ * @date     2026.01.23
  ******************************************************************************/
 
 #ifndef __PORT_CMX_H
@@ -55,8 +55,6 @@ typedef s_u32_t  m_rtccount_t;
 
 
 /* Extern */
-extern  s_u32_t  m_basepri;
-
 #if (MCUCFG_PENDSVFIFO_DEPTH > 0)
 extern  s_u32_t  mPendSV_FIFO_DepthMAX;
 extern  void    *mPendSV_FIFO_0[MCUCFG_PENDSVFIFO_DEPTH + 1];
@@ -193,18 +191,12 @@ do{ \
 #define mPendSV_SetPRI()  *(volatile s_u8_t  *)0xE000ED22 = 0xFF
 #define mPendSV_Set()     *(volatile s_u32_t *)0xE000ED04 = 0x10000000
 #define mPendSV_Clear()
-#define mPendSV_INIT() \
-do{ \
-	mPendSV_SetPRI(); \
-	m_basepri <<= 7 - ((*(volatile s_u32_t *)0xE000ED00 >> 8) & 7); \
-	m_basepri--; \
-	m_basepri <<= 1 + ((*(volatile s_u32_t *)0xE000ED00 >> 8) & 7); \
-}while(false)
+#define mPendSV_INIT()    mPendSV_SetPRI()
 
 /* 内核锁 */
 __STATIC_FORCEINLINE void __mu_disable_sysirq(void)
 {
-	__set_BASEPRI(m_basepri);
+	__set_BASEPRI(0xFF);
 	__ASM("dsb");
 	__ASM("isb");
 }
@@ -232,12 +224,7 @@ __STATIC_FORCEINLINE void __mu_disable_sysirq(void)
 	*(volatile s_u32_t *)(0xE000E280 + MCUCFG_XXXx_IRQn / 32 * 4) = 0x01UL << (MCUCFG_XXXx_IRQn % 32)
 */
 #define mPendSV_Clear()
-
-#define mPendSV_INIT() \
-do{ \
-	mPendSV_SetPRI(); \
-	m_basepri = 1 + ((*(volatile s_u32_t *)0xE000ED00 >> 8) & 7); \
-}while(false)
+#define mPendSV_INIT()   mPendSV_SetPRI()
 
 /* 内核锁 */
 #define mSysINT_Disable() \
@@ -395,7 +382,7 @@ __STATIC_INLINE s_u32_t __mx_disable_irq(void)
 __STATIC_INLINE s_u32_t __mx_masking_pri(s_u32_t newpri)
 {
 	register s_u32_t oldpri = __get_BASEPRI();
-	__set_BASEPRI_MAX(newpri << m_basepri);
+	__set_BASEPRI_MAX(newpri << 4);
 	__ASM("dsb");
 	__ASM("isb");
 	return oldpri;