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Andy Piper
fdd0011695
The ChibiOS 21.11.x merge dropped the rev X/Y conditionals upstream, which left our STM32_ENFORCE_H7_REV_XY define a no-op on every H7 board that does not set MCU_CLOCKRATE_MHZ 480. That silently disabled the errata 2.2.15 AXI SRAM read corruption workaround and applied rev V only ODEN, CSICFGR and ADC boost settings to rev X/Y parts. stm32_clock_init() sets the ODEN bit in SYSCFG_PWRCR to put the core into overdrive, which is required above STM32_SYSCLK_MAX_NOBOOST. hal_lld_init() then reset every APB4 peripheral, and SYSCFG is on APB4, so ODEN was cleared while the PLL kept running at the higher rate. The core was left above its VOS1 rating with no indication. The exclusion was already intended: the AHB4 reset above masks off RCC_APB4RSTR_SYSCFGRST, but SYSCFG is not on AHB4 so it had no effect there. On AHB4 that bit is GPIOBRST, which STM32_GPIO_EN_MASK already covers, so that line is left alone. Measured on an STM32H743 rev V at 480 MHz: SYSCFG_PWRCR reads 0x00 after boot without this change and 0x81 with it.