diff --git a/libraries/AP_HAL_ChibiOS/EventSource.cpp b/libraries/AP_HAL_ChibiOS/EventSource.cpp
index 203fd535e37..dfb21919b6b 100644
--- a/libraries/AP_HAL_ChibiOS/EventSource.cpp
+++ b/libraries/AP_HAL_ChibiOS/EventSource.cpp
@@ -24,7 +24,7 @@ void EventSource::signal(uint32_t evt_mask)
     ch_evt_src_.broadcastFlags(evt_mask);
 }
 
-void EventSource::signalI(uint32_t evt_mask)
+__RAMFUNC__ void EventSource::signalI(uint32_t evt_mask)
 {
     chSysLockFromISR();
     ch_evt_src_.broadcastFlagsI(evt_mask);
diff --git a/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.h b/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.h
index ae47c9b1d3a..de0ada91ffd 100644
--- a/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.h
+++ b/libraries/AP_HAL_ChibiOS/HAL_ChibiOS_Class.h
@@ -27,7 +27,6 @@
 #include <stdio.h>
 #include "ch.h"
 #include "hal.h"
-#include "hrt.h"
 
 class HAL_ChibiOS : public AP_HAL::HAL {
 public:
diff --git a/libraries/AP_HAL_ChibiOS/QSPIDevice.cpp b/libraries/AP_HAL_ChibiOS/QSPIDevice.cpp
index 04ec03ce7e0..3af703d06ec 100644
--- a/libraries/AP_HAL_ChibiOS/QSPIDevice.cpp
+++ b/libraries/AP_HAL_ChibiOS/QSPIDevice.cpp
@@ -49,12 +49,12 @@ QSPIDesc QSPIDeviceManager::device_table[] = { HAL_QSPI_DEVICE_LIST };
 #define STR(x) #x
 
 #if (STM32_QSPICLK % HAL_QSPI1_CLK)
-#error "QSPI Clock" STR(STM32_QSPICLK) " needs to be divisible by selected clock" STR(HAL_QSPI1_CLK)
+#error "QSPI Clock" XSTR(STM32_QSPICLK) " needs to be divisible by selected clock" XSTR(HAL_QSPI1_CLK)
 #endif
 
 #if defined(STM32_WSPI_USE_QUADSPI2) && STM32_WSPI_USE_QUADSPI2
 #if (STM32_QSPICLK % HAL_QSPI2_CLK)
-#error "QSPI Clock" STR(STM32_QSPICLK) " needs to be divisible by selected clock" STR(HAL_QSPI2_CLK)
+#error "QSPI Clock" XSTR(STM32_QSPICLK) " needs to be divisible by selected clock" XSTR(HAL_QSPI2_CLK)
 #endif
 #endif
 
diff --git a/libraries/AP_HAL_ChibiOS/RCOutput.cpp b/libraries/AP_HAL_ChibiOS/RCOutput.cpp
index 2f8a0a95329..306b76ed3bd 100644
--- a/libraries/AP_HAL_ChibiOS/RCOutput.cpp
+++ b/libraries/AP_HAL_ChibiOS/RCOutput.cpp
@@ -178,7 +178,7 @@ void RCOutput::rcout_thread()
     }
 }
 
-void RCOutput::dshot_update_tick(void* p)
+__RAMFUNC__ void RCOutput::dshot_update_tick(void* p)
 {
     chSysLockFromISR();
     RCOutput* rcout = (RCOutput*)p;
@@ -1201,7 +1201,7 @@ void RCOutput::dshot_send_groups(uint32_t time_out_us)
 #endif //#ifndef DISABLE_DSHOT
 }
 
-void RCOutput::dshot_send_next_group(void* p)
+__RAMFUNC__ void RCOutput::dshot_send_next_group(void* p)
 {
     chSysLockFromISR();
     RCOutput* rcout = (RCOutput*)p;
@@ -1528,7 +1528,7 @@ void RCOutput::send_pulses_DMAR(pwm_group &group, uint32_t buffer_length)
 /*
   unlock DMA channel after a dshot send completes and no return value is expected
  */
-void RCOutput::dma_unlock(void *p)
+__RAMFUNC__ void RCOutput::dma_unlock(void *p)
 {
     chSysLockFromISR();
     pwm_group *group = (pwm_group *)p;
@@ -1546,7 +1546,7 @@ void RCOutput::dma_unlock(void *p)
 /*
   DMA interrupt handler. Used to mark DMA completed for DShot
  */
-void RCOutput::dma_up_irq_callback(void *p, uint32_t flags)
+__RAMFUNC__ void RCOutput::dma_up_irq_callback(void *p, uint32_t flags)
 {
     pwm_group *group = (pwm_group *)p;
     chSysLockFromISR();
diff --git a/libraries/AP_HAL_ChibiOS/RCOutput_bdshot.cpp b/libraries/AP_HAL_ChibiOS/RCOutput_bdshot.cpp
index fb228e5bf30..4d072c20475 100644
--- a/libraries/AP_HAL_ChibiOS/RCOutput_bdshot.cpp
+++ b/libraries/AP_HAL_ChibiOS/RCOutput_bdshot.cpp
@@ -352,7 +352,7 @@ void RCOutput::bdshot_config_icu_dshot(stm32_tim_t* TIMx, uint8_t chan, uint8_t
 /*
   unlock DMA channel after a bi-directional dshot transaction completes
  */
-void RCOutput::bdshot_finish_dshot_gcr_transaction(void *p)
+__RAMFUNC__ void RCOutput::bdshot_finish_dshot_gcr_transaction(void *p)
 {
     pwm_group *group = (pwm_group *)p;
     chSysLockFromISR();
@@ -456,7 +456,7 @@ uint8_t RCOutput::bdshot_find_next_ic_channel(const pwm_group& group)
 /*
   DMA UP channel interrupt handler. Used to mark DMA send completed for DShot
  */
-void RCOutput::dma_up_irq_callback(void *p, uint32_t flags)
+__RAMFUNC__ void RCOutput::dma_up_irq_callback(void *p, uint32_t flags)
 {
     pwm_group *group = (pwm_group *)p;
     chSysLockFromISR();
@@ -496,7 +496,7 @@ void RCOutput::dma_up_irq_callback(void *p, uint32_t flags)
 }
 
 // DMA IC channel handler. Used to mark DMA receive completed for DShot
-void RCOutput::bdshot_dma_ic_irq_callback(void *p, uint32_t flags)
+__RAMFUNC__ void RCOutput::bdshot_dma_ic_irq_callback(void *p, uint32_t flags)
 {
     chSysLockFromISR();
 
diff --git a/libraries/AP_HAL_ChibiOS/Scheduler.cpp b/libraries/AP_HAL_ChibiOS/Scheduler.cpp
index c03b89b0e79..3224a191a6e 100644
--- a/libraries/AP_HAL_ChibiOS/Scheduler.cpp
+++ b/libraries/AP_HAL_ChibiOS/Scheduler.cpp
@@ -39,6 +39,7 @@
 #include "hwdef/common/watchdog.h"
 #include <AP_Filesystem/AP_Filesystem.h>
 #include "shared_dma.h"
+#include <AP_Common/ExpandingString.h>
 
 #if HAL_WITH_IO_MCU
 #include <AP_IOMCU/AP_IOMCU.h>
diff --git a/libraries/AP_HAL_ChibiOS/Storage.cpp b/libraries/AP_HAL_ChibiOS/Storage.cpp
index 10661d8c507..4bcd9744c24 100644
--- a/libraries/AP_HAL_ChibiOS/Storage.cpp
+++ b/libraries/AP_HAL_ChibiOS/Storage.cpp
@@ -442,6 +442,12 @@ bool Storage::_flash_erase_ok(void)
  */
 bool Storage::healthy(void)
 {
+#ifdef USE_POSIX
+    // SD card storage is really slow
+    if (_initialisedType == StorageBackend::SDCard) {
+        return log_fd != -1 || AP_HAL::millis() - _last_empty_ms < 30000U;
+    }
+#endif
     return ((_initialisedType != StorageBackend::None) &&
             (AP_HAL::millis() - _last_empty_ms < 2000u));
 }
diff --git a/libraries/AP_HAL_ChibiOS/Storage.h b/libraries/AP_HAL_ChibiOS/Storage.h
index d61cd4a6bb3..3e216dea340 100644
--- a/libraries/AP_HAL_ChibiOS/Storage.h
+++ b/libraries/AP_HAL_ChibiOS/Storage.h
@@ -29,7 +29,13 @@
 
 // when using flash storage we use a small line size to make storage
 // compact and minimise the number of erase cycles needed
+#ifdef STORAGE_FLASH_PAGE
 #define CH_STORAGE_LINE_SHIFT 3
+#elif defined(USE_POSIX)
+#define CH_STORAGE_LINE_SHIFT 9
+#else
+#define CH_STORAGE_LINE_SHIFT 3
+#endif
 
 #define CH_STORAGE_LINE_SIZE (1<<CH_STORAGE_LINE_SHIFT)
 #define CH_STORAGE_NUM_LINES (CH_STORAGE_SIZE/CH_STORAGE_LINE_SIZE)
diff --git a/libraries/AP_HAL_ChibiOS/UARTDriver.cpp b/libraries/AP_HAL_ChibiOS/UARTDriver.cpp
index 33d3193cc3a..33850d1f1c6 100644
--- a/libraries/AP_HAL_ChibiOS/UARTDriver.cpp
+++ b/libraries/AP_HAL_ChibiOS/UARTDriver.cpp
@@ -549,7 +549,7 @@ void UARTDriver::rx_irq_cb(void* self)
 /*
   handle a RX DMA full interrupt
  */
-void UARTDriver::rxbuff_full_irq(void* self, uint32_t flags)
+__RAMFUNC__ void UARTDriver::rxbuff_full_irq(void* self, uint32_t flags)
 {
 #if HAL_USE_SERIAL == TRUE
     UARTDriver* uart_drv = (UARTDriver*)self;
@@ -895,7 +895,7 @@ bool UARTDriver::wait_timeout(uint16_t n, uint32_t timeout_ms)
 /*
   DMA transmit completion interrupt handler
  */
-void UARTDriver::tx_complete(void* self, uint32_t flags)
+__RAMFUNC__ void UARTDriver::tx_complete(void* self, uint32_t flags)
 {
     UARTDriver* uart_drv = (UARTDriver*)self;
     chSysLockFromISR();
@@ -1419,7 +1419,7 @@ void UARTDriver::set_flow_control(enum flow_control flowcontrol)
   software update of rts line. We don't use the HW support for RTS as
   it has no hysteresis, so it ends up toggling RTS on every byte
  */
-void UARTDriver::update_rts_line(void)
+__RAMFUNC__ void UARTDriver::update_rts_line(void)
 {
     if (arts_line == 0 || _flow_control == FLOW_CONTROL_DISABLE) {
         return;
@@ -1546,7 +1546,7 @@ void UARTDriver::set_stop_bits(int n)
 
 
 // record timestamp of new incoming data
-void UARTDriver::receive_timestamp_update(void)
+__RAMFUNC__ void UARTDriver::receive_timestamp_update(void)
 {
     _receive_timestamp[_receive_timestamp_idx^1] = AP_HAL::micros64();
     _receive_timestamp_idx ^= 1;
diff --git a/libraries/AP_HAL_ChibiOS/Util.cpp b/libraries/AP_HAL_ChibiOS/Util.cpp
index a81ec5d2b12..8017bd5b914 100644
--- a/libraries/AP_HAL_ChibiOS/Util.cpp
+++ b/libraries/AP_HAL_ChibiOS/Util.cpp
@@ -376,7 +376,7 @@ bool Util::was_watchdog_reset() const
 /*
   display stack usage as text buffer for @SYS/threads.txt
  */
-void Util::thread_info(ExpandingString &str)
+__RAMFUNC__ void Util::thread_info(ExpandingString &str)
 {
 #if HAL_ENABLE_THREAD_STATISTICS
     uint64_t cumulative_cycles = ch.kernel_stats.m_crit_isr.cumulative;
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/DevEBoxH7v2/hwdef-bl.dat b/libraries/AP_HAL_ChibiOS/hwdef/DevEBoxH7v2/hwdef-bl.dat
new file mode 100644
index 00000000000..87c992d08e2
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/DevEBoxH7v2/hwdef-bl.dat
@@ -0,0 +1,60 @@
+# hw definition file for processing by chibios_pins.py
+# for DevEBox H7 hardware.
+
+# MCU class and specific type
+MCU STM32H7xx STM32H750xx
+
+# board ID for firmware load
+APJ_BOARD_ID 1061
+
+# crystal frequency, setup to use external oscillator
+OSCILLATOR_HZ 25000000
+
+FLASH_SIZE_KB 128
+FLASH_RESERVE_START_KB 0
+FLASH_RESERVE_END_KB 0
+FLASH_BOOTLOADER_LOAD_KB 128
+
+# 8mb external flash
+EXT_FLASH_SIZE_MB 8
+EXT_FLASH_RESERVE_START_KB 1024
+EXT_FLASH_RESERVE_END_KB 448
+
+# order of UARTs (and USB). Allow bootloading on USB and telem1
+SERIAL_ORDER OTG1 USART1 UART7
+
+# UART7 is debug
+PE7 UART7_RX UART7 NODMA
+PE8 UART7_TX UART7 NODMA
+define BOOTLOADER_DEBUG SD7
+
+# QuadSPI Flash
+PD11 QUADSPI_BK1_IO0 QUADSPI1
+PD12 QUADSPI_BK1_IO1 QUADSPI1
+PE2 QUADSPI_BK1_IO2 QUADSPI1
+PD13 QUADSPI_BK1_IO3 QUADSPI1
+PB6 QUADSPI_BK1_NCS QUADSPI1
+PB2 QUADSPI_CLK QUADSPI1
+
+# IFace  Device Name  Bus      QSPI Mode  Clk Freq  Size (Pow2)  NCS Delay
+QSPIDEV  w25q         QUADSPI1 MODE3      120*MHZ   23           2
+
+# USART1
+PA10 USART1_RX USART1
+PA9  USART1_TX USART1
+
+# USB
+PA11 OTG_FS_DM OTG1
+PA12 OTG_FS_DP OTG1
+
+PA13 JTMS-SWDIO SWD
+PA14 JTCK-SWCLK SWD
+
+PA1 LED_BOOTLOADER OUTPUT LOW
+define HAL_LED_ON 0
+
+define HAL_USE_EMPTY_STORAGE 1
+define HAL_STORAGE_SIZE 16384
+
+# Add CS pins to ensure they are high in bootloader
+PA4 MPU6000_CS CS
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/DevEBoxH7v2/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/DevEBoxH7v2/hwdef.dat
new file mode 100644
index 00000000000..175d3b6c682
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/DevEBoxH7v2/hwdef.dat
@@ -0,0 +1,137 @@
+# hw definition file for processing by chibios_pins.py
+# for DevEBox H7 hardware based on SPRacingH7 pinout
+# configured to boot from external flash
+
+# MCU class and specific type
+MCU STM32H7xx STM32H750xx
+
+# board ID for firmware load
+APJ_BOARD_ID 1061
+
+# crystal frequency, setup to use external oscillator
+OSCILLATOR_HZ 25000000
+
+STM32_ST_USE_TIMER 2
+
+# reserve 256 bytes for comms between app and bootloader
+RAM_RESERVE_START 256
+
+define NO_DATAFLASH TRUE
+
+FLASH_SIZE_KB 128
+FLASH_RESERVE_START_KB 0
+
+EXT_FLASH_SIZE_MB 8
+EXT_FLASH_RESERVE_START_KB 1024
+EXT_FLASH_RESERVE_END_KB 448
+
+# only one I2C bus
+I2C_ORDER I2C1
+
+# order of UARTs (and USB)
+SERIAL_ORDER OTG1 USART1 USART2 USART3 UART4 UART5 EMPTY EMPTY UART8
+
+# Buzzer - DMA timer channel use by LEDs
+PD7 BUZZER OUTPUT GPIO(80) LOW
+define HAL_BUZZER_PIN 80
+define HAL_BUZZER_ON 1
+define HAL_BUZZER_OFF 0
+
+# USB
+PA11 OTG_FS_DM OTG1
+PA12 OTG_FS_DP OTG1
+
+# Debug
+PA13 JTMS-SWDIO SWD
+PA14 JTCK-SWCLK SWD
+
+# SPI3 MPU6500 #1
+PA15 MPU6500_1_CS CS
+PB3 SPI3_SCK SPI3
+PB4 SPI3_MISO SPI3
+PD6 SPI3_MOSI SPI3
+
+# I2C1 for baro
+PB8 I2C1_SCL I2C1 PULLUP
+PB9 I2C1_SDA I2C1 PULLUP
+
+PC1 BATT_VOLTAGE_SENS ADC1 SCALE(1)
+PC0 BATT_CURRENT_SENS ADC1 SCALE(1)
+
+PC4 RSSI_IN ADC1
+define BOARD_RSSI_ANA_PIN 0
+
+# define default battery setup
+define HAL_BATT_VOLT_PIN 13
+define HAL_BATT_CURR_PIN 12
+define HAL_BATT_VOLT_SCALE 10.9
+define HAL_BATT_CURR_SCALE 28.5
+define HAL_BATT_MONITOR_DEFAULT 4
+
+PC5 RSSI_ADC ADC1
+
+# USART1
+PB15 USART1_RX USART1
+PB14 USART1_TX USART1
+
+# USART2 (RCIN)
+PD5 USART2_TX USART2
+PD6 USART2_RX USART2 ALT(1)
+define HAL_SERIAL2_PROTOCOL SerialProtocol_RCIN
+
+# USART3
+PD9 USART3_RX USART3
+PD8 USART3_TX USART3
+
+# UART4
+PD0 UART4_RX UART4
+PD1 UART4_TX UART4
+
+# UART5
+PB5 UART5_RX UART5
+PB13 UART5_TX UART5
+
+# UART8
+PE0 UART8_RX UART8
+PE1 UART8_TX UART8
+
+# SD card
+PC8 SDMMC1_D0 SDMMC1
+PC9 SDMMC1_D1 SDMMC1
+PC10 SDMMC1_D2 SDMMC1
+PC11 SDMMC1_D3 SDMMC1
+PC12 SDMMC1_CK SDMMC1
+PD2 SDMMC1_CMD SDMMC1
+
+# QuadSPI Flash
+PD11 QUADSPI_BK1_IO0 QUADSPI1
+PD12 QUADSPI_BK1_IO1 QUADSPI1
+PE2 QUADSPI_BK1_IO2 QUADSPI1
+PD13 QUADSPI_BK1_IO3 QUADSPI1
+PB6 QUADSPI_BK1_NCS QUADSPI1
+PB2 QUADSPI_CLK QUADSPI1
+
+# Motors
+PA0  TIM5_CH1 TIM5 PWM(1) GPIO(50)          # M1
+PH11 TIM5_CH2 TIM5 PWM(2) GPIO(51)          # M2
+PA2  TIM5_CH3 TIM5 PWM(3) GPIO(52)          # M3
+PA3  TIM5_CH4 TIM5 PWM(4) GPIO(53)          # M4
+
+PA1 LED0 OUTPUT LOW GPIO(90) # Blue LED
+
+define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE
+define ALLOW_ARM_NO_COMPASS
+define HAL_BARO_ALLOW_INIT_NO_BARO
+
+define HAL_OS_FATFS_IO 1
+define HAL_BOARD_LOG_DIRECTORY "/APM/LOGS"
+define HAL_BOARD_TERRAIN_DIRECTORY "/APM/TERRAIN"
+
+define BOARD_PWM_COUNT_DEFAULT 4
+
+define HAL_USE_EMPTY_STORAGE 1
+#define STORAGE_FLASH_PAGE 14
+define HAL_STORAGE_SIZE 16384
+
+# Nucleo LED
+PB0 LED1 OUTPUT LOW
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef-bl.dat b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef-bl.dat
index 0c22b073f4c..f7b17ad64a1 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef-bl.dat
+++ b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef-bl.dat
@@ -25,7 +25,7 @@ FLASH_SIZE_KB 2048
 # setup build for a peripheral firmware
 env AP_PERIPH 1
 
-EXTERNAL_PROG_FLASH_MB 32
+EXT_FLASH_SIZE_MB 32
 
 # bootloader is installed at zero offset
 FLASH_RESERVE_START_KB 0
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef.dat
index 6ed0626068a..20714712df3 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef.dat
+++ b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL/hwdef.dat
@@ -82,4 +82,4 @@ PB2 QUADSPI_CLK QUADSPI1
 
 define CAN_APP_NODE_NAME "org.cubepilot.H757"
 
-EXTERNAL_PROG_FLASH_MB 32
+EXT_FLASH_SIZE_MB 32
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef-bl.dat b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef-bl.dat
index b895b51d9ad..a335710110f 100755
--- a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef-bl.dat
+++ b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef-bl.dat
@@ -25,7 +25,7 @@ FLASH_SIZE_KB 2048
 # setup build for a peripheral firmware
 env AP_PERIPH 1
 
-# EXTERNAL_PROG_FLASH_MB 32
+# EXT_FLASH_SIZE_MB 32
 
 # bootloader is installed at zero offset
 FLASH_RESERVE_START_KB 0
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef.dat
index b7a5bc75209..828d25435a3 100755
--- a/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef.dat
+++ b/libraries/AP_HAL_ChibiOS/hwdef/H757I_EVAL_intf/hwdef.dat
@@ -82,4 +82,4 @@ PB2 QUADSPI_CLK QUADSPI1
 
 define CAN_APP_NODE_NAME "org.cubepilot.H757"
 
-# EXTERNAL_PROG_FLASH_MB 32
+# EXT_FLASH_SIZE_MB 32
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/defaults.parm b/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/defaults.parm
new file mode 100644
index 00000000000..e8a9591241f
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/defaults.parm
@@ -0,0 +1,6 @@
+# setup for LEDs on chan5
+SERVO11_FUNCTION 120
+NTF_LED_TYPES 257
+
+# setup SERIAL2 for RCIN
+SERIAL2_BAUD 115
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/hwdef-bl.dat b/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/hwdef-bl.dat
new file mode 100644
index 00000000000..ad8e463be88
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/hwdef-bl.dat
@@ -0,0 +1,58 @@
+# hw definition file for processing by chibios_pins.py
+# for SP/Racing Extreme H7 hardware.
+
+# MCU class and specific type
+MCU STM32H7xx STM32H750xx
+
+# board ID for firmware load
+APJ_BOARD_ID 1060
+
+# crystal frequency, setup to use external oscillator
+OSCILLATOR_HZ 8000000
+
+# limited flash that can't be used
+FLASH_SIZE_KB 128
+FLASH_RESERVE_START_KB 0
+FLASH_RESERVE_END_KB 0
+FLASH_BOOTLOADER_LOAD_KB 128
+
+# 16mb external flash
+EXT_FLASH_SIZE_MB 16
+EXT_FLASH_RESERVE_START_KB 1024
+EXT_FLASH_RESERVE_END_KB 448
+
+# order of UARTs (and USB). Allow bootloading on USB and telem1
+SERIAL_ORDER OTG1 USART1
+
+# USART1
+PB15 USART1_RX USART1
+PB14 USART1_TX USART1
+
+# USB
+PA11 OTG_FS_DM OTG1
+PA12 OTG_FS_DP OTG1
+
+PA13 JTMS-SWDIO SWD
+PA14 JTCK-SWCLK SWD
+
+PE3 LED_BOOTLOADER OUTPUT LOW # Blue LED
+define HAL_LED_ON 0
+
+# QuadSPI Flash
+PD11 QUADSPI_BK1_IO0 QUADSPI1
+PD12 QUADSPI_BK1_IO1 QUADSPI1
+PE2 QUADSPI_BK1_IO2 QUADSPI1
+PD13 QUADSPI_BK1_IO3 QUADSPI1
+PB10 QUADSPI_BK1_NCS QUADSPI1
+PB2 QUADSPI_CLK QUADSPI1
+
+# IFace  Device Name  Bus      QSPI Mode  Clk Freq  Size (Pow2)  NCS Delay
+QSPIDEV  w25q         QUADSPI1 MODE3      120*MHZ   24           2
+
+define HAL_USE_EMPTY_STORAGE 1
+define HAL_STORAGE_SIZE 16384
+
+# Add CS pins to ensure they are high in bootloader
+PB12 ICM20602_2_CS CS
+PA15 ICM20602_1_CS CS
+PE11 AT7456E_CS CS
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/hwdef.dat b/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/hwdef.dat
new file mode 100644
index 00000000000..103c4090b20
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/SPRacingH7/hwdef.dat
@@ -0,0 +1,174 @@
+# hw definition file for processing by chibios_pins.py
+# for SP/Racing Extreme H7 hardware.
+# thanks to betaflight for pin information
+
+# MCU class and specific type
+MCU STM32H7xx STM32H750xx
+
+# board ID for firmware load
+APJ_BOARD_ID 1060
+
+# crystal frequency, setup to use external oscillator
+OSCILLATOR_HZ 8000000
+
+env OPTIMIZE -O2
+
+STM32_ST_USE_TIMER 2
+
+# internal flash is off limits
+FLASH_SIZE_KB 128
+FLASH_RESERVE_START_KB 0
+
+EXT_FLASH_SIZE_MB 16
+EXT_FLASH_RESERVE_START_KB 1024
+EXT_FLASH_RESERVE_END_KB 448
+
+# only one I2C bus
+I2C_ORDER I2C1
+
+# order of UARTs (and USB)
+SERIAL_ORDER OTG1 USART1 USART2 USART3 UART4 UART5 EMPTY EMPTY UART8
+
+# Buzzer - DMA timer channel use by LEDs
+PD7 BUZZER OUTPUT GPIO(80) LOW
+define HAL_BUZZER_PIN 80
+define HAL_BUZZER_ON 1
+define HAL_BUZZER_OFF 0
+
+# USB
+PA11 OTG_FS_DM OTG1
+PA12 OTG_FS_DP OTG1
+
+# Debug
+PA13 JTMS-SWDIO SWD
+PA14 JTCK-SWCLK SWD
+
+# SPI2 ICM20602  #2
+PB12 ICM20602_2_CS CS
+PD3 SPI2_SCK SPI2
+PC2 SPI2_MISO SPI2
+PC3 SPI2_MOSI SPI2
+
+# SPI3 ICM20602  #1
+PA15 ICM20602_1_CS CS
+PB3 SPI3_SCK SPI3
+PB4 SPI3_MISO SPI3
+PD6 SPI3_MOSI SPI3
+
+# SPI4 for OSD
+PE11 AT7456E_CS CS
+PE12 SPI4_SCK SPI4
+PE13 SPI4_MISO SPI4
+PE14 SPI4_MOSI SPI4
+
+# I2C1 for baro
+PB8 I2C1_SCL I2C1 PULLUP
+PB9 I2C1_SDA I2C1 PULLUP
+
+PC1 BATT_VOLTAGE_SENS ADC1 SCALE(1)
+PC0 BATT_CURRENT_SENS ADC1 SCALE(1)
+
+PC4 RSSI_IN ADC1
+define BOARD_RSSI_ANA_PIN 0
+
+# define default battery setup
+define HAL_BATT_VOLT_PIN 13
+define HAL_BATT_CURR_PIN 12
+define HAL_BATT_VOLT_SCALE 10.9
+define HAL_BATT_CURR_SCALE 28.5
+define HAL_BATT_MONITOR_DEFAULT 4
+
+PC5 RSSI_ADC ADC1
+
+# USART1
+PB15 USART1_RX USART1
+PB14 USART1_TX USART1
+
+# USART2 (RCIN)
+PD5 USART2_TX USART2
+PD6 USART2_RX USART2 ALT(1)
+define HAL_SERIAL2_PROTOCOL SerialProtocol_RCIN
+
+# USART3
+PD9 USART3_RX USART3
+PD8 USART3_TX USART3
+
+# UART4
+PD0 UART4_RX UART4
+PD1 UART4_TX UART4
+
+# UART5
+PB5 UART5_RX UART5
+PB13 UART5_TX UART5
+
+# UART8
+PE0 UART8_RX UART8
+PE1 UART8_TX UART8
+
+# SD card
+PC8 SDMMC1_D0 SDMMC1
+PC9 SDMMC1_D1 SDMMC1
+PC10 SDMMC1_D2 SDMMC1
+PC11 SDMMC1_D3 SDMMC1
+PC12 SDMMC1_CK SDMMC1
+PD2 SDMMC1_CMD SDMMC1
+
+# QuadSPI Flash
+PD11 QUADSPI_BK1_IO0 QUADSPI1
+PD12 QUADSPI_BK1_IO1 QUADSPI1
+PE2 QUADSPI_BK1_IO2 QUADSPI1
+PD13 QUADSPI_BK1_IO3 QUADSPI1
+PB10 QUADSPI_BK1_NCS QUADSPI1
+PB2 QUADSPI_CLK QUADSPI1
+
+# Motors
+PA0  TIM5_CH1 TIM5 PWM(1) GPIO(50) BIDIR    # M1
+PA1  TIM5_CH2 TIM5 PWM(2) GPIO(51)          # M2
+PA2  TIM5_CH3 TIM5 PWM(3) GPIO(52) BIDIR    # M3
+PA3  TIM5_CH4 TIM5 PWM(4) GPIO(53)          # M4
+
+PB6  TIM4_CH1 TIM4 PWM(5) GPIO(54)          # M5
+PB7  TIM4_CH2 TIM4 PWM(6) GPIO(55)          # M6
+
+PC6  TIM8_CH1 TIM8 PWM(7) GPIO(56)          # M7
+PC7  TIM8_CH2 TIM8 PWM(8) GPIO(57)          # M8
+
+PD14 TIM4_CH3 TIM4 PWM(9) GPIO(58)          # M9
+PD15 TIM4_CH4 TIM4 PWM(10) GPIO(59)         # M10
+
+# NeoPixel LED strip
+PA8 TIM1_CH1 TIM1 PWM(11) GPIO(60)
+PE3 LED0 OUTPUT LOW GPIO(90) # Blue LED
+
+# spi devices
+SPIDEV icm20602_1 SPI3 DEVID1 ICM20602_1_CS MODE3  2*MHZ  10*MHZ
+SPIDEV icm20602_2 SPI2 DEVID2 ICM20602_2_CS MODE3  2*MHZ  10*MHZ
+SPIDEV osd       SPI4 DEVID4 AT7456E_CS MODE0 10*MHZ 10*MHZ
+
+DMA_PRIORITY SPI3* SPI2* TIM5*
+
+define HAL_COMPASS_DEFAULT HAL_COMPASS_NONE
+define ALLOW_ARM_NO_COMPASS
+define HAL_PROBE_EXTERNAL_I2C_COMPASSES
+
+# two IMUs
+IMU Invensense SPI:icm20602_1 ROTATION_YAW_90
+IMU Invensense SPI:icm20602_2 ROTATION_YAW_135
+define HAL_DEFAULT_INS_FAST_SAMPLE 3
+
+# one BARO
+BARO BMP388 I2C:0:0x76
+
+# setup for OSD
+define OSD_ENABLED 1
+define HAL_OSD_TYPE_DEFAULT 1
+ROMFS_WILDCARD libraries/AP_OSD/fonts/font*.bin
+
+define HAL_OS_FATFS_IO 1
+define HAL_BOARD_LOG_DIRECTORY "/APM/LOGS"
+define HAL_BOARD_TERRAIN_DIRECTORY "/APM/TERRAIN"
+
+define BOARD_PWM_COUNT_DEFAULT 11
+define STM32_PWM_USE_ADVANCED TRUE
+
+define HAL_STORAGE_SIZE 16384
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/board.c b/libraries/AP_HAL_ChibiOS/hwdef/common/board.c
index c35969a0d65..5c2fb63a01c 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/common/board.c
+++ b/libraries/AP_HAL_ChibiOS/hwdef/common/board.c
@@ -171,7 +171,7 @@ static void stm32_gpio_init(void) {
   /* Enabling GPIO-related clocks, the mask comes from the
      registry header file.*/
 #if defined(STM32H7)
-#if !EXTERNAL_PROG_FLASH_MB // if we have external flash resetting GPIO might disable all comms with it
+#if !EXT_FLASH_SIZE_MB // if we have external flash resetting GPIO might disable all comms with it
   rccResetAHB4(STM32_GPIO_EN_MASK);
 #endif
   rccEnableAHB4(STM32_GPIO_EN_MASK, true);
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/common_extf.ld b/libraries/AP_HAL_ChibiOS/hwdef/common/common_extf.ld
index 0978493476c..80b9b313c42 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/common/common_extf.ld
+++ b/libraries/AP_HAL_ChibiOS/hwdef/common/common_extf.ld
@@ -19,13 +19,17 @@
     generated from hwdef.dat
 */
 
+/* RAM region to be used for fast code. */
+REGION_ALIAS("FASTCODE_RAM", ram1)
+
+/* stack areas are configured to be in AXI RAM (ram1) to ensure the SSBL will load the image */
 /* RAM region to be used for Main stack. This stack accommodates the processing
    of all exceptions and interrupts*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
+REGION_ALIAS("MAIN_STACK_RAM", ram1);
 
 /* RAM region to be used for the process stack. This is the stack used by
    the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+REGION_ALIAS("PROCESS_STACK_RAM", ram1);
 
 /* RAM region to be used for data segment.*/
 REGION_ALIAS("DATA_RAM", ram0);
@@ -40,6 +44,17 @@ __ram0_start__          = ORIGIN(ram0);
 __ram0_size__           = LENGTH(ram0);
 __ram0_end__            = __ram0_start__ + __ram0_size__;
 
+/* AXI */
+__ram1_start__          = ORIGIN(ram1);
+__ram1_size__           = LENGTH(ram1);
+__ram1_end__            = __ram1_start__ + __ram1_size__;
+
+/* DTCM */
+__ram2_start__          = ORIGIN(ram2);
+__ram2_size__           = LENGTH(ram2);
+__ram2_end__            = __ram2_start__ + __ram2_size__;
+
+/* ITCM */
 __instram_start__      = ORIGIN(instram);
 __instram_size__       = LENGTH(instram);
 __instram_end__        = __instram_start__ + __instram_size__;
@@ -72,18 +87,124 @@ SECTIONS
         __fini_array_end__ = .;
     } > default_flash
 
-    .ramfunc : ALIGN(4) SUBALIGN(4)
+    /* INSTRUCTION_RAM area is fast-access ITCM used for RAM-based code, 64k on H7 */
+    .fastramfunc : ALIGN(4) SUBALIGN(4)
     {
         . = ALIGN(4);
-        __instram_init_text__ = LOADADDR(.ramfunc);
+        __instram_init_text__ = LOADADDR(.fastramfunc);
         __instram_init__ = .;
+        /* ChibiOS won't boot unless these are excluded */
         EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o)
-        *libch.a:*(.text .text.* .rodata .rodata.* .glue_7t .glue_7 .gcc*)
-        *(.ramfunc)
+        /* performance critical sections of ChibiOS */
+        *libch.a:ch*.*(.text*)
+        *libch.a:nvic.*(.text*)
+        *libch.a:bouncebuffer.*(.text*)
+        *libch.a:stm32_util.*(.text*)
+        *libch.a:stm32_dma.*(.text*)
+        *libch.a:memstreams.*(.text*)
+        *libch.a:malloc.*(.text*)
+        *libch.a:hrt.*(.text*)
+        *libch.a:hal*.*(.text*)
+        /* a selection of performance critical functions driven CPUInfo results */
+        lib/lib*.a:Semaphores.*(.text*)
+        lib/lib*.a:AP_Math.*(.text*)
+        lib/lib*.a:vector3.*(.text*)
+        lib/lib*.a:matrix3.*(.text*)
+        /* only used on debug builds */
+        *libg_nano.a:*memset*(.text*)
+        *libg_nano.a:*memcpy*(.text*)
+        *libm.a:*(.text*)
+        /* For some reason boards won't boot if libc is in RAM, but will with debug on */
+        /**libc_nano.a:*(.text* .rodata*)
+        *libstdc++_nano.a:(.text* .rodata*)*/
+        *(.fastramfunc)
         . = ALIGN(4);
         __instram_end__ = .;
     } > instram AT > default_flash
 
+    /* FLASH_RAM area is primarily used for RAM-based code and data, 256k allocation on H7 */
+    .ramfunc : ALIGN(4) SUBALIGN(4)
+    {
+        . = ALIGN(4);
+        __ram1_init_text__ = LOADADDR(.ramfunc);
+        __ram1_init__ = .;
+        /* ChibiOS won't boot unless these are excluded */
+        EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o)
+        /*libch.a:*(.text* .rodata* .glue_7t .glue_7 .gcc*)*/
+        /* a selection of larger performance critical functions */
+        lib/lib*.a:*Filter.*(.text* .rodata*)
+        lib/lib*.a:*Filter2p.*(.text* .rodata*)
+        lib/lib*.a:SPIDevice.*(.text* .rodata*)
+        lib/lib*.a:Util.*(.text* .rodata*)
+        lib/lib*.a:Device.*(.text* .rodata*)
+        lib/lib*.a:Scheduler.*(.text* .rodata*)
+        lib/lib*.a:shared_dma.*(.text* .rodata*)
+        lib/lib*.a:RingBuffer.*(.text* .rodata*)
+        lib/lib*.a:crc.*(.text* .rodata*)
+        lib/lib*.a:matrixN.*(.text* .rodata*)
+        lib/lib*.a:matrix_alg.*(.text* .rodata*)
+        lib/lib*.a:AP_NavEKF*.*(.text* .rodata*)
+        lib/lib*.a:EKFGSF*.*(.text* .rodata*)
+        lib/lib*.a:vector2.*(.text* .rodata*)
+        lib/lib*.a:quaternion.*(.text* .rodata*)
+        lib/lib*.a:polygon.*(.text* .rodata*)
+        /* uncomment these to test CPUInfo in FLASH_RAM */
+        /*Tools/CPUInfo/CPUInfo.*(.text* .rodata*)
+        Tools/CPUInfo/EKF_Maths.*(.text* .rodata*)*/
+        *(.ramfunc*)
+        . = ALIGN(4);
+    } > ram1 AT > default_flash
+
+    .ram1 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        __ram1_clear__ = .;
+        . = ALIGN(4);
+        __ram1_noinit__ = .;
+        *(.ram1*)
+        . = ALIGN(4);
+        __ram1_free__ = .;
+    } > ram1
+
+    /* DATA_RAM area is DTCM primarily used for RAM-based data, e.g. vtables */
+    .ramdata : ALIGN(4)
+    {
+        . = ALIGN(4);
+        __ram2_init_text__ = LOADADDR(.ramdata);
+        __ram2_init__ = .;
+        /* ChibiOS won't boot unless these are excluded */
+        EXCLUDE_FILE (*vectors.o *crt0_v7m.o *crt1.o)
+        /* performance critical sections of ChibiOS */
+        *libch.a:ch*.*(.rodata*)
+        *libch.a:nvic.*(.rodata*)
+        *libch.a:bouncebuffer.*(.rodata*)
+        *libch.a:stm32_util.*(.rodata*)
+        *libch.a:stm32_dma.*(.rodata*)
+        *libch.a:memstreams.*(.rodata*)
+        *libch.a:malloc.*(.rodata*)
+        *libch.a:hrt.*(.rodata*)
+        *libch.a:hal*.*(.rodata*)
+        /* a selection of performance critical functions driven CPUInfo results */
+        lib/lib*.a:Semaphores.*(.rodata*)
+        lib/lib*.a:AP_Math.*(.rodata*)
+        lib/lib*.a:vector3.*(.rodata*)
+        lib/lib*.a:matrix3.*(.rodata*)
+        *libm.a:*(.rodata*)
+        *(.ramdata*)
+        . = ALIGN(4);
+    } > ram2 AT > default_flash
+
+    .ram2 (NOLOAD) : ALIGN(4)
+    {
+        . = ALIGN(4);
+        __ram2_clear__ = .;
+        . = ALIGN(4);
+        __ram2_noinit__ = .;
+        *(.ram2*)
+        . = ALIGN(4);
+        __ram2_free__ = .;
+    } > ram2
+
     .text : ALIGN(4) SUBALIGN(4)
     {
         /* we want app_descriptor near the start of flash so a false
@@ -210,4 +331,13 @@ SECTIONS
         . = ORIGIN(HEAP_RAM) + LENGTH(HEAP_RAM);
         __heap_end__ = .;
     } > HEAP_RAM
+
+    /* The crash log uses the unused part of a flash section.*/
+    .crash_log (NOLOAD) :
+    {
+        . = ALIGN(32);
+        __crash_log_base__ = .;
+        . = ORIGIN(default_flash) + LENGTH(default_flash);
+        __crash_log_end__ = .;
+    } > default_flash
 }
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/malloc.c b/libraries/AP_HAL_ChibiOS/hwdef/common/malloc.c
index 4449e9c72b5..b6cb8f9adbb 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/common/malloc.c
+++ b/libraries/AP_HAL_ChibiOS/hwdef/common/malloc.c
@@ -420,6 +420,7 @@ size_t mem_available(void)
     return totalp;
 }
 
+#if CH_CFG_USE_DYNAMIC == TRUE
 /*
   allocate a thread on any available heap
  */
@@ -444,6 +445,7 @@ thread_t *thread_create_alloc(size_t size,
     }
     return NULL;
 }
+#endif
 
 /*
   return heap information
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
index 5e30dddf219..7e2e38fe3ce 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
+++ b/libraries/AP_HAL_ChibiOS/hwdef/common/stm32h7_mcuconf.h
@@ -47,6 +47,7 @@
 #define STM32H743_MCUCONF
 #define STM32H753_MCUCONF
 #define STM32H745_MCUCONF
+#define STM32H750_MCUCONF
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
@@ -312,7 +313,6 @@
 #define STM32_IRQ_FDCAN2_PRIORITY           10
 
 #define STM32_IRQ_MDMA_PRIORITY             9
-
 #define STM32_IRQ_QUADSPI1_PRIORITY         10
 
 #define STM32_IRQ_SDMMC1_PRIORITY           9
@@ -349,7 +349,9 @@
 #define STM32_ADC_DUAL_MODE                 FALSE
 #define STM32_ADC_COMPACT_SAMPLES           FALSE
 #define STM32_ADC_USE_ADC12                 TRUE
+#ifndef STM32H750xx
 #define STM32_ADC_USE_ADC3                  TRUE
+#endif
 #define STM32_ADC_ADC12_DMA_PRIORITY        2
 #define STM32_ADC_ADC3_DMA_PRIORITY         2
 #define STM32_ADC_ADC12_IRQ_PRIORITY        5
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
index 760325fb41c..7a252dc6052 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H743xx.py
@@ -29,7 +29,7 @@ mcu = {
         (0x30000000, 256, 0), # SRAM1, SRAM2
         (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
         (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
-        (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
+		(0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
         (0x30040000,  32, 0), # SRAM3.
         (0x38000000,  64, 1), # SRAM4.
     ],
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H750xx.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H750xx.py
new file mode 100644
index 00000000000..e85faae9403
--- /dev/null
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H750xx.py
@@ -0,0 +1,1140 @@
+#!/usr/bin/env python
+'''
+these tables are generated from the STM32 datasheets for the STM32H750XB
+'''
+
+# additional build information for ChibiOS
+build = {
+    "CHIBIOS_STARTUP_MK"  : "os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk",
+    "CHIBIOS_PLATFORM_MK" : "os/hal/ports/STM32/STM32H7xx/platform.mk"
+    }
+
+# MCU parameters
+mcu = {
+    # location of MCU serial number
+    'UDID_START' : 0x1FF1E800,
+
+    # DMA peripheral capabilities:
+    # - can't use ITCM or DTCM for any DMA
+    # - SPI1 to SPI5 can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 for DMA
+    # - SPI6, I2C4 and ADC3 can use SRAM4 on BDMA
+    # - UARTS can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 for DMA
+    # - I2C1, I2C2 and I2C3 can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 with DMA
+    # - timers can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 with DMA
+    # - ADC12 can use AXI SRAM, SRAM1 to SRAM3 and SRAM4
+    # - SDMMC can use AXI SRAM, SRAM1 to SRAM3 with IDMA (cannot use SRAM4)
+
+    # ram map, as list of (address, size-kb, flags)
+    # flags of 1 means DMA-capable (DMA and BDMA)
+    # flags of 2 means faster memory for CPU intensive work
+    # flags of 4 means memory can be used for SDMMC DMA
+    'RAM_MAP' : [
+        (0x30000000, 256, 0), # SRAM1, SRAM2
+        (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
+        (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
+        (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
+        (0x30040000,  32, 0), # SRAM3.
+        (0x38000000,  64, 1), # SRAM4.
+    ],
+
+    'RAM_MAP_EXTERNAL_FLASH' : [
+		# SSBL checks that stack is in this region so needs to come first
+        (0x30000000, 256, 0), # SRAM1, SRAM2
+        (0x24000000, 256, 4), # AXI SRAM. Use this for SDMMC IDMA ops
+        (0x20000000,  64, 2), # DTCM, tightly coupled, no DMA, fast
+        (0x30040000,  32, 0), # SRAM3.
+        (0x38000000,  64, 1), # SRAM4.
+    ],
+    'INSTRUCTION_RAM' : (0x00000400,  63), # ITCM (first 1k removed, to keep address 0 unused)
+    'FLASH_RAM' : 		(0x24040000, 256), # AXI SRAM used for process stack and ram functions
+    'DATA_RAM' :        (0x20010000,  64), # DTCM, tightly coupled, no DMA, fast
+
+    # avoid a problem in the bootloader by making DTCM first. The DCache init
+    # when using SRAM1 as primary memory gets a hard fault in bootloader
+    # we can't use DTCM first for main firmware as some builds overflow the first segment
+    'RAM_MAP_BOOTLOADER' : [
+        (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
+        (0x30000000, 256, 0), # SRAM1, SRAM2
+        (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
+        (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
+        (0x30040000,  32, 0), # SRAM3.
+        (0x38000000,  64, 1), # SRAM4.
+    ],
+
+    'EXPECTED_CLOCK' : 400000000,
+
+    # this MCU has M7 instructions and hardware double precision
+    'CORTEX'    : 'cortex-m7',
+    'CPU_FLAGS' : '-mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard',
+
+    'DEFINES' : {
+        'HAL_HAVE_HARDWARE_DOUBLE' : '1'
+    }	
+}
+
+pincount = {
+    'A': 16,
+    'B': 16,
+    'C': 16,
+    'D': 16,
+    'E': 16,
+    'F': 16,
+    'G': 16,
+    'H': 16,
+    'I': 16,
+    'J': 16,
+    'K': 16
+}
+    
+# no DMA map as we will dynamically allocate DMA channels using the DMAMUX
+DMA_Map = None
+
+AltFunction_map = {
+	# format is PIN:FUNCTION : AFNUM
+	# extracted from stm32h750xb.csv
+	"PA0:ETH_CRS"       	:	11,
+	"PA0:SAI2_SD_B"     	:	10,
+	"PA0:SDMMC2_CMD"    	:	9,
+	"PA0:TIM15_BKIN"    	:	4,
+	"PA0:TIM2_CH1"      	:	1,
+	"PA0:TIM2_ETR"      	:	1,
+	"PA0:TIM5_CH1"      	:	2,
+	"PA0:TIM8_ETR"      	:	3,
+	"PA0:UART4_TX"      	:	8,
+	"PA0:USART2_CTS"    	:	7,
+	"PA0:USART2_NSS"    	:	7,
+	"PA1:ETH_REF_CLK"   	:	11,
+	"PA1:ETH_RX_CLK"    	:	11,
+	"PA1:LPTIM3_OUT"    	:	3,
+	"PA1:LTDC_R2"       	:	14,
+	"PA1:QUADSPI_BK1_IO3"	:	9,
+	"PA1:SAI2_MCLK_B"   	:	10,
+	"PA1:TIM15_CH1N"    	:	4,
+	"PA1:TIM2_CH2"      	:	1,
+	"PA1:TIM5_CH2"      	:	2,
+	"PA1:UART4_RX"      	:	8,
+	"PA1:USART2_DE"     	:	7,
+	"PA1:USART2_RTS"    	:	7,
+	"PA2:ETH_MDIO"      	:	11,
+	"PA2:LPTIM4_OUT"    	:	3,
+	"PA2:LTDC_R1"       	:	14,
+	"PA2:MDIOS_MDIO"    	:	12,
+	"PA2:SAI2_SCK_B"    	:	8,
+	"PA2:TIM15_CH1"     	:	4,
+	"PA2:TIM2_CH3"      	:	1,
+	"PA2:TIM5_CH3"      	:	2,
+	"PA2:USART2_TX"     	:	7,
+	"PA3:ETH_COL"       	:	11,
+	"PA3:LPTIM5_OUT"    	:	3,
+	"PA3:LTDC_B2"       	:	9,
+	"PA3:LTDC_B5"       	:	14,
+	"PA3:TIM15_CH2"     	:	4,
+	"PA3:TIM2_CH4"      	:	1,
+	"PA3:TIM5_CH4"      	:	2,
+	"PA3:USART2_RX"     	:	7,
+	"PA3:USB_OTG_HS_ULPI_D0"	:	10,
+	"PA4:DCMI_HSYNC"    	:	13,
+	"PA4:I2S1_WS"       	:	5,
+	"PA4:I2S3_WS"       	:	6,
+	"PA4:LTDC_VSYNC"    	:	14,
+	"PA4:SPI1_NSS"      	:	5,
+	"PA4:SPI3_NSS"      	:	6,
+	"PA4:SPI6_NSS"      	:	8,
+	"PA4:TIM5_ETR"      	:	2,
+	"PA4:USART2_CK"     	:	7,
+	"PA4:USB_OTG_HS_SOF"	:	12,
+	"PA5:I2S1_CK"       	:	5,
+	"PA5:LTDC_R4"       	:	14,
+	"PA5:SPI1_SCK"      	:	5,
+	"PA5:SPI6_SCK"      	:	8,
+	"PA5:TIM2_CH1"      	:	1,
+	"PA5:TIM2_ETR"      	:	1,
+	"PA5:TIM8_CH1N"     	:	3,
+	"PA5:USB_OTG_HS_ULPI_CK"	:	10,
+	"PA6:DCMI_PIXCLK"   	:	13,
+	"PA6:I2S1_SDI"      	:	5,
+	"PA6:LTDC_G2"       	:	14,
+	"PA6:MDIOS_MDC"     	:	11,
+	"PA6:SPI1_MISO"     	:	5,
+	"PA6:SPI6_MISO"     	:	8,
+	"PA6:TIM13_CH1"     	:	9,
+	"PA6:TIM1_BKIN"     	:	1,
+	"PA6:TIM1_BKIN_COMP1"	:	12,
+	"PA6:TIM1_BKIN_COMP2"	:	12,
+	"PA6:TIM3_CH1"      	:	2,
+	"PA6:TIM8_BKIN"     	:	3,
+	"PA6:TIM8_BKIN_COMP1"	:	10,
+	"PA6:TIM8_BKIN_COMP2"	:	10,
+	"PA7:ETH_CRS_DV"    	:	11,
+	"PA7:ETH_RX_DV"     	:	11,
+	"PA7:FMC_SDNWE"     	:	12,
+	"PA7:I2S1_SDO"      	:	5,
+	"PA7:SPI1_MOSI"     	:	5,
+	"PA7:SPI6_MOSI"     	:	8,
+	"PA7:TIM14_CH1"     	:	9,
+	"PA7:TIM1_CH1N"     	:	1,
+	"PA7:TIM3_CH2"      	:	2,
+	"PA7:TIM8_CH1N"     	:	3,
+	"PA8:HRTIM_CHB2"    	:	2,
+	"PA8:I2C3_SCL"      	:	4,
+	"PA8:LTDC_B3"       	:	13,
+	"PA8:LTDC_R6"       	:	14,
+	"PA8:RCC_MCO_1"     	:	0,
+	"PA8:TIM1_CH1"      	:	1,
+	"PA8:TIM8_BKIN2"    	:	3,
+	"PA8:TIM8_BKIN2_COMP1"	:	12,
+	"PA8:TIM8_BKIN2_COMP2"	:	12,
+	"PA8:UART7_RX"      	:	11,
+	"PA8:USART1_CK"     	:	7,
+	"PA8:USB_OTG_FS_SOF"	:	10,
+	"PA9:DCMI_D0"       	:	13,
+	"PA9:HRTIM_CHC1"    	:	2,
+	"PA9:I2C3_SMBA"     	:	4,
+	"PA9:I2S2_CK"       	:	5,
+	"PA9:LPUART1_TX"    	:	3,
+	"PA9:LTDC_R5"       	:	14,
+	"PA9:SPI2_SCK"      	:	5,
+	"PA9:TIM1_CH2"      	:	1,
+	"PA9:USART1_TX"     	:	7,
+	"PA10:DCMI_D1"      	:	13,
+	"PA10:HRTIM_CHC2"   	:	2,
+	"PA10:LPUART1_RX"   	:	3,
+	"PA10:LTDC_B1"      	:	14,
+	"PA10:LTDC_B4"      	:	12,
+	"PA10:MDIOS_MDIO"   	:	11,
+	"PA10:TIM1_CH3"     	:	1,
+	"PA10:USART1_RX"    	:	7,
+	"PA10:USB_OTG_FS_ID"	:	10,
+	"PA11:FDCAN1_RX"    	:	9,
+	"PA11:HRTIM_CHD1"   	:	2,
+	"PA11:I2S2_WS"      	:	5,
+	"PA11:LPUART1_CTS"  	:	3,
+	"PA11:LTDC_R4"      	:	14,
+	"PA11:SPI2_NSS"     	:	5,
+	"PA11:TIM1_CH4"     	:	1,
+	"PA11:UART4_RX"     	:	6,
+	"PA11:USART1_CTS"   	:	7,
+	"PA11:USART1_NSS"   	:	7,
+	"PA11:OTG_FS_DM"		:	10,
+	"PA12:FDCAN1_TX"    	:	9,
+	"PA12:HRTIM_CHD2"   	:	2,
+	"PA12:I2S2_CK"      	:	5,
+	"PA12:LPUART1_DE"   	:	3,
+	"PA12:LPUART1_RTS"  	:	3,
+	"PA12:LTDC_R5"      	:	14,
+	"PA12:SAI2_FS_B"    	:	8,
+	"PA12:SPI2_SCK"     	:	5,
+	"PA12:TIM1_ETR"     	:	1,
+	"PA12:UART4_TX"     	:	6,
+	"PA12:USART1_DE"    	:	7,
+	"PA12:USART1_RTS"   	:	7,
+	"PA12:OTG_FS_DP"		:	10,
+	"PA13:JTMS-SWDIO"		:	0,
+	"PA14:JTCK-SWCLK"		:	0,
+	"PA15:CEC"          	:	4,
+	"PA15:JTDI"   			:	0,
+	"PA15:HRTIM_FLT1"   	:	2,
+	"PA15:I2S1_WS"      	:	5,
+	"PA15:I2S3_WS"      	:	6,
+	"PA15:SPI1_NSS"     	:	5,
+	"PA15:SPI3_NSS"     	:	6,
+	"PA15:SPI6_NSS"     	:	7,
+	"PA15:TIM2_CH1"     	:	1,
+	"PA15:TIM2_ETR"     	:	1,
+	"PA15:UART4_DE"     	:	8,
+	"PA15:UART4_RTS"    	:	8,
+	"PA15:UART7_TX"     	:	11,
+	"PB0:DFSDM1_CKOUT"  	:	6,
+	"PB0:ETH_RXD2"      	:	11,
+	"PB0:LTDC_G1"       	:	14,
+	"PB0:LTDC_R3"       	:	9,
+	"PB0:TIM1_CH2N"     	:	1,
+	"PB0:TIM3_CH3"      	:	2,
+	"PB0:TIM8_CH2N"     	:	3,
+	"PB0:UART4_CTS"     	:	8,
+	"PB0:USB_OTG_HS_ULPI_D1"	:	10,
+	"PB1:DFSDM1_DATIN1" 	:	6,
+	"PB1:ETH_RXD3"      	:	11,
+	"PB1:LTDC_G0"       	:	14,
+	"PB1:LTDC_R6"       	:	9,
+	"PB1:TIM1_CH3N"     	:	1,
+	"PB1:TIM3_CH4"      	:	2,
+	"PB1:TIM8_CH3N"     	:	3,
+	"PB1:USB_OTG_HS_ULPI_D2"	:	10,
+	"PB2:DFSDM1_CKIN1"  	:	4,
+	"PB2:I2S3_SDO"      	:	7,
+	"PB2:QUADSPI_CLK"   	:	9,
+	"PB2:RTC_OUT_ALARM" 	:	0,
+	"PB2:RTC_OUT_CALIB" 	:	0,
+	"PB2:SAI1_D1"       	:	2,
+	"PB2:SAI1_SD_A"     	:	6,
+	"PB2:SAI4_D1"       	:	10,
+	"PB2:SAI4_SD_A"     	:	8,
+	"PB2:SPI3_MOSI"     	:	7,
+	"PB3:CRS_SYNC"      	:	10,
+	"PB3:JTDO-SWO"			:	0,
+	"PB3:HRTIM_FLT4"    	:	2,
+	"PB3:I2S1_CK"       	:	5,
+	"PB3:I2S3_CK"       	:	6,
+	"PB3:SDMMC2_D2"     	:	9,
+	"PB3:SPI1_SCK"      	:	5,
+	"PB3:SPI3_SCK"      	:	6,
+	"PB3:SPI6_SCK"      	:	8,
+	"PB3:TIM2_CH2"      	:	1,
+	"PB3:UART7_RX"      	:	11,
+	"PB4:HRTIM_EEV6"    	:	3,
+	"PB4:I2S1_SDI"      	:	5,
+	"PB4:I2S2_WS"       	:	7,
+	"PB4:I2S3_SDI"      	:	6,
+	"PB4:SDMMC2_D3"     	:	9,
+	"PB4:SPI1_MISO"     	:	5,
+	"PB4:SPI2_NSS"      	:	7,
+	"PB4:SPI3_MISO"     	:	6,
+	"PB4:SPI6_MISO"     	:	8,
+	"PB4:TIM16_BKIN"    	:	1,
+	"PB4:TIM3_CH1"      	:	2,
+	"PB4:UART7_TX"      	:	11,
+	"PB5:DCMI_D10"      	:	13,
+	"PB5:ETH_PPS_OUT"   	:	11,
+	"PB5:FDCAN2_RX"     	:	9,
+	"PB5:FMC_SDCKE1"    	:	12,
+	"PB5:HRTIM_EEV7"    	:	3,
+	"PB5:I2C1_SMBA"     	:	4,
+	"PB5:I2C4_SMBA"     	:	6,
+	"PB5:I2S1_SDO"      	:	5,
+	"PB5:I2S3_SDO"      	:	7,
+	"PB5:SPI1_MOSI"     	:	5,
+	"PB5:SPI3_MOSI"     	:	7,
+	"PB5:SPI6_MOSI"     	:	8,
+	"PB5:TIM17_BKIN"    	:	1,
+	"PB5:TIM3_CH2"      	:	2,
+	"PB5:UART5_RX"      	:	14,
+	"PB5:USB_OTG_HS_ULPI_D7"	:	10,
+	"PB6:CEC"           	:	5,
+	"PB6:DCMI_D5"       	:	13,
+	"PB6:DFSDM1_DATIN5" 	:	11,
+	"PB6:FDCAN2_TX"     	:	9,
+	"PB6:FMC_SDNE1"     	:	12,
+	"PB6:HRTIM_EEV8"    	:	3,
+	"PB6:I2C1_SCL"      	:	4,
+	"PB6:I2C4_SCL"      	:	6,
+	"PB6:LPUART1_TX"    	:	8,
+	"PB6:QUADSPI_BK1_NCS"	:	10,
+	"PB6:TIM16_CH1N"    	:	1,
+	"PB6:TIM4_CH1"      	:	2,
+	"PB6:UART5_TX"      	:	14,
+	"PB6:USART1_TX"     	:	7,
+	"PB7:DCMI_VSYNC"    	:	13,
+	"PB7:DFSDM1_CKIN5"  	:	11,
+	"PB7:FMC_NL"        	:	12,
+	"PB7:HRTIM_EEV9"    	:	3,
+	"PB7:I2C1_SDA"      	:	4,
+	"PB7:I2C4_SDA"      	:	6,
+	"PB7:LPUART1_RX"    	:	8,
+	"PB7:TIM17_CH1N"    	:	1,
+	"PB7:TIM4_CH2"      	:	2,
+	"PB7:USART1_RX"     	:	7,
+	"PB8:DCMI_D6"       	:	13,
+	"PB8:DFSDM1_CKIN7"  	:	3,
+	"PB8:ETH_TXD3"      	:	11,
+	"PB8:FDCAN1_RX"     	:	9,
+	"PB8:I2C1_SCL"      	:	4,
+	"PB8:I2C4_SCL"      	:	6,
+	"PB8:LTDC_B6"       	:	14,
+	"PB8:SDMMC1_CKIN"   	:	7,
+	"PB8:SDMMC1_D4"     	:	12,
+	"PB8:SDMMC2_D4"     	:	10,
+	"PB8:TIM16_CH1"     	:	1,
+	"PB8:TIM4_CH3"      	:	2,
+	"PB8:UART4_RX"      	:	8,
+	"PB9:DCMI_D7"       	:	13,
+	"PB9:DFSDM1_DATIN7" 	:	3,
+	"PB9:FDCAN1_TX"     	:	9,
+	"PB9:I2C1_SDA"      	:	4,
+	"PB9:I2C4_SDA"      	:	6,
+	"PB9:I2C4_SMBA"     	:	11,
+	"PB9:I2S2_WS"       	:	5,
+	"PB9:LTDC_B7"       	:	14,
+	"PB9:SDMMC1_CDIR"   	:	7,
+	"PB9:SDMMC1_D5"     	:	12,
+	"PB9:SDMMC2_D5"     	:	10,
+	"PB9:SPI2_NSS"      	:	5,
+	"PB9:TIM17_CH1"     	:	1,
+	"PB9:TIM4_CH4"      	:	2,
+	"PB9:UART4_TX"      	:	8,
+	"PB10:DFSDM1_DATIN7"	:	6,
+	"PB10:ETH_RX_ER"    	:	11,
+	"PB10:HRTIM_SCOUT"  	:	2,
+	"PB10:I2C2_SCL"     	:	4,
+	"PB10:I2S2_CK"      	:	5,
+	"PB10:LPTIM2_IN1"   	:	3,
+	"PB10:LTDC_G4"      	:	14,
+	"PB10:QUADSPI_BK1_NCS"	:	9,
+	"PB10:SPI2_SCK"     	:	5,
+	"PB10:TIM2_CH3"     	:	1,
+	"PB10:USART3_TX"    	:	7,
+	"PB10:USB_OTG_HS_ULPI_D3"	:	10,
+	"PB11:DFSDM1_CKIN7" 	:	6,
+	"PB11:ETH_TX_EN"    	:	11,
+	"PB11:HRTIM_SCIN"   	:	2,
+	"PB11:I2C2_SDA"     	:	4,
+	"PB11:LPTIM2_ETR"   	:	3,
+	"PB11:LTDC_G5"      	:	14,
+	"PB11:TIM2_CH4"     	:	1,
+	"PB11:USART3_RX"    	:	7,
+	"PB11:USB_OTG_HS_ULPI_D4"	:	10,
+	"PB12:DFSDM1_DATIN1"	:	6,
+	"PB12:ETH_TXD0"     	:	11,
+	"PB12:FDCAN2_RX"    	:	9,
+	"PB12:I2C2_SMBA"    	:	4,
+	"PB12:I2S2_WS"      	:	5,
+	"PB12:SPI2_NSS"     	:	5,
+	"PB12:TIM1_BKIN"    	:	1,
+	"PB12:TIM1_BKIN_COMP1"	:	13,
+	"PB12:TIM1_BKIN_COMP2"	:	13,
+	"PB12:UART5_RX"     	:	14,
+	"PB12:USART3_CK"    	:	7,
+	"PB12:USB_OTG_HS_ID"	:	12,
+	"PB12:USB_OTG_HS_ULPI_D5"	:	10,
+	"PB13:DFSDM1_CKIN1" 	:	6,
+	"PB13:ETH_TXD1"     	:	11,
+	"PB13:FDCAN2_TX"    	:	9,
+	"PB13:I2S2_CK"      	:	5,
+	"PB13:LPTIM2_OUT"   	:	3,
+	"PB13:SPI2_SCK"     	:	5,
+	"PB13:TIM1_CH1N"    	:	1,
+	"PB13:UART5_TX"     	:	14,
+	"PB13:USART3_CTS"   	:	7,
+	"PB13:USART3_NSS"   	:	7,
+	"PB13:USB_OTG_HS_ULPI_D6"	:	10,
+	"PB14:DFSDM1_DATIN2"	:	6,
+	"PB14:I2S2_SDI"     	:	5,
+	"PB14:SDMMC2_D0"    	:	9,
+	"PB14:SPI2_MISO"    	:	5,
+	"PB14:TIM12_CH1"    	:	2,
+	"PB14:TIM1_CH2N"    	:	1,
+	"PB14:TIM8_CH2N"    	:	3,
+	"PB14:UART4_DE"     	:	8,
+	"PB14:UART4_RTS"    	:	8,
+	"PB14:USART1_TX"    	:	4,
+	"PB14:USART3_DE"    	:	7,
+	"PB14:USART3_RTS"   	:	7,
+	"PB14:USB_OTG_HS_DM"	:	12,
+	"PB15:DFSDM1_CKIN2" 	:	6,
+	"PB15:I2S2_SDO"     	:	5,
+	"PB15:RTC_REFIN"    	:	0,
+	"PB15:SDMMC2_D1"    	:	9,
+	"PB15:SPI2_MOSI"    	:	5,
+	"PB15:TIM12_CH2"    	:	2,
+	"PB15:TIM1_CH3N"    	:	1,
+	"PB15:TIM8_CH3N"    	:	3,
+	"PB15:UART4_CTS"    	:	8,
+	"PB15:USART1_RX"    	:	4,
+	"PB15:USB_OTG_HS_DP"	:	12,
+	"PC0:DFSDM1_CKIN0"  	:	3,
+	"PC0:DFSDM1_DATIN4" 	:	6,
+	"PC0:FMC_SDNWE"     	:	12,
+	"PC0:LTDC_R5"       	:	14,
+	"PC0:SAI2_FS_B"     	:	8,
+	"PC0:USB_OTG_HS_ULPI_STP"	:	10,
+	"PC1:TRACED0" 			:	0,
+	"PC1:DFSDM1_CKIN4"  	:	4,
+	"PC1:DFSDM1_DATIN0" 	:	3,
+	"PC1:ETH_MDC"       	:	11,
+	"PC1:I2S2_SDO"      	:	5,
+	"PC1:MDIOS_MDC"     	:	12,
+	"PC1:SAI1_D1"       	:	2,
+	"PC1:SAI1_SD_A"     	:	6,
+	"PC1:SAI4_D1"       	:	10,
+	"PC1:SAI4_SD_A"     	:	8,
+	"PC1:SDMMC2_CK"     	:	9,
+	"PC1:SPI2_MOSI"     	:	5,
+	"PC2:DFSDM1_CKIN1"  	:	3,
+	"PC2:DFSDM1_CKOUT"  	:	6,
+	"PC2:ETH_TXD2"      	:	11,
+	"PC2:FMC_SDNE0"     	:	12,
+	"PC2:I2S2_SDI"      	:	5,
+	"PC2:SPI2_MISO"     	:	5,
+	"PC2:USB_OTG_HS_ULPI_DIR"	:	10,
+	"PC3:DFSDM1_DATIN1" 	:	3,
+	"PC3:ETH_TX_CLK"    	:	11,
+	"PC3:FMC_SDCKE0"    	:	12,
+	"PC3:I2S2_SDO"      	:	5,
+	"PC3:SPI2_MOSI"     	:	5,
+	"PC3:USB_OTG_HS_ULPI_NXT"	:	10,
+	"PC4:DFSDM1_CKIN2"  	:	3,
+	"PC4:ETH_RXD0"      	:	11,
+	"PC4:FMC_SDNE0"     	:	12,
+	"PC4:I2S1_MCK"      	:	5,
+	"PC4:SPDIFRX1_IN2"  	:	9,
+	"PC5:COMP1_OUT"     	:	13,
+	"PC5:DFSDM1_DATIN2" 	:	3,
+	"PC5:ETH_RXD1"      	:	11,
+	"PC5:FMC_SDCKE0"    	:	12,
+	"PC5:SAI1_D3"       	:	2,
+	"PC5:SAI4_D3"       	:	10,
+	"PC5:SPDIFRX1_IN3"  	:	9,
+	"PC6:DCMI_D0"       	:	13,
+	"PC6:DFSDM1_CKIN3"  	:	4,
+	"PC6:FMC_NWAIT"     	:	9,
+	"PC6:HRTIM_CHA1"    	:	1,
+	"PC6:I2S2_MCK"      	:	5,
+	"PC6:LTDC_HSYNC"    	:	14,
+	"PC6:SDMMC1_D0DIR"  	:	8,
+	"PC6:SDMMC1_D6"     	:	12,
+	"PC6:SDMMC2_D6"     	:	10,
+	"PC6:TIM3_CH1"      	:	2,
+	"PC6:TIM8_CH1"      	:	3,
+	"PC6:USART6_TX"     	:	7,
+	"PC7:DCMI_D1"       	:	13,
+	"PC7:TRGIO"			   	:	0,
+	"PC7:DFSDM1_DATIN3" 	:	4,
+	"PC7:FMC_NE1"       	:	9,
+	"PC7:HRTIM_CHA2"    	:	1,
+	"PC7:I2S3_MCK"      	:	6,
+	"PC7:LTDC_G6"       	:	14,
+	"PC7:SDMMC1_D123DIR"	:	8,
+	"PC7:SDMMC1_D7"     	:	12,
+	"PC7:SDMMC2_D7"     	:	10,
+	"PC7:SWPMI1_TX"     	:	11,
+	"PC7:TIM3_CH2"      	:	2,
+	"PC7:TIM8_CH2"      	:	3,
+	"PC7:USART6_RX"     	:	7,
+	"PC8:DCMI_D2"       	:	13,
+	"PC8:TRACED1"		 	:	0,
+	"PC8:FMC_NCE"       	:	9,
+	"PC8:FMC_NE2"       	:	9,
+	"PC8:HRTIM_CHB1"    	:	1,
+	"PC8:SDMMC1_D0"     	:	12,
+	"PC8:SWPMI1_RX"     	:	11,
+	"PC8:TIM3_CH3"      	:	2,
+	"PC8:TIM8_CH3"      	:	3,
+	"PC8:UART5_DE"      	:	8,
+	"PC8:UART5_RTS"     	:	8,
+	"PC8:USART6_CK"     	:	7,
+	"PC9:DCMI_D3"       	:	13,
+	"PC9:I2C3_SDA"      	:	4,
+	"PC9:I2S_CKIN"      	:	5,
+	"PC9:LTDC_B2"       	:	14,
+	"PC9:LTDC_G3"       	:	10,
+	"PC9:QUADSPI_BK1_IO0"	:	9,
+	"PC9:RCC_MCO_2"     	:	0,
+	"PC9:SDMMC1_D1"     	:	12,
+	"PC9:SWPMI1_SUSPEND"	:	11,
+	"PC9:TIM3_CH4"      	:	2,
+	"PC9:TIM8_CH4"      	:	3,
+	"PC9:UART5_CTS"     	:	8,
+	"PC10:DCMI_D8"      	:	13,
+	"PC10:DFSDM1_CKIN5" 	:	3,
+	"PC10:HRTIM_EEV1"   	:	2,
+	"PC10:I2S3_CK"      	:	6,
+	"PC10:LTDC_R2"      	:	14,
+	"PC10:QUADSPI_BK1_IO1"	:	9,
+	"PC10:SDMMC1_D2"    	:	12,
+	"PC10:SPI3_SCK"     	:	6,
+	"PC10:UART4_TX"     	:	8,
+	"PC10:USART3_TX"    	:	7,
+	"PC11:DCMI_D4"      	:	13,
+	"PC11:DFSDM1_DATIN5"	:	3,
+	"PC11:HRTIM_FLT2"   	:	2,
+	"PC11:I2S3_SDI"     	:	6,
+	"PC11:QUADSPI_BK2_NCS"	:	9,
+	"PC11:SDMMC1_D3"    	:	12,
+	"PC11:SPI3_MISO"    	:	6,
+	"PC11:UART4_RX"     	:	8,
+	"PC11:USART3_RX"    	:	7,
+	"PC12:DCMI_D9"      	:	13,
+	"PC12:TRACED3"			:	0,
+	"PC12:HRTIM_EEV2"   	:	2,
+	"PC12:I2S3_SDO"     	:	6,
+	"PC12:SDMMC1_CK"    	:	12,
+	"PC12:SPI3_MOSI"    	:	6,
+	"PC12:UART5_TX"     	:	8,
+	"PC12:USART3_CK"    	:	7,
+	"PD0:DFSDM1_CKIN6"  	:	3,
+	"PD0:FDCAN1_RX"     	:	9,
+	"PD0:FMC_D2"        	:	12,
+	"PD0:FMC_DA2"       	:	12,
+	"PD0:SAI3_SCK_A"    	:	6,
+	"PD0:UART4_RX"      	:	8,
+	"PD1:DFSDM1_DATIN6" 	:	3,
+	"PD1:FDCAN1_TX"     	:	9,
+	"PD1:FMC_D3"        	:	12,
+	"PD1:FMC_DA3"       	:	12,
+	"PD1:SAI3_SD_A"     	:	6,
+	"PD1:UART4_TX"      	:	8,
+	"PD2:DCMI_D11"      	:	13,
+	"PD2:TRACED2" 			:	0,
+	"PD2:SDMMC1_CMD"    	:	12,
+	"PD2:TIM3_ETR"      	:	2,
+	"PD2:UART5_RX"      	:	8,
+	"PD3:DCMI_D5"       	:	13,
+	"PD3:DFSDM1_CKOUT"  	:	3,
+	"PD3:FMC_CLK"       	:	12,
+	"PD3:I2S2_CK"       	:	5,
+	"PD3:LTDC_G7"       	:	14,
+	"PD3:SPI2_SCK"      	:	5,
+	"PD3:USART2_CTS"    	:	7,
+	"PD3:USART2_NSS"    	:	7,
+	"PD4:FMC_NOE"       	:	12,
+	"PD4:HRTIM_FLT3"    	:	2,
+	"PD4:SAI3_FS_A"     	:	6,
+	"PD4:USART2_DE"     	:	7,
+	"PD4:USART2_RTS"    	:	7,
+	"PD5:FMC_NWE"       	:	12,
+	"PD5:HRTIM_EEV3"    	:	2,
+	"PD5:USART2_TX"     	:	7,
+	"PD6:DCMI_D10"      	:	13,
+	"PD6:DFSDM1_CKIN4"  	:	3,
+	"PD6:DFSDM1_DATIN1" 	:	4,
+	"PD6:FMC_NWAIT"     	:	12,
+	"PD6:I2S3_SDO"      	:	5,
+	"PD6:LTDC_B2"       	:	14,
+	"PD6:SAI1_D1"       	:	2,
+	"PD6:SAI1_SD_A"     	:	6,
+	"PD6:SAI4_D1"       	:	10,
+	"PD6:SAI4_SD_A"     	:	8,
+	"PD6:SDMMC2_CK"     	:	11,
+	"PD6:SPI3_MOSI"     	:	5,
+	"PD6:USART2_RX"     	:	7,
+	"PD7:DFSDM1_CKIN1"  	:	6,
+	"PD7:DFSDM1_DATIN4" 	:	3,
+	"PD7:FMC_NE1"       	:	12,
+	"PD7:I2S1_SDO"      	:	5,
+	"PD7:SDMMC2_CMD"    	:	11,
+	"PD7:SPDIFRX1_IN0"  	:	9,
+	"PD7:SPI1_MOSI"     	:	5,
+	"PD7:USART2_CK"     	:	7,
+	"PD8:DFSDM1_CKIN3"  	:	3,
+	"PD8:FMC_D13"       	:	12,
+	"PD8:FMC_DA13"      	:	12,
+	"PD8:SAI3_SCK_B"    	:	6,
+	"PD8:SPDIFRX1_IN1"  	:	9,
+	"PD8:USART3_TX"     	:	7,
+	"PD9:DFSDM1_DATIN3" 	:	3,
+	"PD9:FMC_D14"       	:	12,
+	"PD9:FMC_DA14"      	:	12,
+	"PD9:SAI3_SD_B"     	:	6,
+	"PD9:USART3_RX"     	:	7,
+	"PD10:DFSDM1_CKOUT" 	:	3,
+	"PD10:FMC_D15"      	:	12,
+	"PD10:FMC_DA15"     	:	12,
+	"PD10:LTDC_B3"      	:	14,
+	"PD10:SAI3_FS_B"    	:	6,
+	"PD10:USART3_CK"    	:	7,
+	"PD11:FMC_A16"      	:	12,
+	"PD11:I2C4_SMBA"    	:	4,
+	"PD11:LPTIM2_IN2"   	:	3,
+	"PD11:QUADSPI_BK1_IO0"	:	9,
+	"PD11:SAI2_SD_A"    	:	10,
+	"PD11:USART3_CTS"   	:	7,
+	"PD11:USART3_NSS"   	:	7,
+	"PD12:FMC_A17"      	:	12,
+	"PD12:I2C4_SCL"     	:	4,
+	"PD12:LPTIM1_IN1"   	:	1,
+	"PD12:LPTIM2_IN1"   	:	3,
+	"PD12:QUADSPI_BK1_IO1"	:	9,
+	"PD12:SAI2_FS_A"    	:	10,
+	"PD12:TIM4_CH1"     	:	2,
+	"PD12:USART3_DE"    	:	7,
+	"PD12:USART3_RTS"   	:	7,
+	"PD13:FMC_A18"      	:	12,
+	"PD13:I2C4_SDA"     	:	4,
+	"PD13:LPTIM1_OUT"   	:	1,
+	"PD13:QUADSPI_BK1_IO3"	:	9,
+	"PD13:SAI2_SCK_A"   	:	10,
+	"PD13:TIM4_CH2"     	:	2,
+	"PD14:FMC_D0"       	:	12,
+	"PD14:FMC_DA0"      	:	12,
+	"PD14:SAI3_MCLK_B"  	:	6,
+	"PD14:TIM4_CH3"     	:	2,
+	"PD14:UART8_CTS"    	:	8,
+	"PD15:FMC_D1"       	:	12,
+	"PD15:FMC_DA1"      	:	12,
+	"PD15:SAI3_MCLK_A"  	:	6,
+	"PD15:TIM4_CH4"     	:	2,
+	"PD15:UART8_DE"     	:	8,
+	"PD15:UART8_RTS"    	:	8,
+	"PE0:DCMI_D2"       	:	13,
+	"PE0:FMC_NBL0"      	:	12,
+	"PE0:HRTIM_SCIN"    	:	3,
+	"PE0:LPTIM1_ETR"    	:	1,
+	"PE0:LPTIM2_ETR"    	:	4,
+	"PE0:SAI2_MCLK_A"   	:	10,
+	"PE0:TIM4_ETR"      	:	2,
+	"PE0:UART8_RX"      	:	8,
+	"PE1:DCMI_D3"       	:	13,
+	"PE1:FMC_NBL1"      	:	12,
+	"PE1:HRTIM_SCOUT"   	:	3,
+	"PE1:LPTIM1_IN2"    	:	1,
+	"PE1:UART8_TX"      	:	8,
+	"PE2:TRACECLK"			:	0,
+	"PE2:ETH_TXD3"      	:	11,
+	"PE2:FMC_A23"       	:	12,
+	"PE2:QUADSPI_BK1_IO2"	:	9,
+	"PE2:SAI1_CK1"      	:	2,
+	"PE2:SAI1_MCLK_A"   	:	6,
+	"PE2:SAI4_CK1"      	:	10,
+	"PE2:SAI4_MCLK_A"   	:	8,
+	"PE2:SPI4_SCK"      	:	5,
+	"PE3:TRACED0"		 	:	0,
+	"PE3:FMC_A19"       	:	12,
+	"PE3:SAI1_SD_B"     	:	6,
+	"PE3:SAI4_SD_B"     	:	8,
+	"PE3:TIM15_BKIN"    	:	4,
+	"PE4:DCMI_D4"       	:	13,
+	"PE4:TRACED1"		 	:	0,
+	"PE4:DFSDM1_DATIN3" 	:	3,
+	"PE4:FMC_A20"       	:	12,
+	"PE4:LTDC_B0"       	:	14,
+	"PE4:SAI1_D2"       	:	2,
+	"PE4:SAI1_FS_A"     	:	6,
+	"PE4:SAI4_D2"       	:	10,
+	"PE4:SAI4_FS_A"     	:	8,
+	"PE4:SPI4_NSS"      	:	5,
+	"PE4:TIM15_CH1N"    	:	4,
+	"PE5:DCMI_D6"       	:	13,
+	"PE5:TRACED2"		 	:	0,
+	"PE5:DFSDM1_CKIN3"  	:	3,
+	"PE5:FMC_A21"       	:	12,
+	"PE5:LTDC_G0"       	:	14,
+	"PE5:SAI1_CK2"      	:	2,
+	"PE5:SAI1_SCK_A"    	:	6,
+	"PE5:SAI4_CK2"      	:	10,
+	"PE5:SAI4_SCK_A"    	:	8,
+	"PE5:SPI4_MISO"     	:	5,
+	"PE5:TIM15_CH1"     	:	4,
+	"PE6:DCMI_D7"       	:	13,
+	"PE6:TRACED3"		 	:	0,
+	"PE6:FMC_A22"       	:	12,
+	"PE6:LTDC_G1"       	:	14,
+	"PE6:SAI1_D1"       	:	2,
+	"PE6:SAI1_SD_A"     	:	6,
+	"PE6:SAI2_MCLK_B"   	:	10,
+	"PE6:SAI4_D1"       	:	9,
+	"PE6:SAI4_SD_A"     	:	8,
+	"PE6:SPI4_MOSI"     	:	5,
+	"PE6:TIM15_CH2"     	:	4,
+	"PE6:TIM1_BKIN2"    	:	1,
+	"PE6:TIM1_BKIN2_COMP1"	:	11,
+	"PE6:TIM1_BKIN2_COMP2"	:	11,
+	"PE7:DFSDM1_DATIN2" 	:	3,
+	"PE7:FMC_D4"        	:	12,
+	"PE7:FMC_DA4"       	:	12,
+	"PE7:QUADSPI_BK2_IO0"	:	10,
+	"PE7:TIM1_ETR"      	:	1,
+	"PE7:UART7_RX"      	:	7,
+	"PE8:COMP2_OUT"     	:	13,
+	"PE8:DFSDM1_CKIN2"  	:	3,
+	"PE8:FMC_D5"        	:	12,
+	"PE8:FMC_DA5"       	:	12,
+	"PE8:QUADSPI_BK2_IO1"	:	10,
+	"PE8:TIM1_CH1N"     	:	1,
+	"PE8:UART7_TX"      	:	7,
+	"PE9:DFSDM1_CKOUT"  	:	3,
+	"PE9:FMC_D6"        	:	12,
+	"PE9:FMC_DA6"       	:	12,
+	"PE9:QUADSPI_BK2_IO2"	:	10,
+	"PE9:TIM1_CH1"      	:	1,
+	"PE9:UART7_DE"      	:	7,
+	"PE9:UART7_RTS"     	:	7,
+	"PE10:DFSDM1_DATIN4"	:	3,
+	"PE10:FMC_D7"       	:	12,
+	"PE10:FMC_DA7"      	:	12,
+	"PE10:QUADSPI_BK2_IO3"	:	10,
+	"PE10:TIM1_CH2N"    	:	1,
+	"PE10:UART7_CTS"    	:	7,
+	"PE11:DFSDM1_CKIN4" 	:	3,
+	"PE11:FMC_D8"       	:	12,
+	"PE11:FMC_DA8"      	:	12,
+	"PE11:LTDC_G3"      	:	14,
+	"PE11:SAI2_SD_B"    	:	10,
+	"PE11:SPI4_NSS"     	:	5,
+	"PE11:TIM1_CH2"     	:	1,
+	"PE12:COMP1_OUT"    	:	13,
+	"PE12:DFSDM1_DATIN5"	:	3,
+	"PE12:FMC_D9"       	:	12,
+	"PE12:FMC_DA9"      	:	12,
+	"PE12:LTDC_B4"      	:	14,
+	"PE12:SAI2_SCK_B"   	:	10,
+	"PE12:SPI4_SCK"     	:	5,
+	"PE12:TIM1_CH3N"    	:	1,
+	"PE13:COMP2_OUT"    	:	13,
+	"PE13:DFSDM1_CKIN5" 	:	3,
+	"PE13:FMC_D10"      	:	12,
+	"PE13:FMC_DA10"     	:	12,
+	"PE13:LTDC_DE"      	:	14,
+	"PE13:SAI2_FS_B"    	:	10,
+	"PE13:SPI4_MISO"    	:	5,
+	"PE13:TIM1_CH3"     	:	1,
+	"PE14:FMC_D11"      	:	12,
+	"PE14:FMC_DA11"     	:	12,
+	"PE14:LTDC_CLK"     	:	14,
+	"PE14:SAI2_MCLK_B"  	:	10,
+	"PE14:SPI4_MOSI"    	:	5,
+	"PE14:TIM1_CH4"     	:	1,
+	"PE15:FMC_D12"      	:	12,
+	"PE15:FMC_DA12"     	:	12,
+	"PE15:LTDC_R7"      	:	14,
+	"PE15:TIM1_BKIN"    	:	1,
+	"PE15:TIM1_BKIN_COMP1"	:	13,
+	"PE15:TIM1_BKIN_COMP2"	:	13,
+	"PF0:FMC_A0"        	:	12,
+	"PF0:I2C2_SDA"      	:	4,
+	"PF1:FMC_A1"        	:	12,
+	"PF1:I2C2_SCL"      	:	4,
+	"PF2:FMC_A2"        	:	12,
+	"PF2:I2C2_SMBA"     	:	4,
+	"PF3:FMC_A3"        	:	12,
+	"PF4:FMC_A4"        	:	12,
+	"PF5:FMC_A5"        	:	12,
+	"PF6:QUADSPI_BK1_IO3"	:	9,
+	"PF6:SAI1_SD_B"     	:	6,
+	"PF6:SAI4_SD_B"     	:	8,
+	"PF6:SPI5_NSS"      	:	5,
+	"PF6:TIM16_CH1"     	:	1,
+	"PF6:UART7_RX"      	:	7,
+	"PF7:QUADSPI_BK1_IO2"	:	9,
+	"PF7:SAI1_MCLK_B"   	:	6,
+	"PF7:SAI4_MCLK_B"   	:	8,
+	"PF7:SPI5_SCK"      	:	5,
+	"PF7:TIM17_CH1"     	:	1,
+	"PF7:UART7_TX"      	:	7,
+	"PF8:QUADSPI_BK1_IO0"	:	10,
+	"PF8:SAI1_SCK_B"    	:	6,
+	"PF8:SAI4_SCK_B"    	:	8,
+	"PF8:SPI5_MISO"     	:	5,
+	"PF8:TIM13_CH1"     	:	9,
+	"PF8:TIM16_CH1N"    	:	1,
+	"PF8:UART7_DE"      	:	7,
+	"PF8:UART7_RTS"     	:	7,
+	"PF9:QUADSPI_BK1_IO1"	:	10,
+	"PF9:SAI1_FS_B"     	:	6,
+	"PF9:SAI4_FS_B"     	:	8,
+	"PF9:SPI5_MOSI"     	:	5,
+	"PF9:TIM14_CH1"     	:	9,
+	"PF9:TIM17_CH1N"    	:	1,
+	"PF9:UART7_CTS"     	:	7,
+	"PF10:DCMI_D11"     	:	13,
+	"PF10:LTDC_DE"      	:	14,
+	"PF10:QUADSPI_CLK"  	:	9,
+	"PF10:SAI1_D3"      	:	2,
+	"PF10:SAI4_D3"      	:	10,
+	"PF10:TIM16_BKIN"   	:	1,
+	"PF11:DCMI_D12"     	:	13,
+	"PF11:FMC_SDNRAS"   	:	12,
+	"PF11:SAI2_SD_B"    	:	10,
+	"PF11:SPI5_MOSI"    	:	5,
+	"PF12:FMC_A6"       	:	12,
+	"PF13:DFSDM1_DATIN6"	:	3,
+	"PF13:FMC_A7"       	:	12,
+	"PF13:I2C4_SMBA"    	:	4,
+	"PF14:DFSDM1_CKIN6" 	:	3,
+	"PF14:FMC_A8"       	:	12,
+	"PF14:I2C4_SCL"     	:	4,
+	"PF15:FMC_A9"       	:	12,
+	"PF15:I2C4_SDA"     	:	4,
+	"PG0:FMC_A10"       	:	12,
+	"PG1:FMC_A11"       	:	12,
+	"PG2:FMC_A12"       	:	12,
+	"PG2:TIM8_BKIN"     	:	3,
+	"PG2:TIM8_BKIN_COMP1"	:	11,
+	"PG2:TIM8_BKIN_COMP2"	:	11,
+	"PG3:FMC_A13"       	:	12,
+	"PG3:TIM8_BKIN2"    	:	3,
+	"PG3:TIM8_BKIN2_COMP1"	:	11,
+	"PG3:TIM8_BKIN2_COMP2"	:	11,
+	"PG4:FMC_A14"       	:	12,
+	"PG4:FMC_BA0"       	:	12,
+	"PG4:TIM1_BKIN2"    	:	1,
+	"PG4:TIM1_BKIN2_COMP1"	:	11,
+	"PG4:TIM1_BKIN2_COMP2"	:	11,
+	"PG5:FMC_A15"       	:	12,
+	"PG5:FMC_BA1"       	:	12,
+	"PG5:TIM1_ETR"      	:	1,
+	"PG6:DCMI_D12"      	:	13,
+	"PG6:FMC_NE3"       	:	12,
+	"PG6:HRTIM_CHE1"    	:	2,
+	"PG6:LTDC_R7"       	:	14,
+	"PG6:QUADSPI_BK1_NCS"	:	10,
+	"PG6:TIM17_BKIN"    	:	1,
+	"PG7:DCMI_D13"      	:	13,
+	"PG7:FMC_INT"       	:	12,
+	"PG7:HRTIM_CHE2"    	:	2,
+	"PG7:LTDC_CLK"      	:	14,
+	"PG7:SAI1_MCLK_A"   	:	6,
+	"PG7:USART6_CK"     	:	7,
+	"PG8:ETH_PPS_OUT"   	:	11,
+	"PG8:FMC_SDCLK"     	:	12,
+	"PG8:LTDC_G7"       	:	14,
+	"PG8:SPDIFRX1_IN2"  	:	8,
+	"PG8:SPI6_NSS"      	:	5,
+	"PG8:TIM8_ETR"      	:	3,
+	"PG8:USART6_DE"     	:	7,
+	"PG8:USART6_RTS"    	:	7,
+	"PG9:DCMI_VSYNC"    	:	13,
+	"PG9:FMC_NCE"       	:	12,
+	"PG9:FMC_NE2"       	:	12,
+	"PG9:I2S1_SDI"      	:	5,
+	"PG9:QUADSPI_BK2_IO2"	:	9,
+	"PG9:SAI2_FS_B"     	:	10,
+	"PG9:SPDIFRX1_IN3"  	:	8,
+	"PG9:SPI1_MISO"     	:	5,
+	"PG9:USART6_RX"     	:	7,
+	"PG10:DCMI_D2"      	:	13,
+	"PG10:FMC_NE3"      	:	12,
+	"PG10:HRTIM_FLT5"   	:	2,
+	"PG10:I2S1_WS"      	:	5,
+	"PG10:LTDC_B2"      	:	14,
+	"PG10:LTDC_G3"      	:	9,
+	"PG10:SAI2_SD_B"    	:	10,
+	"PG10:SPI1_NSS"     	:	5,
+	"PG11:DCMI_D3"      	:	13,
+	"PG11:ETH_TX_EN"    	:	11,
+	"PG11:HRTIM_EEV4"   	:	2,
+	"PG11:I2S1_CK"      	:	5,
+	"PG11:LPTIM1_IN2"   	:	1,
+	"PG11:LTDC_B3"      	:	14,
+	"PG11:SDMMC2_D2"    	:	10,
+	"PG11:SPDIFRX1_IN0" 	:	8,
+	"PG11:SPI1_SCK"     	:	5,
+	"PG12:ETH_TXD1"     	:	11,
+	"PG12:FMC_NE4"      	:	12,
+	"PG12:HRTIM_EEV5"   	:	2,
+	"PG12:LPTIM1_IN1"   	:	1,
+	"PG12:LTDC_B1"      	:	14,
+	"PG12:LTDC_B4"      	:	9,
+	"PG12:SPDIFRX1_IN1" 	:	8,
+	"PG12:SPI6_MISO"    	:	5,
+	"PG12:USART6_DE"    	:	7,
+	"PG12:USART6_RTS"   	:	7,
+	"PG13:TRACED0"			:	0,
+	"PG13:ETH_TXD0"     	:	11,
+	"PG13:FMC_A24"      	:	12,
+	"PG13:HRTIM_EEV10"  	:	2,
+	"PG13:LPTIM1_OUT"   	:	1,
+	"PG13:LTDC_R0"      	:	14,
+	"PG13:SPI6_SCK"     	:	5,
+	"PG13:USART6_CTS"   	:	7,
+	"PG13:USART6_NSS"   	:	7,
+	"PG14:TRACED1"			:	0,
+	"PG14:ETH_TXD1"     	:	11,
+	"PG14:FMC_A25"      	:	12,
+	"PG14:LPTIM1_ETR"   	:	1,
+	"PG14:LTDC_B0"      	:	14,
+	"PG14:QUADSPI_BK2_IO3"	:	9,
+	"PG14:SPI6_MOSI"    	:	5,
+	"PG14:USART6_TX"    	:	7,
+	"PG15:DCMI_D13"     	:	13,
+	"PG15:FMC_SDNCAS"   	:	12,
+	"PG15:USART6_CTS"   	:	7,
+	"PG15:USART6_NSS"   	:	7,
+	"PH2:ETH_CRS"       	:	11,
+	"PH2:FMC_SDCKE0"    	:	12,
+	"PH2:LPTIM1_IN2"    	:	1,
+	"PH2:LTDC_R0"       	:	14,
+	"PH2:QUADSPI_BK2_IO0"	:	9,
+	"PH2:SAI2_SCK_B"    	:	10,
+	"PH3:ETH_COL"       	:	11,
+	"PH3:FMC_SDNE0"     	:	12,
+	"PH3:LTDC_R1"       	:	14,
+	"PH3:QUADSPI_BK2_IO1"	:	9,
+	"PH3:SAI2_MCLK_B"   	:	10,
+	"PH4:I2C2_SCL"      	:	4,
+	"PH4:LTDC_G4"       	:	14,
+	"PH4:LTDC_G5"       	:	9,
+	"PH4:USB_OTG_HS_ULPI_NXT"	:	10,
+	"PH5:FMC_SDNWE"     	:	12,
+	"PH5:I2C2_SDA"      	:	4,
+	"PH5:SPI5_NSS"      	:	5,
+	"PH6:DCMI_D8"       	:	13,
+	"PH6:ETH_RXD2"      	:	11,
+	"PH6:FMC_SDNE1"     	:	12,
+	"PH6:I2C2_SMBA"     	:	4,
+	"PH6:SPI5_SCK"      	:	5,
+	"PH6:TIM12_CH1"     	:	2,
+	"PH7:DCMI_D9"       	:	13,
+	"PH7:ETH_RXD3"      	:	11,
+	"PH7:FMC_SDCKE1"    	:	12,
+	"PH7:I2C3_SCL"      	:	4,
+	"PH7:SPI5_MISO"     	:	5,
+	"PH8:DCMI_HSYNC"    	:	13,
+	"PH8:FMC_D16"       	:	12,
+	"PH8:I2C3_SDA"      	:	4,
+	"PH8:LTDC_R2"       	:	14,
+	"PH8:TIM5_ETR"      	:	2,
+	"PH9:DCMI_D0"       	:	13,
+	"PH9:FMC_D17"       	:	12,
+	"PH9:I2C3_SMBA"     	:	4,
+	"PH9:LTDC_R3"       	:	14,
+	"PH9:TIM12_CH2"     	:	2,
+	"PH10:DCMI_D1"      	:	13,
+	"PH10:FMC_D18"      	:	12,
+	"PH10:I2C4_SMBA"    	:	4,
+	"PH10:LTDC_R4"      	:	14,
+	"PH10:TIM5_CH1"     	:	2,
+	"PH11:DCMI_D2"      	:	13,
+	"PH11:FMC_D19"      	:	12,
+	"PH11:I2C4_SCL"     	:	4,
+	"PH11:LTDC_R5"      	:	14,
+	"PH11:TIM5_CH2"     	:	2,
+	"PH12:DCMI_D3"      	:	13,
+	"PH12:FMC_D20"      	:	12,
+	"PH12:I2C4_SDA"     	:	4,
+	"PH12:LTDC_R6"      	:	14,
+	"PH12:TIM5_CH3"     	:	2,
+	"PH13:FDCAN1_TX"    	:	9,
+	"PH13:FMC_D21"      	:	12,
+	"PH13:LTDC_G2"      	:	14,
+	"PH13:TIM8_CH1N"    	:	3,
+	"PH13:UART4_TX"     	:	8,
+	"PH14:DCMI_D4"      	:	13,
+	"PH14:FDCAN1_RX"    	:	9,
+	"PH14:FMC_D22"      	:	12,
+	"PH14:LTDC_G3"      	:	14,
+	"PH14:TIM8_CH2N"    	:	3,
+	"PH14:UART4_RX"     	:	8,
+	"PH15:DCMI_D11"     	:	13,
+	"PH15:FMC_D23"      	:	12,
+	"PH15:LTDC_G4"      	:	14,
+	"PH15:TIM8_CH3N"    	:	3,
+	"PI0:DCMI_D13"      	:	13,
+	"PI0:FMC_D24"       	:	12,
+	"PI0:I2S2_WS"       	:	5,
+	"PI0:LTDC_G5"       	:	14,
+	"PI0:SPI2_NSS"      	:	5,
+	"PI0:TIM5_CH4"      	:	2,
+	"PI1:DCMI_D8"       	:	13,
+	"PI1:FMC_D25"       	:	12,
+	"PI1:I2S2_CK"       	:	5,
+	"PI1:LTDC_G6"       	:	14,
+	"PI1:SPI2_SCK"      	:	5,
+	"PI1:TIM8_BKIN2"    	:	3,
+	"PI1:TIM8_BKIN2_COMP1"	:	11,
+	"PI1:TIM8_BKIN2_COMP2"	:	11,
+	"PI2:DCMI_D9"       	:	13,
+	"PI2:FMC_D26"       	:	12,
+	"PI2:I2S2_SDI"      	:	5,
+	"PI2:LTDC_G7"       	:	14,
+	"PI2:SPI2_MISO"     	:	5,
+	"PI2:TIM8_CH4"      	:	3,
+	"PI3:DCMI_D10"      	:	13,
+	"PI3:FMC_D27"       	:	12,
+	"PI3:I2S2_SDO"      	:	5,
+	"PI3:SPI2_MOSI"     	:	5,
+	"PI3:TIM8_ETR"      	:	3,
+	"PI4:DCMI_D5"       	:	13,
+	"PI4:FMC_NBL2"      	:	12,
+	"PI4:LTDC_B4"       	:	14,
+	"PI4:SAI2_MCLK_A"   	:	10,
+	"PI4:TIM8_BKIN"     	:	3,
+	"PI4:TIM8_BKIN_COMP1"	:	11,
+	"PI4:TIM8_BKIN_COMP2"	:	11,
+	"PI5:DCMI_VSYNC"    	:	13,
+	"PI5:FMC_NBL3"      	:	12,
+	"PI5:LTDC_B5"       	:	14,
+	"PI5:SAI2_SCK_A"    	:	10,
+	"PI5:TIM8_CH1"      	:	3,
+	"PI6:DCMI_D6"       	:	13,
+	"PI6:FMC_D28"       	:	12,
+	"PI6:LTDC_B6"       	:	14,
+	"PI6:SAI2_SD_A"     	:	10,
+	"PI6:TIM8_CH2"      	:	3,
+	"PI7:DCMI_D7"       	:	13,
+	"PI7:FMC_D29"       	:	12,
+	"PI7:LTDC_B7"       	:	14,
+	"PI7:SAI2_FS_A"     	:	10,
+	"PI7:TIM8_CH3"      	:	3,
+	"PI9:FDCAN1_RX"     	:	9,
+	"PI9:FMC_D30"       	:	12,
+	"PI9:LTDC_VSYNC"    	:	14,
+	"PI9:UART4_RX"      	:	8,
+	"PI10:ETH_RX_ER"    	:	11,
+	"PI10:FMC_D31"      	:	12,
+	"PI10:LTDC_HSYNC"   	:	14,
+	"PI11:LTDC_G6"      	:	9,
+	"PI11:USB_OTG_HS_ULPI_DIR"	:	10,
+	"PI12:LTDC_HSYNC"   	:	14,
+	"PI13:LTDC_VSYNC"   	:	14,
+	"PI14:LTDC_CLK"     	:	14,
+	"PI15:LTDC_G2"      	:	9,
+	"PI15:LTDC_R0"      	:	14,
+	"PJ0:LTDC_R1"       	:	14,
+	"PJ0:LTDC_R7"       	:	9,
+	"PJ1:LTDC_R2"       	:	14,
+	"PJ2:LTDC_R3"       	:	14,
+	"PJ3:LTDC_R4"       	:	14,
+	"PJ4:LTDC_R5"       	:	14,
+	"PJ5:LTDC_R6"       	:	14,
+	"PJ6:LTDC_R7"       	:	14,
+	"PJ6:TIM8_CH2"      	:	3,
+	"PJ7:TRGIN"  		 	:	0,
+	"PJ7:LTDC_G0"       	:	14,
+	"PJ7:TIM8_CH2N"     	:	3,
+	"PJ8:LTDC_G1"       	:	14,
+	"PJ8:TIM1_CH3N"     	:	1,
+	"PJ8:TIM8_CH1"      	:	3,
+	"PJ8:UART8_TX"      	:	8,
+	"PJ9:LTDC_G2"       	:	14,
+	"PJ9:TIM1_CH3"      	:	1,
+	"PJ9:TIM8_CH1N"     	:	3,
+	"PJ9:UART8_RX"      	:	8,
+	"PJ10:LTDC_G3"      	:	14,
+	"PJ10:SPI5_MOSI"    	:	5,
+	"PJ10:TIM1_CH2N"    	:	1,
+	"PJ10:TIM8_CH2"     	:	3,
+	"PJ11:LTDC_G4"      	:	14,
+	"PJ11:SPI5_MISO"    	:	5,
+	"PJ11:TIM1_CH2"     	:	1,
+	"PJ11:TIM8_CH2N"    	:	3,
+	"PJ12:TRGOUT" 			:	0,
+	"PJ12:LTDC_B0"      	:	14,
+	"PJ12:LTDC_G3"      	:	9,
+	"PJ13:LTDC_B1"      	:	14,
+	"PJ13:LTDC_B4"      	:	9,
+	"PJ14:LTDC_B2"      	:	14,
+	"PJ15:LTDC_B3"      	:	14,
+	"PK0:LTDC_G5"       	:	14,
+	"PK0:SPI5_SCK"      	:	5,
+	"PK0:TIM1_CH1N"     	:	1,
+	"PK0:TIM8_CH3"      	:	3,
+	"PK1:LTDC_G6"       	:	14,
+	"PK1:SPI5_NSS"      	:	5,
+	"PK1:TIM1_CH1"      	:	1,
+	"PK1:TIM8_CH3N"     	:	3,
+	"PK2:LTDC_G7"       	:	14,
+	"PK2:TIM1_BKIN"     	:	1,
+	"PK2:TIM1_BKIN_COMP1"	:	11,
+	"PK2:TIM1_BKIN_COMP2"	:	11,
+	"PK2:TIM8_BKIN"     	:	3,
+	"PK2:TIM8_BKIN_COMP1"	:	10,
+	"PK2:TIM8_BKIN_COMP2"	:	10,
+	"PK3:LTDC_B4"       	:	14,
+	"PK4:LTDC_B5"       	:	14,
+	"PK5:LTDC_B6"       	:	14,
+	"PK6:LTDC_B7"       	:	14,
+	"PK7:LTDC_DE"       	:	14,
+}
+
+
+ADC1_map = {
+    # format is PIN : ADC1_CHAN
+    "PF11"  :   2,
+    "PA6"	:	3,
+    "PC4"	:	4,
+    "PB1"	:	5,
+    "PF12"  :   6,
+    "PA7"	:	7,
+    "PC5"	:	8,
+    "PB0"	:	9,
+	"PC0"	:	10,
+	"PC1"	:	11,
+	"PC2"	:	12,
+    "PC3"	:	13,
+    "PA2"	:	14,
+    "PA3"	:	15,
+    "PA0"	:	16,
+    "PA1"	:	17,
+    "PA4"	:	18,
+    "PA5"	:	19,
+}
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H757xx.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H757xx.py
index cf4ca61bad1..c5db294e439 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H757xx.py
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/STM32H757xx.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 '''
-these tables are generated from the STM32 datasheets for the STM32H743bi
+these tables are generated from the STM32 datasheets for the STM32H757
 '''
 
 # additional build information for ChibiOS
@@ -14,18 +14,52 @@ mcu = {
     # location of MCU serial number
     'UDID_START' : 0x1FF1E800,
 
+    # DMA peripheral capabilities:
+    # - can't use ITCM or DTCM for any DMA
+    # - SPI1 to SPI5 can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 for DMA
+    # - SPI6, I2C4 and ADC3 can use SRAM4 on BDMA
+    # - UARTS can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 for DMA
+    # - I2C1, I2C2 and I2C3 can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 with DMA
+    # - timers can use AXI SRAM, SRAM1 to SRAM3 and SRAM4 with DMA
+    # - ADC12 can use AXI SRAM, SRAM1 to SRAM3 and SRAM4
+    # - SDMMC can use AXI SRAM, SRAM1 to SRAM3 with IDMA (cannot use SRAM4)
+
     # ram map, as list of (address, size-kb, flags)
     # flags of 1 means DMA-capable (DMA and BDMA)
     # flags of 2 means faster memory for CPU intensive work
     # flags of 4 means memory can be used for SDMMC DMA
     'RAM_MAP' : [
-        (0x30000000, 288, 0), # SRAM1, SRAM2, SRAM3
+        (0x30000000, 256, 0), # SRAM1, SRAM2
         (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
-        (0x38000000,  64, 1), # SRAM4. This supports both DMA and BDMA ops
         (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
+        (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
+        (0x30040000,  32, 0), # SRAM3.
+        (0x38000000,  64, 1), # SRAM4.
     ],
 
-    'INSTRUCTION_RAM' : (0x00000400, 63), # ITCM (first 1k removed, to keep address 0 unused)
+    'RAM_MAP_EXTERNAL_FLASH' : [
+		# SSBL checks that stack is in this region so needs to come first
+        (0x30000000, 256, 0), # SRAM1, SRAM2
+        (0x20000000,  64, 2), # DTCM, tightly coupled, no DMA, fast
+        (0x24000000, 128, 4), # AXI SRAM. Use this for SDMMC IDMA ops
+        (0x30040000,  32, 0), # SRAM3.
+        (0x38000000,  64, 1), # SRAM4.
+    ],
+    'INSTRUCTION_RAM' : (0x00000400,  63), # ITCM (first 1k removed, to keep address 0 unused)
+    'FLASH_RAM' : 		(0x24020000, 384), # AXI SRAM used for process stack and ram functions
+    'DATA_RAM' :        (0x20010000,  64), # DTCM, tightly coupled, no DMA, fast
+
+	# avoid a problem in the bootloader by making DTCM first. The DCache init
+    # when using SRAM1 as primary memory gets a hard fault in bootloader
+    # we can't use DTCM first for main firmware as some builds overflow the first segment
+    'RAM_MAP_BOOTLOADER' : [
+        (0x20000000, 128, 2), # DTCM, tightly coupled, no DMA, fast
+        (0x30000000, 256, 0), # SRAM1, SRAM2
+        (0x24000000, 512, 4), # AXI SRAM. Use this for SDMMC IDMA ops
+        (0x00000400,  63, 2), # ITCM (first 1k removed, to keep address 0 unused)
+        (0x30040000,  32, 0), # SRAM3.
+        (0x38000000,  64, 1), # SRAM4.
+    ],
 
     'EXPECTED_CLOCK' : 400000000,
 
diff --git a/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py b/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
index fb63d27fbd6..5a7dfcff13b 100644
--- a/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
+++ b/libraries/AP_HAL_ChibiOS/hwdef/scripts/chibios_hwdef.py
@@ -705,6 +705,10 @@ def get_ram_map():
         ram_map = get_mcu_config('RAM_MAP_BOOTLOADER', False)
         if ram_map is not None:
             return ram_map
+    elif env_vars['EXT_FLASH_SIZE_MB']:
+        ram_map = get_mcu_config('RAM_MAP_EXTERNAL_FLASH', False)
+        if ram_map is not None:
+            return ram_map
     return get_mcu_config('RAM_MAP', True)
 
 def get_flash_pages_sizes():
@@ -905,21 +909,29 @@ def write_mcu_config(f):
     flash_size = get_config('FLASH_SIZE_KB', type=int)
     f.write('#define BOARD_FLASH_SIZE %u\n' % flash_size)
     env_vars['BOARD_FLASH_SIZE'] = flash_size
-    f.write('#define CRT1_AREAS_NUMBER 1\n')
 
     flash_reserve_start = get_config(
         'FLASH_RESERVE_START_KB', default=16, type=int)
     f.write('\n// location of loaded firmware\n')
     f.write('#define FLASH_LOAD_ADDRESS 0x%08x\n' % (0x08000000 + flash_reserve_start*1024))
-    f.write('#define EXTERNAL_PROG_FLASH_MB %u\n' % get_config('EXTERNAL_PROG_FLASH_MB', default=0, type=int))
+    # can be no persistent parameters if no space allocated for them
+    if not args.bootloader and flash_reserve_start == 0:
+        f.write('#define HAL_ENABLE_SAVE_PERSISTENT_PARAMS 0\n')
 
-    env_vars['EXTERNAL_PROG_FLASH_MB'] = get_config('EXTERNAL_PROG_FLASH_MB', default=0, type=int)
+    f.write('#define EXT_FLASH_SIZE_MB %u\n' % get_config('EXT_FLASH_SIZE_MB', default=0, type=int))
+    f.write('#define EXT_FLASH_RESERVE_START_KB %u\n' % get_config('EXT_FLASH_RESERVE_START_KB', default=0, type=int))
+    f.write('#define EXT_FLASH_RESERVE_END_KB %u\n' % get_config('EXT_FLASH_RESERVE_END_KB', default=0, type=int))
 
-    if env_vars['EXTERNAL_PROG_FLASH_MB'] and not args.bootloader:
+    env_vars['EXT_FLASH_SIZE_MB'] = get_config('EXT_FLASH_SIZE_MB', default=0, type=int)
+
+    if env_vars['EXT_FLASH_SIZE_MB'] and not args.bootloader:
+        f.write('#define CRT1_AREAS_NUMBER 3\n')
         f.write('#define CRT1_RAMFUNC_ENABLE TRUE\n') # this will enable loading program sections to RAM
-        f.write('#define __RAMFUNC__ __attribute__ ((long_call, __section__(".ramfunc")))\n')
-        f.write('#define PORT_IRQ_ATTRIBUTES __RAMFUNC__\n')
+        f.write('#define __FASTRAMFUNC__ __attribute__ ((__section__(".fastramfunc")))\n')
+        f.write('#define __RAMFUNC__ __attribute__ ((__section__(".ramfunc")))\n')
+        f.write('#define PORT_IRQ_ATTRIBUTES __FASTRAMFUNC__\n')
     else:
+        f.write('#define CRT1_AREAS_NUMBER 1\n')
         f.write('#define CRT1_RAMFUNC_ENABLE FALSE\n')
 
     storage_flash_page = get_storage_flash_page()
@@ -940,8 +952,10 @@ def write_mcu_config(f):
         env_vars['ENABLE_CRASHDUMP'] = 0
 
     if args.bootloader:
-        if env_vars['EXTERNAL_PROG_FLASH_MB']:
-            f.write('#define APP_START_ADDRESS 0x90000000\n')
+        if env_vars['EXT_FLASH_SIZE_MB']:
+            f.write('\n// location of loaded firmware in external flash\n')
+            f.write('#define APP_START_ADDRESS 0x%08x\n' % (0x90000000 + get_config(
+                'EXT_FLASH_RESERVE_START_KB', default=0, type=int)*1024))
             f.write('#define BOOT_FROM_EXT_FLASH 1\n')
         f.write('#define FLASH_BOOTLOADER_LOAD_KB %u\n' % get_config('FLASH_BOOTLOADER_LOAD_KB', type=int))
         f.write('#define FLASH_RESERVE_END_KB %u\n' % get_config('FLASH_RESERVE_END_KB', default=0, type=int))
@@ -1053,7 +1067,6 @@ def write_mcu_config(f):
 #define HAL_USE_I2C FALSE
 #define HAL_USE_PWM FALSE
 #define CH_DBG_ENABLE_STACK_CHECK FALSE
-#define CH_CFG_USE_DYNAMIC FALSE
 // avoid timer and RCIN threads to save memory
 #define HAL_NO_TIMER_THREAD
 #define HAL_NO_RCOUT_THREAD
@@ -1074,12 +1087,13 @@ def write_mcu_config(f):
 #endif
 #define HAL_USE_RTC FALSE
 #define DISABLE_SERIAL_ESC_COMM TRUE
+#define CH_CFG_USE_DYNAMIC FALSE
 ''')
-        if not env_vars['EXTERNAL_PROG_FLASH_MB']:
+        if not env_vars['EXT_FLASH_SIZE_MB']:
             f.write('''
-#define CH_CFG_USE_HEAP FALSE
-#define CH_CFG_USE_SEMAPHORES FALSE
 #define CH_CFG_USE_MEMCORE FALSE
+#define CH_CFG_USE_SEMAPHORES FALSE
+#define CH_CFG_USE_HEAP FALSE
 ''')
     if env_vars.get('ROMFS_UNCOMPRESSED', False):
         f.write('#define HAL_ROMFS_UNCOMPRESSED\n')
@@ -1114,20 +1128,47 @@ def write_ldscript(fname):
     # space to reserve for storage at end of flash
     flash_reserve_end = get_config('FLASH_RESERVE_END_KB', default=0, type=int)
 
+    # space to reserve for bootloader and storage at start of external flash
+    ext_flash_reserve_start = get_config(
+        'EXT_FLASH_RESERVE_START_KB', default=0, type=int)
+    env_vars['EXT_FLASH_RESERVE_START_KB'] = str(ext_flash_reserve_start)
+
+    # space to reserve for storage at end of flash
+    ext_flash_reserve_end = get_config('EXT_FLASH_RESERVE_END_KB', default=0, type=int)
+
     # ram layout
     ram_map = get_ram_map()
     instruction_ram = get_mcu_config('INSTRUCTION_RAM', False)
 
     flash_base = 0x08000000 + flash_reserve_start * 1024
-    ext_flash_base = 0x90000000
+    ext_flash_base = 0x90000000 + ext_flash_reserve_start * 1024
     if instruction_ram is not None:
         instruction_ram_base = instruction_ram[0]
         instruction_ram_length = instruction_ram[1]
 
+    ram1_start = 0
+    ram1_len = 0
+    flash_ram = get_mcu_config('FLASH_RAM', False)
+    if flash_ram is not None:
+        ram1_start = flash_ram[0]
+        ram1_len = flash_ram[1] * 1024
+
+    ram2_start = 0
+    ram2_len = 0
+    data_ram = get_mcu_config('DATA_RAM', False)
+    if data_ram is not None:
+        ram2_start = data_ram[0]
+        ram2_len = data_ram[1] * 1024
+
+    # get external flash if any
+    ext_flash_size = get_config('EXT_FLASH_SIZE_MB', default=0, type=int)
+
     if not args.bootloader:
         flash_length = flash_size - (flash_reserve_start + flash_reserve_end)
+        ext_flash_length = ext_flash_size * 1024 - (ext_flash_reserve_start + ext_flash_reserve_end)
     else:
         flash_length = min(flash_size, get_config('FLASH_BOOTLOADER_LOAD_KB', type=int))
+        ext_flash_length = 0
 
     env_vars['FLASH_TOTAL'] = flash_length * 1024
 
@@ -1140,7 +1181,6 @@ def write_ldscript(fname):
     ram_reserve_start = get_ram_reserve_start()
     ram0_start += ram_reserve_start
     ram0_len -= ram_reserve_start
-    ext_flash_length = get_config('EXTERNAL_PROG_FLASH_MB', default=0, type=int)
     if ext_flash_length == 0 or args.bootloader:
         env_vars['HAS_EXTERNAL_FLASH_SECTIONS'] = 0
         f.write('''/* generated ldscript.ld */
@@ -1153,25 +1193,29 @@ MEMORY
 INCLUDE common.ld
 ''' % (flash_base, flash_length, ram0_start, ram0_len))
     else:
-        if ext_flash_length > 32:
+        if ext_flash_size > 32:
             error("We only support 24bit addressing over external flash")
         env_vars['HAS_EXTERNAL_FLASH_SECTIONS'] = 1
         f.write('''/* generated ldscript.ld */
 MEMORY
 {
-    default_flash : org = 0x%08x, len = %uM
+    default_flash (rx) : org = 0x%08x, len = %uK
     instram : org = 0x%08x, len = %uK
     ram0  : org = 0x%08x, len = %u
+    ram1  : org = 0x%08x, len = %u
+    ram2  : org = 0x%08x, len = %u
 }
 
 INCLUDE common_extf.ld
 ''' % (ext_flash_base, ext_flash_length,
        instruction_ram_base, instruction_ram_length,
-       ram0_start, ram0_len))
+       ram0_start, ram0_len,
+       ram1_start, ram1_len,
+       ram2_start, ram2_len))
 
 def copy_common_linkerscript(outdir):
     dirpath = os.path.dirname(os.path.realpath(__file__))
-    if not get_config('EXTERNAL_PROG_FLASH_MB', default=0, type=int) or args.bootloader:
+    if not get_config('EXT_FLASH_SIZE_MB', default=0, type=int) or args.bootloader:
         shutil.copy(os.path.join(dirpath, "../common/common.ld"),
                     os.path.join(outdir, "common.ld"))
     else:
diff --git a/libraries/AP_HAL_ChibiOS/sdcard.cpp b/libraries/AP_HAL_ChibiOS/sdcard.cpp
index 7e02243000f..6caafa4cf9c 100644
--- a/libraries/AP_HAL_ChibiOS/sdcard.cpp
+++ b/libraries/AP_HAL_ChibiOS/sdcard.cpp
@@ -197,7 +197,7 @@ void spiStopHook(SPIDriver *spip)
 {
 }
 
-void spiSelectHook(SPIDriver *spip)
+__RAMFUNC__ void spiSelectHook(SPIDriver *spip)
 {
     if (sdcard_running) {
         device->get_semaphore()->take_blocking();
@@ -205,7 +205,7 @@ void spiSelectHook(SPIDriver *spip)
     }
 }
 
-void spiUnselectHook(SPIDriver *spip)
+__RAMFUNC__ void spiUnselectHook(SPIDriver *spip)
 {
     if (sdcard_running) {
         device->set_chip_select(false);
@@ -220,14 +220,14 @@ void spiIgnoreHook(SPIDriver *spip, size_t n)
     }
 }
 
-void spiSendHook(SPIDriver *spip, size_t n, const void *txbuf)
+__RAMFUNC__ void spiSendHook(SPIDriver *spip, size_t n, const void *txbuf)
 {
     if (sdcard_running) {
         device->transfer((const uint8_t *)txbuf, n, nullptr, 0);
     }
 }
 
-void spiReceiveHook(SPIDriver *spip, size_t n, void *rxbuf)
+__RAMFUNC__ void spiReceiveHook(SPIDriver *spip, size_t n, void *rxbuf)
 {
     if (sdcard_running) {
         device->transfer(nullptr, 0, (uint8_t *)rxbuf, n);
diff --git a/libraries/AP_HAL_ChibiOS/system.cpp b/libraries/AP_HAL_ChibiOS/system.cpp
index 65f3a2bb7e0..b4b3b3b4c7d 100644
--- a/libraries/AP_HAL_ChibiOS/system.cpp
+++ b/libraries/AP_HAL_ChibiOS/system.cpp
@@ -272,7 +272,7 @@ void panic(const char *errormsg, ...)
 #endif
 }
 
-uint32_t micros()
+__FASTRAMFUNC__ uint32_t micros()
 {
 #if CH_CFG_ST_RESOLUTION == 32 && CH_CFG_ST_FREQUENCY==1000000U
     // special case optimisation for 32 bit timers
@@ -293,48 +293,48 @@ uint16_t micros16()
 #endif
 }
     
-uint32_t millis()
+__FASTRAMFUNC__ uint32_t millis()
 {
     return hrt_millis32();
 }
 
-uint16_t millis16()
+__FASTRAMFUNC__ uint16_t millis16()
 {
     return hrt_millis32() & 0xFFFF;
 }
 
-uint64_t micros64()
+__FASTRAMFUNC__ uint64_t micros64()
 {
     return hrt_micros64();
 }
 
-uint64_t millis64()
+__FASTRAMFUNC__ uint64_t millis64()
 {
     return hrt_micros64() / 1000U;
 }
 
 
-uint32_t native_micros()
+__FASTRAMFUNC__ uint32_t native_micros()
 {
     return micros();
 }
 
-uint32_t native_millis()
+__FASTRAMFUNC__ uint32_t native_millis()
 {
     return millis();
 }
 
-uint16_t native_millis16()
+__FASTRAMFUNC__ uint16_t native_millis16()
 {
     return millis16();
 }
 
-uint64_t native_micros64()
+__FASTRAMFUNC__ uint64_t native_micros64()
 {
     return micros64();
 }
 
-uint64_t native_millis64()
+__FASTRAMFUNC__ uint64_t native_millis64()
 {
     return millis64();
 }